ATE239254T1 - Cache-speicherbetrieb - Google Patents

Cache-speicherbetrieb

Info

Publication number
ATE239254T1
ATE239254T1 AT98952911T AT98952911T ATE239254T1 AT E239254 T1 ATE239254 T1 AT E239254T1 AT 98952911 T AT98952911 T AT 98952911T AT 98952911 T AT98952911 T AT 98952911T AT E239254 T1 ATE239254 T1 AT E239254T1
Authority
AT
Austria
Prior art keywords
cache
data
processor
determining
storage operation
Prior art date
Application number
AT98952911T
Other languages
English (en)
Inventor
David Russell Milway
Fash Nowashdi
Original Assignee
Virata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Virata Ltd filed Critical Virata Ltd
Application granted granted Critical
Publication of ATE239254T1 publication Critical patent/ATE239254T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT98952911T 1997-11-13 1998-11-11 Cache-speicherbetrieb ATE239254T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9724031.1A GB9724031D0 (en) 1997-11-13 1997-11-13 Cache memory operation
PCT/GB1998/003377 WO1999026142A1 (en) 1997-11-13 1998-11-11 Cache memory operation

Publications (1)

Publication Number Publication Date
ATE239254T1 true ATE239254T1 (de) 2003-05-15

Family

ID=10822039

Family Applications (1)

Application Number Title Priority Date Filing Date
AT98952911T ATE239254T1 (de) 1997-11-13 1998-11-11 Cache-speicherbetrieb

Country Status (8)

Country Link
US (1) US6470428B1 (de)
EP (1) EP1029280B1 (de)
AT (1) ATE239254T1 (de)
AU (1) AU1045399A (de)
DE (1) DE69814137T2 (de)
GB (1) GB9724031D0 (de)
IL (1) IL135044A (de)
WO (1) WO1999026142A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
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US7240157B2 (en) * 2001-09-26 2007-07-03 Ati Technologies, Inc. System for handling memory requests and method thereof
US7143243B2 (en) * 2003-05-29 2006-11-28 Via-Cyrix, Inc. Tag array access reduction in a cache memory
US20050071570A1 (en) * 2003-09-26 2005-03-31 Takasugl Robin Alexis Prefetch controller for controlling retrieval of data from a data storage device
US7120706B2 (en) * 2003-10-31 2006-10-10 Lucent Technologies Inc. Contention resolution in a memory management system
US7730531B2 (en) * 2005-04-15 2010-06-01 Microsoft Corporation System and method for detection of artificially generated system load
US7616218B1 (en) * 2005-12-05 2009-11-10 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives
US8601223B1 (en) 2006-09-19 2013-12-03 Nvidia Corporation Techniques for servicing fetch requests utilizing coalesing page table entries
US8543792B1 (en) 2006-09-19 2013-09-24 Nvidia Corporation Memory access techniques including coalesing page table entries
US8352709B1 (en) 2006-09-19 2013-01-08 Nvidia Corporation Direct memory access techniques that include caching segmentation data
US8347064B1 (en) 2006-09-19 2013-01-01 Nvidia Corporation Memory access techniques in an aperture mapped memory space
US8707011B1 (en) 2006-10-24 2014-04-22 Nvidia Corporation Memory access techniques utilizing a set-associative translation lookaside buffer
US8700883B1 (en) 2006-10-24 2014-04-15 Nvidia Corporation Memory access techniques providing for override of a page table
US8533425B1 (en) 2006-11-01 2013-09-10 Nvidia Corporation Age based miss replay system and method
US8347065B1 (en) 2006-11-01 2013-01-01 Glasco David B System and method for concurrently managing memory access requests
US8706975B1 (en) 2006-11-01 2014-04-22 Nvidia Corporation Memory access management block bind system and method
US8607008B1 (en) 2006-11-01 2013-12-10 Nvidia Corporation System and method for independent invalidation on a per engine basis
US8504794B1 (en) 2006-11-01 2013-08-06 Nvidia Corporation Override system and method for memory access management
US8700865B1 (en) 2006-11-02 2014-04-15 Nvidia Corporation Compressed data access system and method
JP2008257508A (ja) * 2007-04-05 2008-10-23 Nec Electronics Corp キャッシュ制御方法およびキャッシュ装置並びにマイクロコンピュータ
US8464002B2 (en) * 2009-10-14 2013-06-11 Board Of Regents Of The University Of Texas System Burst-based cache dead block prediction
US10146545B2 (en) * 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US8880476B2 (en) * 2012-06-28 2014-11-04 International Business Machines Corporation Low-overhead enhancement of reliability of journaled file system using solid state storage and de-duplication
US20140189310A1 (en) 2012-12-27 2014-07-03 Nvidia Corporation Fault detection in instruction translations
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125748A (ja) * 1990-09-18 1992-04-27 Fujitsu Ltd キャッシュメモリ制御方式
US5625793A (en) 1991-04-15 1997-04-29 International Business Machines Corporation Automatic cache bypass for instructions exhibiting poor cache hit ratio
US5423016A (en) 1992-02-24 1995-06-06 Unisys Corporation Block buffer for instruction/operand caches
JP3194201B2 (ja) 1992-02-24 2001-07-30 株式会社日立製作所 キャッシュモード選択方法
GB2273181A (en) 1992-12-02 1994-06-08 Ibm Cache/non-cache access control.
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
EP0782079A1 (de) 1995-12-18 1997-07-02 Texas Instruments Incorporated Stoss-Zugriff in Datenverarbeitungssystemen

Also Published As

Publication number Publication date
AU1045399A (en) 1999-06-07
DE69814137D1 (de) 2003-06-05
DE69814137T2 (de) 2004-03-18
EP1029280A1 (de) 2000-08-23
WO1999026142A1 (en) 1999-05-27
IL135044A (en) 2004-06-20
EP1029280B1 (de) 2003-05-02
IL135044A0 (en) 2001-05-20
US6470428B1 (en) 2002-10-22
GB9724031D0 (en) 1998-01-14

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