ATE231307T1 - Skalierbare architektur für programmierbare logische vorrichtungen mit hoher dichte und zweiebenigen hierarchischen verbindungsresourcen - Google Patents

Skalierbare architektur für programmierbare logische vorrichtungen mit hoher dichte und zweiebenigen hierarchischen verbindungsresourcen

Info

Publication number
ATE231307T1
ATE231307T1 AT00941247T AT00941247T ATE231307T1 AT E231307 T1 ATE231307 T1 AT E231307T1 AT 00941247 T AT00941247 T AT 00941247T AT 00941247 T AT00941247 T AT 00941247T AT E231307 T1 ATE231307 T1 AT E231307T1
Authority
AT
Austria
Prior art keywords
slb
segment
ssm
gsm
global
Prior art date
Application number
AT00941247T
Other languages
English (en)
Inventor
Om P Agrawal
Claudia A Stanley
Xiaojie Warren He
Larry R Metzger
Robert A Simon
Kerry A Ilgenstein
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Application granted granted Critical
Publication of ATE231307T1 publication Critical patent/ATE231307T1/de

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT00941247T 1999-06-06 2000-06-06 Skalierbare architektur für programmierbare logische vorrichtungen mit hoher dichte und zweiebenigen hierarchischen verbindungsresourcen ATE231307T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/326,940 US6184713B1 (en) 1999-06-06 1999-06-06 Scalable architecture for high density CPLDS having two-level hierarchy of routing resources
PCT/US2000/015596 WO2000076072A1 (en) 1999-06-06 2000-06-06 SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES

Publications (1)

Publication Number Publication Date
ATE231307T1 true ATE231307T1 (de) 2003-02-15

Family

ID=23274432

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00941247T ATE231307T1 (de) 1999-06-06 2000-06-06 Skalierbare architektur für programmierbare logische vorrichtungen mit hoher dichte und zweiebenigen hierarchischen verbindungsresourcen

Country Status (6)

Country Link
US (2) US6184713B1 (de)
EP (1) EP1188241B1 (de)
AT (1) ATE231307T1 (de)
AU (1) AU5597600A (de)
DE (1) DE60001237D1 (de)
WO (1) WO2000076072A1 (de)

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Also Published As

Publication number Publication date
US6184713B1 (en) 2001-02-06
AU5597600A (en) 2000-12-28
DE60001237D1 (de) 2003-02-20
EP1188241B1 (de) 2003-01-15
EP1188241A1 (de) 2002-03-20
US6348813B1 (en) 2002-02-19
WO2000076072A1 (en) 2000-12-14

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