DE60322757D1 - Nutzung eines nicht benötigten Eingangs/Ausgangsblocks für die zentralen logische Funktionen - Google Patents

Nutzung eines nicht benötigten Eingangs/Ausgangsblocks für die zentralen logische Funktionen

Info

Publication number
DE60322757D1
DE60322757D1 DE60322757T DE60322757T DE60322757D1 DE 60322757 D1 DE60322757 D1 DE 60322757D1 DE 60322757 T DE60322757 T DE 60322757T DE 60322757 T DE60322757 T DE 60322757T DE 60322757 D1 DE60322757 D1 DE 60322757D1
Authority
DE
Germany
Prior art keywords
output block
logic functions
central logic
unnecessary input
unnecessary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60322757T
Other languages
English (en)
Inventor
Rajat Chauhan
Rajesh Kaushik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sicronic Remote KG LLC
Original Assignee
Sicronic Remote KG LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sicronic Remote KG LLC filed Critical Sicronic Remote KG LLC
Application granted granted Critical
Publication of DE60322757D1 publication Critical patent/DE60322757D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE60322757T 2002-01-17 2003-01-02 Nutzung eines nicht benötigten Eingangs/Ausgangsblocks für die zentralen logische Funktionen Expired - Lifetime DE60322757D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN35DE2002 2002-01-17

Publications (1)

Publication Number Publication Date
DE60322757D1 true DE60322757D1 (de) 2008-09-25

Family

ID=11097022

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60322757T Expired - Lifetime DE60322757D1 (de) 2002-01-17 2003-01-02 Nutzung eines nicht benötigten Eingangs/Ausgangsblocks für die zentralen logische Funktionen

Country Status (3)

Country Link
US (1) US7157936B2 (de)
EP (2) EP1968193B1 (de)
DE (1) DE60322757D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6980026B1 (en) * 2003-12-16 2005-12-27 Xilinx, Inc. Structures and methods for reducing power consumption in programmable logic devices
US7622947B1 (en) * 2003-12-18 2009-11-24 Nvidia Corporation Redundant circuit presents connections on specified I/O ports
US7376929B1 (en) * 2004-11-10 2008-05-20 Xilinx, Inc. Method and apparatus for providing a protection circuit for protecting an integrated circuit design
US7939856B2 (en) * 2004-12-31 2011-05-10 Stmicroelectronics Pvt. Ltd. Area-efficient distributed device structure for integrated voltage regulators
JP4442523B2 (ja) * 2005-06-30 2010-03-31 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US7814336B1 (en) 2005-07-12 2010-10-12 Xilinx, Inc. Method and apparatus for protection of time-limited operation of a circuit
ITPI20070063A1 (it) * 2007-05-28 2008-11-29 Donati S R L Macchina per l' esecuzione autonoma di esercizi di fisioterapia.
US7814454B2 (en) * 2007-06-28 2010-10-12 International Business Machines Corporation Selectable device options for characterizing semiconductor devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
JPH04192809A (ja) * 1990-11-27 1992-07-13 Kawasaki Steel Corp プログラマブル集積回路
US5381058A (en) * 1993-05-21 1995-01-10 At&T Corp. FPGA having PFU with programmable output driver inputs
US5869982A (en) * 1995-12-29 1999-02-09 Cypress Semiconductor Corp. Programmable I/O cell with data conversion capability
US5825202A (en) * 1996-09-26 1998-10-20 Xilinx, Inc. Integrated circuit with field programmable and application specific logic areas
US6191611B1 (en) * 1997-10-16 2001-02-20 Altera Corporation Driver circuitry for programmable logic devices with hierarchical interconnection resources
US6184713B1 (en) * 1999-06-06 2001-02-06 Lattice Semiconductor Corporation Scalable architecture for high density CPLDS having two-level hierarchy of routing resources
US6268743B1 (en) * 2000-03-06 2001-07-31 Acatel Corporation Block symmetrization in a field programmable gate array
US6353331B1 (en) * 2000-07-10 2002-03-05 Xilinx, Inc. Complex programmable logic device with lookup table
US6518787B1 (en) * 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US6703860B1 (en) * 2001-12-14 2004-03-09 Lattice Semiconductor Corporation I/O block for a programmable interconnect circuit
US6842039B1 (en) * 2002-10-21 2005-01-11 Altera Corporation Configuration shift register
US6774670B1 (en) * 2002-12-30 2004-08-10 Actel Corporation Intra-tile buffer system for a field programmable gate array
US6888373B2 (en) * 2003-02-11 2005-05-03 Altera Corporation Fracturable incomplete look up table for area efficient logic elements

Also Published As

Publication number Publication date
US20030172363A1 (en) 2003-09-11
US7157936B2 (en) 2007-01-02
EP1968193B1 (de) 2011-07-27
EP1330033B1 (de) 2008-08-13
EP1330033A3 (de) 2006-11-29
EP1968193A3 (de) 2008-12-17
EP1330033A2 (de) 2003-07-23
EP1968193A2 (de) 2008-09-10

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Legal Events

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