ATE123581T1 - Programmierbare zeitsteuerung der datenübertragung. - Google Patents

Programmierbare zeitsteuerung der datenübertragung.

Info

Publication number
ATE123581T1
ATE123581T1 AT89306723T AT89306723T ATE123581T1 AT E123581 T1 ATE123581 T1 AT E123581T1 AT 89306723 T AT89306723 T AT 89306723T AT 89306723 T AT89306723 T AT 89306723T AT E123581 T1 ATE123581 T1 AT E123581T1
Authority
AT
Austria
Prior art keywords
data transmission
transmission time
programmable data
time control
latch
Prior art date
Application number
AT89306723T
Other languages
English (en)
Inventor
Michael A Gagliardo
John J Lynch
James E Tessari
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE123581T1 publication Critical patent/ATE123581T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)
  • Memory System (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
AT89306723T 1989-01-27 1989-07-03 Programmierbare zeitsteuerung der datenübertragung. ATE123581T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/303,624 US5335337A (en) 1989-01-27 1989-01-27 Programmable data transfer timing

Publications (1)

Publication Number Publication Date
ATE123581T1 true ATE123581T1 (de) 1995-06-15

Family

ID=23172954

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89306723T ATE123581T1 (de) 1989-01-27 1989-07-03 Programmierbare zeitsteuerung der datenübertragung.

Country Status (6)

Country Link
US (2) US5335337A (de)
EP (1) EP0379772B1 (de)
JP (1) JP2928866B2 (de)
AT (1) ATE123581T1 (de)
CA (1) CA1321030C (de)
DE (1) DE68922984T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
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GB2256292B (en) * 1991-05-21 1994-11-02 Research Machines Plc A bus timing system of a computer
US5559967A (en) * 1993-03-18 1996-09-24 Apple Computer, Inc. Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independent of the data signal transfers
JP3490131B2 (ja) * 1994-01-21 2004-01-26 株式会社ルネサステクノロジ データ転送制御方法、データプロセッサ及びデータ処理システム
JPH08123717A (ja) * 1994-10-25 1996-05-17 Oki Electric Ind Co Ltd 半導体記憶装置
US5758130A (en) * 1995-08-04 1998-05-26 Apple Computer, Inc. Digital signal distribution for long and short paths
US5805872A (en) * 1995-09-08 1998-09-08 Digital Equipment Corporation Apparatus for generation of control signals from the read cycle rate and read speed of a memory
JP3307807B2 (ja) * 1995-09-29 2002-07-24 三洋電機株式会社 映像信号処理装置
US5802132A (en) * 1995-12-29 1998-09-01 Intel Corporation Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US5834956A (en) 1995-12-29 1998-11-10 Intel Corporation Core clock correction in a 2/N mode clocking scheme
US6092165A (en) * 1996-08-16 2000-07-18 Unisys Corporation Memory control unit using a programmable shift register for generating timed control signals
DE69731066T2 (de) * 1997-01-23 2005-10-06 Hewlett-Packard Development Co., L.P., Houston Speichersteuerungsvorrichtung mit programmierbarer Impulsverzögerung
US6209072B1 (en) * 1997-05-06 2001-03-27 Intel Corporation Source synchronous interface between master and slave using a deskew latch
JPH11328961A (ja) * 1998-05-21 1999-11-30 Fujitsu Ltd 電子回路装置及びインタフェース回路
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
KR20030023295A (ko) * 2001-09-13 2003-03-19 삼성전자주식회사 프로그램이 가능한 인터페이스 신호 조정회로
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US9471094B1 (en) * 2014-12-30 2016-10-18 Cadence Design Systems, Inc. Method of aligning timing of a chip select signal with a cycle of a memory device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IE33526B1 (en) * 1968-08-26 1974-07-24 Wavin Bv Improvements in a method for manufacturing a block bag
US3668650A (en) * 1970-07-23 1972-06-06 Contrologic Inc Single package basic processor unit with synchronous and asynchronous timing control
US4014006A (en) * 1973-08-10 1977-03-22 Data General Corporation Data processing system having a unique cpu and memory tuning relationship and data path configuration
USRE30331E (en) * 1973-08-10 1980-07-08 Data General Corporation Data processing system having a unique CPU and memory timing relationship and data path configuration
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
US4021784A (en) * 1976-03-12 1977-05-03 Sperry Rand Corporation Clock synchronization system
US4095265A (en) * 1976-06-07 1978-06-13 International Business Machines Corporation Memory control structure for a pipelined mini-processor system
US4050097A (en) * 1976-09-27 1977-09-20 Honeywell Information Systems, Inc. Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus
US4153941A (en) * 1976-11-11 1979-05-08 Kearney & Trecker Corporation Timing circuit and method for controlling the operation of cyclical devices
US4079456A (en) * 1977-01-24 1978-03-14 Rca Corporation Output buffer synchronizing circuit having selectively variable delay means
US4124890A (en) * 1977-06-20 1978-11-07 Vasenkov Alexandr A Microprocessor computing system
US4370733A (en) * 1978-05-19 1983-01-25 Gaudio John J Pattern generation system
US4393458A (en) * 1980-02-06 1983-07-12 Sperry Corporation Data recovery method and apparatus using variable window
US4415984A (en) * 1980-06-25 1983-11-15 Burroughs Corporation Synchronous clock regenerator for binary serial data signals
US4405898A (en) * 1980-06-30 1983-09-20 International Business Machines Corporation Pseudo synchronous clocking
US4386401A (en) * 1980-07-28 1983-05-31 Sperry Corporation High speed processing restarting apparatus
US4712190A (en) * 1985-01-25 1987-12-08 Digital Equipment Corporation Self-timed random access memory chip

Also Published As

Publication number Publication date
EP0379772A2 (de) 1990-08-01
CA1321030C (en) 1993-08-03
EP0379772B1 (de) 1995-06-07
DE68922984D1 (de) 1995-07-13
JP2928866B2 (ja) 1999-08-03
US5408641A (en) 1995-04-18
US5335337A (en) 1994-08-02
DE68922984T2 (de) 1996-04-04
JPH02253464A (ja) 1990-10-12
EP0379772A3 (de) 1992-05-20

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