ATE113399T1 - Verfahren und gerät zur fehlererkennung und - korrektur in einem nach dem überlappten steuerungsverfahren arbeitenden rechnersystem. - Google Patents

Verfahren und gerät zur fehlererkennung und - korrektur in einem nach dem überlappten steuerungsverfahren arbeitenden rechnersystem.

Info

Publication number
ATE113399T1
ATE113399T1 AT89309651T AT89309651T ATE113399T1 AT E113399 T1 ATE113399 T1 AT E113399T1 AT 89309651 T AT89309651 T AT 89309651T AT 89309651 T AT89309651 T AT 89309651T AT E113399 T1 ATE113399 T1 AT E113399T1
Authority
AT
Austria
Prior art keywords
execution
instruction
cpu
errors
error
Prior art date
Application number
AT89309651T
Other languages
English (en)
Inventor
Richard C Beaven
Michael B Evans
Ricky C Hetherington
Tryggve Fossum
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE113399T1 publication Critical patent/ATE113399T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766Error or fault reporting or storing
    • G06F11/0772Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766Error or fault reporting or storing
    • G06F11/0781Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1405Saving, restoring, recovering or retrying at machine instruction level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Retry When Errors Occur (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Multi Processors (AREA)
AT89309651T 1989-02-03 1989-09-22 Verfahren und gerät zur fehlererkennung und - korrektur in einem nach dem überlappten steuerungsverfahren arbeitenden rechnersystem. ATE113399T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,828 US4982402A (en) 1989-02-03 1989-02-03 Method and apparatus for detecting and correcting errors in a pipelined computer system

Publications (1)

Publication Number Publication Date
ATE113399T1 true ATE113399T1 (de) 1994-11-15

Family

ID=23187045

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89309651T ATE113399T1 (de) 1989-02-03 1989-09-22 Verfahren und gerät zur fehlererkennung und - korrektur in einem nach dem überlappten steuerungsverfahren arbeitenden rechnersystem.

Country Status (6)

Country Link
US (1) US4982402A (de)
EP (1) EP0380858B1 (de)
JP (1) JPH02232737A (de)
AT (1) ATE113399T1 (de)
AU (1) AU628163B2 (de)
DE (1) DE68919069T2 (de)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8828817D0 (en) * 1988-12-09 1989-01-18 Int Computers Ltd Data processing apparatus
US5197133A (en) * 1988-12-19 1993-03-23 Bull Hn Information Systems Inc. Control store addressing from multiple sources
JPH07113898B2 (ja) * 1989-05-09 1995-12-06 株式会社日立製作所 障害検出方式
US5490262A (en) * 1989-09-01 1996-02-06 Oki Electric Industry Co., Ltd. Dual cache memory device with cache monitoring
US5355503A (en) * 1990-05-31 1994-10-11 National Semiconductor Corporation Event driven scanning of data input equipment using multi-input wake-up techniques
AU644160B2 (en) * 1990-09-18 1993-12-02 Bull Hn Information Systems Inc. Error handling in a VLSI central processor unit employing a pipelined address and execution module
US5203003A (en) * 1991-03-28 1993-04-13 Echelon Corporation Computer architecture for conserving power by using shared resources and method for suspending processor execution in pipeline
US5339399A (en) * 1991-04-12 1994-08-16 Intel Corporation Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
US5321698A (en) * 1991-12-27 1994-06-14 Amdahl Corporation Method and apparatus for providing retry coverage in multi-process computer environment
US5423025A (en) * 1992-09-29 1995-06-06 Amdahl Corporation Error handling mechanism for a controller having a plurality of servers
JP3338488B2 (ja) * 1992-11-18 2002-10-28 富士通株式会社 データ処理装置の検証方法及び装置
US5561761A (en) * 1993-03-31 1996-10-01 Ylsi Technology, Inc. Central processing unit data entering and interrogating device and method therefor
US5557795A (en) * 1993-06-15 1996-09-17 Xerox Corporation Pipelined image processing system for a single application environment
US5701479A (en) * 1993-06-15 1997-12-23 Xerox Corporation Pipelined image processing system for a single application environment
US5995996A (en) * 1993-06-15 1999-11-30 Xerox Corporation Pipelined image processing system for a single application environment
US5602990A (en) * 1993-07-23 1997-02-11 Pyramid Technology Corporation Computer system diagnostic testing using hardware abstraction
JP3373607B2 (ja) * 1993-09-01 2003-02-04 富士通株式会社 プロセッサの制御機構検証用命令列の自動生成方法及び装置
US5996062A (en) * 1993-11-24 1999-11-30 Intergraph Corporation Method and apparatus for controlling an instruction pipeline in a data processing system
US5550988A (en) * 1994-03-01 1996-08-27 Intel Corporation Apparatus and method for performing error correction in a multi-processor system
US5630055A (en) * 1995-05-05 1997-05-13 Digital Equipment Corporation Autonomous pipeline reconfiguration for continuous error correction for fills from tertiary cache or memory
US5699506A (en) * 1995-05-26 1997-12-16 National Semiconductor Corporation Method and apparatus for fault testing a pipelined processor
US5924125A (en) * 1995-08-01 1999-07-13 Arya; Siamak Method and apparatus for parallel access to consecutive TLB entries
US5678003A (en) * 1995-10-20 1997-10-14 International Business Machines Corporation Method and system for providing a restartable stop in a multiprocessor system
US6202174B1 (en) * 1996-09-16 2001-03-13 Advanced Micro Devices Inc Method for identifying and correcting errors in a central processing unit
US6016543A (en) * 1997-05-14 2000-01-18 Mitsubishi Denki Kabushiki Kaisha Microprocessor for controlling the conditional execution of instructions
KR100230454B1 (ko) * 1997-05-28 1999-11-15 윤종용 다중처리 시스템의 캐시메모리 검사방법
US6044456A (en) * 1998-01-05 2000-03-28 Intel Corporation Electronic system and method for maintaining synchronization of multiple front-end pipelines
US6543026B1 (en) * 1999-09-10 2003-04-01 Lsi Logic Corporation Forward error correction apparatus and methods
US6493819B1 (en) * 1999-11-16 2002-12-10 Advanced Micro Devices, Inc. Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor
EP1359485B1 (de) * 2002-05-03 2015-04-29 Infineon Technologies AG Steuer- und Überwachungssystem
US20040117588A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corporation Access request for a data processing system having no system memory
US20040117583A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corporation Apparatus for influencing process scheduling in a data processing system capable of utilizing a virtual memory processing scheme
US20040117589A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Interrupt mechanism for a data processing system having hardware managed paging of disk data
US20040117590A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Aliasing support for a data processing system having no system memory
US20040117587A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Hardware managed virtual-to-physical address translation mechanism
US20050055528A1 (en) * 2002-12-12 2005-03-10 International Business Machines Corporation Data processing system having a physically addressed cache of disk memory
US7017024B2 (en) * 2002-12-12 2006-03-21 International Business Machines Corporation Data processing system having no system memory
US7370243B1 (en) * 2004-06-30 2008-05-06 Sun Microsystems, Inc. Precise error handling in a fine grain multithreaded multicore processor
US7308605B2 (en) * 2004-07-20 2007-12-11 Hewlett-Packard Development Company, L.P. Latent error detection
JP2006039678A (ja) * 2004-07-22 2006-02-09 Fujitsu Ltd 情報処理装置およびエラー検出方法
US7380169B2 (en) * 2004-09-24 2008-05-27 Intel Corporation Converting merge buffer system-kill errors to process-kill errors
US20070294588A1 (en) * 2006-05-09 2007-12-20 Coulson Richard L Performing a diagnostic on a block of memory associated with a correctable read error
US20080133690A1 (en) * 2006-10-05 2008-06-05 Holt John M Contention detection and resolution
CN101548268B (zh) * 2006-10-05 2014-05-21 瓦拉泰克有限公司 更新存储器位置的内容的方法和系统
US20080120477A1 (en) * 2006-10-05 2008-05-22 Holt John M Contention detection with modified message format
US7962697B2 (en) * 2006-10-05 2011-06-14 Waratek Pty Limited Contention detection
US20080127214A1 (en) * 2006-10-05 2008-05-29 Holt John M Contention detection with counter rollover
US20080126503A1 (en) * 2006-10-05 2008-05-29 Holt John M Contention resolution with echo cancellation
US20080250221A1 (en) * 2006-10-09 2008-10-09 Holt John M Contention detection with data consolidation
US20090150653A1 (en) * 2007-12-07 2009-06-11 Pedro Chaparro Monferrer Mechanism for soft error detection and recovery in issue queues
US8230269B2 (en) * 2008-06-17 2012-07-24 Microsoft Corporation Monitoring data categorization and module-based health correlations
US8896610B2 (en) * 2011-02-18 2014-11-25 Texas Instruments Incorporated Error recovery operations for a hardware accelerator
US8880668B2 (en) * 2011-02-28 2014-11-04 Verizon Patent And Licensing Inc. Method and system for integrating data from multiple sources
US9600382B2 (en) * 2012-09-03 2017-03-21 Southeast University Error recovery circuit oriented to CPU pipeline
US9361116B2 (en) 2012-12-28 2016-06-07 Intel Corporation Apparatus and method for low-latency invocation of accelerators
US9417873B2 (en) 2012-12-28 2016-08-16 Intel Corporation Apparatus and method for a hybrid latency-throughput processor
US9053025B2 (en) 2012-12-28 2015-06-09 Intel Corporation Apparatus and method for fast failure handling of instructions
US10140129B2 (en) 2012-12-28 2018-11-27 Intel Corporation Processing core having shared front end unit
US10346195B2 (en) 2012-12-29 2019-07-09 Intel Corporation Apparatus and method for invocation of a multi threaded accelerator
CN113407239B (zh) * 2021-06-09 2023-06-13 中山大学 一种基于异步单轨的流水线处理器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293919A (en) * 1979-08-13 1981-10-06 International Business Machines Corporation Level sensitive scan design (LSSD) system
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
JPS59123058A (ja) * 1982-12-29 1984-07-16 Fujitsu Ltd マシンチエツク処理方式
US4757445A (en) * 1983-09-12 1988-07-12 Motorola, Inc. Method and apparatus for validating prefetched instruction
US4583222A (en) * 1983-11-07 1986-04-15 Digital Equipment Corporation Method and apparatus for self-testing of floating point accelerator processors

Also Published As

Publication number Publication date
DE68919069T2 (de) 1995-06-08
EP0380858B1 (de) 1994-10-26
US4982402A (en) 1991-01-01
EP0380858A3 (de) 1991-08-28
AU628163B2 (en) 1992-09-10
JPH02232737A (ja) 1990-09-14
AU5394590A (en) 1991-12-19
EP0380858A2 (de) 1990-08-08
DE68919069D1 (de) 1994-12-01

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