AR060844A1 - Intercalador de bits paralelos para un sistema inalambrico - Google Patents

Intercalador de bits paralelos para un sistema inalambrico

Info

Publication number
AR060844A1
AR060844A1 ARP070101905A ARP070101905A AR060844A1 AR 060844 A1 AR060844 A1 AR 060844A1 AR P070101905 A ARP070101905 A AR P070101905A AR P070101905 A ARP070101905 A AR P070101905A AR 060844 A1 AR060844 A1 AR 060844A1
Authority
AR
Argentina
Prior art keywords
intercharter
wireless system
clock edge
parallel bit
data
Prior art date
Application number
ARP070101905A
Other languages
English (en)
Inventor
Jinxia Bai
Thomas Sun
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AR060844A1 publication Critical patent/AR060844A1/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
    • H04L1/0017—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy where the mode-switching is based on Quality of Service requirement
    • H04L1/0018—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy where the mode-switching is based on Quality of Service requirement based on latency requirement
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0093—Point-to-multipoint

Abstract

Sistemas y métodos para procesar paquetes de datos inalámbricos. Un método incluye determinar un subconjunto de bits de datos para ser procesados en un transmisor inalámbrico y emplear un borde de reloj para almacenar los datos. El borde de reloj hace posible mapear por lo menos dos bits procedentes del subconjunto de bits de datos dentro de una memoria de intercalado por un borde de reloj dado. A partir de la memoria, otros procesos de codificacion son aplicados antes de transmitir los paquetes de datos a través de una red inalámbrica.
ARP070101905A 2006-05-02 2007-05-02 Intercalador de bits paralelos para un sistema inalambrico AR060844A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/416,853 US7830957B2 (en) 2006-05-02 2006-05-02 Parallel bit interleaver for a wireless system

Publications (1)

Publication Number Publication Date
AR060844A1 true AR060844A1 (es) 2008-07-16

Family

ID=38564193

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP070101905A AR060844A1 (es) 2006-05-02 2007-05-02 Intercalador de bits paralelos para un sistema inalambrico

Country Status (8)

Country Link
US (1) US7830957B2 (es)
EP (1) EP2013976A1 (es)
JP (1) JP2009536007A (es)
KR (1) KR20090016687A (es)
CN (1) CN101438500B (es)
AR (1) AR060844A1 (es)
TW (1) TW200803325A (es)
WO (1) WO2007131023A1 (es)

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US8817626B2 (en) * 2007-03-08 2014-08-26 Nokia Corporation Interoperability of digital broadcasting and cellular communication systems
US8493835B2 (en) * 2008-03-26 2013-07-23 Qualcomm, Incorporated Method and apparatus for mapping virtual resources to physical resources in a wireless communication system
CN104158643B (zh) 2008-10-31 2017-08-15 Lg电子株式会社 发送广播信号的方法
US20100251069A1 (en) * 2009-03-31 2010-09-30 Qualcomm Incorporated Method and apparatus for efficient memory allocation for turbo decoder input with long turbo codeword
JP5321344B2 (ja) * 2009-08-18 2013-10-23 三菱電機株式会社 送信装置及び送信方法、受信装置及び受信方法
EP2525497A1 (en) * 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
EP2525498A1 (en) * 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
EP2525495A1 (en) * 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
EP2525496A1 (en) 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
KR102051298B1 (ko) * 2012-07-27 2019-12-03 선 페이턴트 트러스트 송신방법, 수신방법, 송신기 및 수신기
EP2690790A1 (en) * 2012-07-27 2014-01-29 Panasonic Corporation Bit interleaving for rotated constellations with quasi-cyclic LDPC codes
US10623134B2 (en) 2015-12-31 2020-04-14 Telefonaktiebolaget Lm Ericsson (Publ) Communication device and method therein for transmitting data packets in a wireless communication network
CN109495207B (zh) * 2017-09-11 2021-08-10 上海诺基亚贝尔股份有限公司 用于在无线通信系统中交织数据的方法和设备

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4777635A (en) * 1986-08-08 1988-10-11 Data Systems Technology Corp. Reed-Solomon code encoder and syndrome generator circuit
JPH0832460A (ja) * 1994-07-15 1996-02-02 Toshiba Corp 誤り訂正符号化方式並びに誤り訂正符号化装置並びに誤り訂正復号方式並びに誤り訂正復号装置
KR100186627B1 (ko) * 1996-09-21 1999-05-15 삼성전자 주식회사 베이스 밴드 인터리버
US6163871A (en) * 1998-05-29 2000-12-19 Adaptec, Inc. RAM based error correction code encoder and syndrome generator with programmable interleaving degrees
CN1345485A (zh) * 1999-04-06 2002-04-17 三星电子株式会社 二维交织设备及方法
US7219173B2 (en) * 2001-07-31 2007-05-15 Micronas Usa, Inc. System for video processing control and scheduling wherein commands are unaffected by signal interrupts and schedule commands are transmitted at precise time
US6954885B2 (en) * 2001-12-14 2005-10-11 Qualcomm Incorporated Method and apparatus for coding bits of data in parallel
DE10202090B4 (de) * 2002-01-21 2010-08-12 Infineon Technologies Ag Elektronische Sender-Empfänger-Vorrichtung
US7091889B2 (en) * 2002-09-09 2006-08-15 Telefonaktiebolaget Lm Ericsson (Publ) Speed and memory optimized interleaving
CN1455524A (zh) * 2003-03-17 2003-11-12 西南交通大学 用于多发射多接收（mimo）天线阵列系统的空间并行交织方法
US20040268207A1 (en) 2003-05-21 2004-12-30 Engim, Inc. Systems and methods for implementing a rate converting, low-latency, low-power block interleaver
JP3717912B2 (ja) * 2003-11-06 2005-11-16 沖電気工業株式会社 インタリーブ装置

Also Published As

Publication number Publication date
CN101438500A (zh) 2009-05-20
WO2007131023A1 (en) 2007-11-15
TW200803325A (en) 2008-01-01
US20070258532A1 (en) 2007-11-08
KR20090016687A (ko) 2009-02-17
JP2009536007A (ja) 2009-10-01
CN101438500B (zh) 2013-08-21
US7830957B2 (en) 2010-11-09
EP2013976A1 (en) 2009-01-14

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