AR052369A1 - Metodo de colocacion de un conjunto electronico sobre un substrato y dispositivo de colocacion de dicho conjunto - Google Patents

Metodo de colocacion de un conjunto electronico sobre un substrato y dispositivo de colocacion de dicho conjunto

Info

Publication number
AR052369A1
AR052369A1 ARP060100344A AR052369A1 AR 052369 A1 AR052369 A1 AR 052369A1 AR P060100344 A ARP060100344 A AR P060100344A AR 052369 A1 AR052369 A1 AR 052369A1
Authority
AR
Argentina
Prior art keywords
segment
substrate
chip
track
assembly
Prior art date
Application number
Other languages
English (en)
Inventor
Francois Droz
Original Assignee
Nagrald S A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nagrald S A filed Critical Nagrald S A
Publication of AR052369A1 publication Critical patent/AR052369A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07718—Constructional details, e.g. mounting of circuits in the carrier the record carrier being manufactured in a continuous process, e.g. using endless rolls
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Abstract

El objetivo de la presente consiste en garantizar una precision máxima tanto a nivel de la fabricacion de un conjunto electronico a partir de un chip de pequena dimensiones como a nivel de la colocacion de este conjunto sobre substrato aislante. Este objetivo es alcanzado por un método de colocacion sobre un soporte, llamado substrato (7), de la menos un conjunto electronico constituido por un chip (4) que incluye al menos un contacto eléctrico (5, 5') sobre una de sus caras, y dicho contacto (5, 5') está conectado a un segmento (3, 3') de pista conductora, y dicha colocacion es efectuada por medio de un dispositivo de instalacion (6) que mantiene y situa dicho conjunto sobre el substrato (7), caracterizado por el hecho de que comprende las etapas siguientes: formacion de un segmento (3, 3') de pista conductora que posee un contorno predeterminado; transferencia del segmento (3, 3') de pista sobre el dispositivo de instalacion (6); toma del chip (4) con el dispositivo de instalacion (4) que lleva el segmento (3, 3') de pista para que dicho segmento (3, 3') de pista se coloque sobre al menos un contacto (5, 5') del chip (4); colocacion del conjunto electronico constituido por el chip (4) y el segmento (3, 3') de pista en una posicion predeterminada sobre el substrato (7); introduccion del chip (4) y del segmento (3, 3') de pista en el substrato (7). La presente se refiere también al dispositivo de instalacion utilizado en el método y a un objeto portátil que incluye un conjunto electronico colocado segun el método.
ARP060100344 2005-02-01 2006-01-31 Metodo de colocacion de un conjunto electronico sobre un substrato y dispositivo de colocacion de dicho conjunto AR052369A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05100694A EP1686512A1 (fr) 2005-02-01 2005-02-01 Procédé de placement d'un ensemble électronique sur un substrat et dispositif de placement d'un tel ensemble

Publications (1)

Publication Number Publication Date
AR052369A1 true AR052369A1 (es) 2007-03-14

Family

ID=34938618

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP060100344 AR052369A1 (es) 2005-02-01 2006-01-31 Metodo de colocacion de un conjunto electronico sobre un substrato y dispositivo de colocacion de dicho conjunto

Country Status (4)

Country Link
EP (1) EP1686512A1 (es)
AR (1) AR052369A1 (es)
MY (1) MY149176A (es)
TW (1) TWI420606B (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2925969B1 (fr) * 2007-12-26 2010-01-22 Datacard Corp Procede et dispositif d'encartage d'un module ou puce.

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5406699A (en) * 1992-09-18 1995-04-18 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronics package
FR2701139B1 (fr) * 1993-02-01 1995-04-21 Solaic Sa Procédé pour l'implantation d'un micro-circuit sur un corps de carte intelligente et/ou à mémoire, et carte comportant un micro-circuit ainsi implanté.
WO2000002243A1 (fr) * 1998-07-01 2000-01-13 Seiko Epson Corporation Dispositif a semi-conducteur, procede de fabrication associe, carte imprimee et dispositif electronique
JP4421081B2 (ja) * 1999-06-09 2010-02-24 パナソニック株式会社 パワーモジュールとその製造方法
DE10016715C1 (de) * 2000-04-04 2001-09-06 Infineon Technologies Ag Herstellungsverfahren für laminierte Chipkarten
DE10136359C2 (de) * 2001-07-26 2003-06-12 Muehlbauer Ag Verfahren zum Verbinden von Mikrochipmodulen mit auf einem ersten Trägerband angeordneten Antennen zum Herstellen eines Transponders
US6838316B2 (en) * 2002-03-06 2005-01-04 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method using ultrasonic flip chip bonding technique

Also Published As

Publication number Publication date
TW200711008A (en) 2007-03-16
MY149176A (en) 2013-07-31
EP1686512A1 (fr) 2006-08-02
TWI420606B (zh) 2013-12-21

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Legal Events

Date Code Title Description
FG Grant, registration
FD Application declared void or lapsed, e.g., due to non-payment of fee