WO1985002050A1

WO1985002050A1 - Apparatus for controlling writing and reading in relation to graphic memory

Info

Publication number: WO1985002050A1
Application number: PCT/JP1984/000503
Authority: WO
Inventors: Yoshiaki Ikeda
Original assignee: Fanuc Ltd
Priority date: 1983-10-25
Filing date: 1984-10-22
Publication date: 1985-05-09
Also published as: EP0161319A1; EP0161319B1; DE3480363D1; EP0161319A4; JPS6090387A

Abstract

Apparatus for controlling writing and reading in relation to graphic memories (1R, 1G, 1B) for a red screen, a green screen and a blue screen, respectively, each of the graphic memories having a capacity of N x M bits. The apparatus operates in such a manner that data is written into the graphic memories (1R, 1G, 1B) bit by bit and is read out therefrom in units of M bits. The apparatus is capable of modification of one bit per cycle of a CPU (8) with a reduced number of hardware elements. Each of the graphic memories (1R, 1G, 1B) is constituted by an M-bit output RAM group consisting of M 1-bit output RAMs (20 to 27) each having a capacity of 1 X N bits. Further, the same address space is allotted to the graphic memories (1R, 1G, 1B), and 1-bit data lines of a data bus (9) of the CPU (8) are respectively connected to all the RAMs (20 to 27) in each of the graphic memories (1R, 1G, 1B). The writing of data, which is effected bit by bit, is carried out in such a manner that one bit of each of the RAMs (20 to 27) in each of the graphic memories (1R, 1G, 1B) is specified by the CPU address, and a write signal is delivered to any of the desired M RAMs (20 to 27) with a part of the CPU address.

Description

. Specification

Harmful readout control device for graphic memory

Technical field

The present invention relates to a harmful readout control device for a graphic memory in a color graphic display.

Background technology

In general, in a color graphics display, one bit of the graphics memory corresponds to one pixel on the screen, so when creating graphic data in the digital memory, it is necessary to perform data corruption in bit units Nature occurs. Conventionally, this bit-by-bit processing has been realized by the following method. -

1) The processor (CPU) reads data from the graphic memory in byte units, changes the corresponding one bit of the bytes, and writes it again in byte units.

2) A hardware, usually called a bit operation circuit, is provided between the CPU and the graphic memory, and the read, modify, and write of 1) are executed.

However, the method 1) requires a small amount of hardware, but has a drawback in that the processing speed is slow because the operation time of at least two cycles of CPU is required for writing one bit. The method 2) can modify one bit in one cycle of CPU, but has the disadvantage of requiring extremely complicated hardware and increasing the cost.

Disclosure of the invention

An object of the present invention is to enable a one-bit modification in one cycle of a CPU by adding a small amount of hardware. Briefly describing the present invention, the writing of graphic memory of the present invention The readout control unit is a red screen with NXM bit capacity. In the read / write control device, the graphics memory for reading data in units of 1-bit and for reading data in units of M bits into the graphics memory for planes, screens, and blues. , Green memory, and blue screen graphic memory are composed of M-bit output RAMs consisting of M RAMs with 1-bit output and 1 XN-bit capacity, and for red-screen and 緣 -screen. , The same address space is allocated to the graphics memory for the blue screen, and 1-bit data lines with different data buzz of the CPU are assigned to the graphics for the red screen, the blue screen, and the blue screen. Connected to all RAMs in the graphics memory, and the 1-bit data writing is performed by specifying one bit of each RAM of each graphics memory by the CPU address and by using a part of the CPU address. Any one RA of M RAMs It is designed to send a write signal to M. Brief explanation of drawings

Figure 1 is a write read control instrumentation of the present invention - main part block diagram showing an example of the location of the hard de A configuration, FIGS. 2 and 3 each region and di splay of RAM 2 o ~ 2 ₇ A diagram showing the relationship with the display position on the screen, Fig. 4 is a diagram showing signal waveform examples of each part in Fig. 1, and Fig. 5 is a diagram when graphic data 1β, 1G, IB FIG. 6 is a flow chart showing a processing example of the CPU 8, FIG. 6 is a diagram showing a data format example of the CPU, and FIG. 7 is a block diagram showing an embodiment of the timing generation circuit 14.

BEST MODE FOR CARRYING OUT THE INVENTION

In FIG. 1, 11H is a graphics memory for red screen, 1G is a graphics memory for green screen, 1B is a graphics memory for blue screen, RAM 2 of lx N bits each. To 27. These graphic memories have the same address space. Although it illustrated for convenience on the red-screen graphic Kkume mode only eight in Li 18 RAM 2 o ~ 2 ₇ in FIG have, other graphic Kkumemori 1G, 1B also eight RAM as well. Gras Fi click Note Li 1R, 1G, output 1B is 8 bits, the 8 bits each 1 bi Tsu bets by withdrawn Resona these are collected from each RAM 2 o ~ 2 ₇ And are set in shift registers 3R, 3G, and 3B. For example, as shown in FIG. 2, if each bit of each RAM 2o to 27 is numbered, each of a total of 8 XN bits is displayed on the display screen 4 as shown in FIG. 3, for example. Corresponds to the area. This is because the address of one of the display addresses added from the CRT controller 5 via the multiplexer 6 allows the RAM 2o to 27 to have the same bit ( For example, 0 to 7 and 8 to 15) are read out and set in shift registers 3R, 3G, and 3B at the same time for 8 bits, and the dot clock dc (from the CRT controller 5) is output from the CRT controller 5. (The frequency is 8 times the clock for counting up the display address counter.) As serial data, a red video signal is output to a CRT (not shown) via AND circuits 7R, 7G, and 7B. This is because the video signal and the blue video signal are input. Incidentally, CRT Control This setup roller 5 Karaa down de circuits 7R, 7G, signal ί entered in 7B, only the horizontal blanking interval "is 0 ^a signal that becomes red video signals, green video signals and blue A gate signal for outputting a video signal only during the display period.

Data input of each RAM 2 o ~ 2 ₇ is, by one bit of the 0-bit th data bus 9 of the CPU 8 for the graph I click Note re-1R for red screen (a 0), for緣screen For graphics memory 1G, the first bit (aj) of data bus 9 is The memory IB is performed by one bit of the second bit (a ₂ ) of the data bus 9. That is, in each graphic memory, only one bit of data is rewritten in one cycle of the operation of the CPU 8. Note that 10 R, 10 G, and 10 B are drivers.

Delivery of addressing and Rai DOO signal when writing data of one bit to each RAM 2 o ~ 2 ₇ from the CPU 8 is carried out as follows. Of the address bus 11 of the IS bit of the CPU 8, a total of 3 bits of the 0th to 2nd bits (ao, at, a2) are added to the RAM selection circuit 12 and the remaining bits are For example, a total of 10 bits are added to the multiplexer 6. The address of each graphic memory is specified by the CPU address input through the multiplexer 6. On the other hand, the signal d from the address decoder 13 and the signal c from the timing generation circuit 14 are input to the RAM selection circuit 12, and eight signals of the logical product of the signal d and the signal c are input to the RAM selection circuit 12. Is output to any of the output lines 12Q to 12T. Under 3 'bi Tsu Bok contents of one is to be output to the output line add-Resubasu _{11 (a 2, ai, ao} ) is determined by. The eight output lines 120 to 12 ₇ are connected grayed Rafi Kkumemori IB, 1G, Rye preparative terminal and over对one each RAM 20 ~ 2 ₇ of IB. Thus, the lower 3 Bitsu bets add-less a _2, ai, by ao, each graphic Kkumemori IB, 1G, or write data of one bit in IB throat RAM is determined. Note that the address decoder 13 decodes the address information of the address bus 11 and sets the signal d to "1" when the CPU attempts to access the graphic memories 1R, 1G, and 1B. When the CRT controller 5 is being accessed, the signal e is set to "1". As the configuration of the address decoder 13, for example, if the address space of the graphic memories IB, 1G, and IB is F0000-FFFF, the CPU has four address bits a16 to a19.

^ OMPI An AND circuit that sets the signal d to "1" when both bits are "1", and an analog circuit that sets the signal e to "1» when the address space of the CRT controller is accessed. It can be composed of an AND circuit.

Thailand Mi ring generated image path 14 is configured to receives the line bets signals from CRT 8. "1" signal c to the RAM 2 tj ~ 2 ₇ Rye Tosai in cycle of the immediately following. The timing generation circuit 14 outputs the symbol a to the multiplexer 6 and outputs the signal b to the shift registers 3R, 3G, 3B. The signal a is a signal for distinguishing between a cycle for reading data from the graphic memories 1R, 1G, and 1B and a cycle for writing data from the CPU 8, and the output of the multiplexer 6 is output to the CPU by the signal a. Switch to less bus 9 side and CRT controller 5 side. The signal b is a strobe signal for latching the 8-bit data read from the graphic memories 1R, 1G, and IB to the shift registers 3R, 3G, and 3B.

■ The timing generation circuit 14 can be configured, for example, as shown in FIG. In the figure, the octal counter 70 is counted up by a dot clock dc, and the lower three bits of the output Q! , Q 2. Q 3 is retrieved. Each output 3 is input to the AND circuit 71, and the output of the AND surface 71 becomes a signal b. Also, output Q ₃ becomes signal a. The dot clock dc is also input to the flip-flop 74 clock terminal. The logical product of the write signal and the output of the AND circuit 71 is obtained by the AND circuit 72, and the output of the AND circuit 72 is input to the set terminal S of the flip-flop 73. You. The output Q of the flip-flop is connected to the set element S of the flip-flop 74, and the inverted output Q of the flip-flop 73 is connected to the flip-flop. Connected to the reset terminal R of the flip-flop 74 and connected to the reset terminal R of the flip-flop 73 if the output Q of the flip-flop 74 Is done. The output Q of the flip-flop 74 becomes the signal c.

Fig. 4 shows the dot clock, which is the shift pulse of the shift registers 3β, 3G, 3Β, the header for counting the display address, the output of the multiplexer 6, and the graphics memory 1R, 1G. , IB input, graphics memory 1R, 1G, 1B output, signals a, b, c, CPU 8 write signal timing chart. As shown in the figure, the contents of the graphic memories 18, 1G, and IB are read in 8-bit units, and a write cycle is generated between each read.

Next, the operation of the apparatus shown in FIG. 1 will be described. FIG. 5 is a flowchart showing a processing example of the CPU 8 when writing graphic data to the graphic memories 1R, 1G, and IB. As shown in the figure, when a figure is to be created, it is first determined what color of the figure is to be displayed or not. Then, corresponding to each display color, the following information is stored in the lower 3 bits of an 8-bit register such as an internal register of the CPU. That is, as shown in FIG. 6, red information is set to the least significant bit a0, 緣 information is set to the next bit a, and blue information is set to the next bit a2. Display color Black 0 0 0 Display color Red 0 0 1 Display color 緣 0 1 0 Display color “1 0 0 Display color 黃 0 1 1 Display color Magenta 1 0 1 Display color Cyan 1 1 0 Display color White 1 1 1 Next, the data in the above register is harmed to the address of the corresponding RAM 2o to 27. For example, when a red dot is displayed at one point on the screen, the area of the corresponding graphic memory at that point is displayed. If RAM is the second of RAM 21 (the area of number 9 in Figure 2), write as shown in Figure 4. After the symbol is generated, the lower 3 bits of the CPU address are set to, for example, (0, 0, 1) to select the output line 12 !, and the address added to the multiplexer 6 is set to the RAM 2 I Set so that the second area of is selected. Then, the data of (0000 0000 1) is transmitted to the data bus 9. As mentioned above, since the graphic Kkume model re-1R for red screen are connected to the least significant bits of the data bus ^9, α 1 ^a data RAM 2! Will be recorded in the second area. At this time, “0” is stored in the second area of the RAM 2 i of the 緣 screen graphics memory 1G and the blue screen graphics memory 1B.

On the other hand, when the multiplexer 6 is switched by the signal a, the contents of the graphics memories 1R, 1G, and IB are read out in 8-bit units, and at least within one scanning period of the screen, the RAM 2! Data is read out and displayed.

As described above, according to this study, data is harmed on a 1-bit basis to the NXM-bit graphics memory for red screen, blue screen, and blue screen. In the writing / reading control device for a graphic memory for reading data in units, the RAM for the red screen, the black screen, and the blue screen is 1 bit output and has a capacity of 1 XN bits] VI RAM And the same address space is allocated to the graphics memory for the red screen, the blue screen, and the blue screen. By specifying the address twice, it is possible to specify the same address of 8 bits for the graphic memory for red screen, border screen, and blue screen, and for each different 1-bit data on the CPU data bus. Line for red screen, for ， screen Connected to all the RAM of the graphics Kkume model in Li for blue screen, the 1-bit To write data on a per-chip basis, specify one bit of each RAM of each graphic memory in the CPU address and send a write signal to any one of the M RAMs in a part of the CPU address By doing so, there is the advantage that data can be harmed at the bit level from the CPU and the color can be specified at the same time as the data is written. As described above, according to the present invention, it is possible to modify one bit of the graphics memory in one cycle of the CP only by adding a small amount of hardware.

Claims

The scope of the claims

Writes data in 1-bit units to the N, M-bit graphics memory for red screen, blue screen, and blue screen, and reads data in M-bit units. In the read / write control unit, the M-bit output RAM group consisting of M RAMs each having 1-bit output and 1-XN-bit capacity of the above-mentioned red, green, and blue screen graphics memory. The same address space is allocated to the graphics memory for red screen, blue screen, and blue screen, and different 1-bit data lines of the CPU data bus are used for the red screen, blue screen, and blue screen. It is connected to all the RAMs in the screen and blue screen graphics memory, and the 1-bit unit data writing is performed by specifying 1 bit of each RAM of each DRAM memory by CPU address and by CPU address. Any one of R A M graphics Tsu Kume Mori write read control apparatus characterized that you configured to perform by leaving feed Reye bets signal to the M R A M in some less.