SU1675929A1 - Data display unit - Google Patents

Abstract

The invention relates to automation and computing and can be used to display information from a computer. The purpose of the invention is to increase the speed of the device, which is achieved by the introduction of the register 6, the third memory block 7 and the corresponding functional connections. The invention allows separate and independent processing of image fragments bounded by an arbitrary closed broken line, without changing the image information recorded in the memory block. 5 il.

Description

X

cl

YU

Yu

The invention relates to automation and computing and can be used to display information from a computer.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - block diagram of the information processing unit; in fig. 3 - block diagram block diagram; in fig. 4 is a block diagram of the control unit; in fig. 5-structured address addressing scheme.

The device comprises a synchronization unit 1, a control unit 2, an address generator 3, first 4 and a memory block 5, a register 6, a third memory block 7, an information processing unit 8, a video signal generator 9, a television receiver 10.

The information processing unit contains multiplexers 11-14, memory blocks 15 and 16, register 17, arithmetic logic unit 18, counter 19.

The synchronization unit contains a generator of 20 clock pulses, point counters 21 and lines 22, a decoder 23.

The control unit contains a multiplexer 24, a decoder 25, a register 26, a decoder 27, a counter 28, a trigger 29, an AND element 30, a decoder 31.

The address driver includes a switch 32, a register 33, an adder 34, a recporn 35, a switch 36, a register 37, an adder 38, registers 39 and 40, a counter 41, a switch 42, a register 43.

The device works as follows.

The halftone information is fed to the information input of the device in digital codes, each of which represents information about a single point on the screen and is encoded with n-bits, where, 2,3 ,, .., and passing through the multiplexer 24 of the control unit 2, is written to the first block 4 of memory by addresses that are calculated by the address formation schemes: switches 32 and 36, registers 33 and 37, adders 34 and 38, output registers 35 and 39, and through output switch 42 and register 43 of the driver 3, addresses are issued to address inputs of the first 4 and second 5 memory blocks. Then, the graphic information in the form of K-bit is fed to the information input of the device.

codes, 2, 3, containing information

about contours (closed broken lines, bounding a fragment of the image to be processed), which are recorded in the second memory block 5 by addresses, which are formed in the same way as for the grayscale information in the address generator 3. After writing the grayscale and graphic information to the corresponding memory blocks, the operator determines which

types of processing (functional or color) to expose the image and using a control computer (not shown) fill in the appropriate information blocks 15 and 16 of the memory of processing block 8

0 information, and also associates with the image codes of arithmetic and logical operations for the arithmetic logic unit 18, intended for image processing, and writes the codes

5 to the third memory block 7.

The filling of blocks 15 and 16 of memory of block 8 and the third block of memory 7, which are used as tables for data transcoding, is performed as follows:

0 way. The counter 19 of block 8 is pre-recorded with the starting address for writing to the above blocks and through multiplexers 11 and 12 is applied to the address inputs of blocks 7.15 and 16 of memory. Data

5 for recording in all the memory blocks are received from the input of the device, and the recording control signals and the sampling of the memory blocks are received from the decoder 27 of the control unit 2. The address width of blocks 7, 15 and 16

0 memory is (n + k) bits. This is necessary to control the processing of data, depending on the belonging of the raster points to the corresponding image areas, limited by arbitrary

5 contours.

The processing and display of the image on the screen of the television receiver is carried out as follows. Information about the halftone image and contours, written respectively to the first memory block 4 and the second memory block 5, is output from the memory blocks according to the initial regeneration addresses stored in register 40 of the driver 3 addresses and current addresses

5 regenerations, which are generated by the counter 41 and transmitted via the output switch 42 and the register 43 of the address generator 3 to the address inputs of the memory blocks 4 and 5. The halftone information from the first memory block 4 is fed to the second information input of the processing unit 8, and the graphic one from the second memory block 5 is fed through register 6 to the fourth information input of the information processing block 8. Register 6 is a set of triggers enabled in counting mode, with a general reset. The trigger inputs of the triggers receive bits of contour codes that are stored in memory block 5. The contour is represented by a broken line.

line. At the first (odd), in the process of scanning the line, the intersection of a contour that has a certain code is switched to 1 corresponding triggers of register b. At the second (even) intersection of the contour, the corresponding triggers are switched to O. At the end of the line, all the triggers of the register are reset to O, which allows for image processing within the screen. The halftone and transformed graphical information is fed to the input of multiplexer 11. The halftone information arrives as the youngest part of the code, and the transformed graphical information as the eldest part of the code. From the output of the multiplexer 11, information is fed to the address inputs of memory blocks 7 and 15, where respectively the functional conversion tables and sample codes of arithmetic v logic operations for the arithmetic logic unit 18 are recorded. Information from the output of memory block 15 is fed to the information input, and the output of memory block 7 - to the control input of the arithmetic logic unit 18 of the information processing unit 8; To the second information input of the arithmetic logic unit 18, information is received either from the register 17 of the unit 8, or from the control A device input which, in conjunction with the device output, can be used to connect a second display channel. From the arithmetic logic unit 18, information is fed to the input of multiplexer 12 and is the lowest part of the address for memory block 16. The same input of the multiplexer 12 receives information from the register 6, which is the highest part of the address for the memory block 16. From the output of the multiplexer 12, information is fed to the address input of the memory block 16, which functions as a color table. The higher address bits divide the address space of the memory block 16 by 2 pages, which allows the image to be colored based on the location of a portion of the image on the screen, i.e. in contours. Data from the memory block 16 is fed to the input of the multiplexer 13 of the processing block 8, the second input of which receives information from the second memory block 5. From the output of the multiplexer 13, the information is fed to the input of the video signal generator 9, where the discrete image information is converted into analog signals and transmitted together with the clock signals to the television receiver.

Thus, the proposed device allows separate processing of different image fragments without changing the contents of memory blocks 4 and 5, thereby significantly improving the speed of the device.

Claims (1)

Formula of the Invention A device for displaying information comprising a synchronization unit, an address generator, a control unit, first and second memory blocks, an information processing unit, a video signal generator, the output of which is connected to the video input of the television receiver, the output of the synchronization unit is connected to the clock inputs of the control unit of the address generator, the first and second memory blocks and the sync input of the video signal generator, whose information input is connected to the first output of the information processing unit, the first information input of which is connected to the information inputs of the control unit and the address generator, is the information input of the device, the first output of the control unit is connected to the information inputs of the first and second memory blocks, the control inputs of the cohors are connected to the second output of the control unit, the third output of which is connected to the first control input of the information processing unit, connected to the control input of the address generator, the output of which is connected to the address inputs of the first and second memory blocks, the outputs of which are connected respectively to the second and third information in odes information processing unit, the second the output of which is the output of the device, the second control input of the information processing unit is the control input of the device, from that, in order to increase the speed of the device, it contains a register, a third memory block, the output of which is connected to the third control the input of the information processing unit, the third output of which is connected to the address input of the third unit the memory, the information input of which is connected to the first information input of the information processing unit, the fourth information input of which is connected to the register output, the information input which is connected to the output of the second memory block, the control inputs of the register and the third memory block are connected to the third output of the control block. rm L sh IT out1 J one vsh.g 3 s Compiled by A. Korobov Editor V. Bugrenkova Tehred M. Morgental I "TS Proofreader T. Malets