US4283662A - Line scan circuits for cathode ray tube displays - Google Patents

Line scan circuits for cathode ray tube displays Download PDF

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Publication number
US4283662A
US4283662A US06/080,889 US8088979A US4283662A US 4283662 A US4283662 A US 4283662A US 8088979 A US8088979 A US 8088979A US 4283662 A US4283662 A US 4283662A
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pulses
pulse
square
synchronization
output
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US06/080,889
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English (en)
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Frank Ainscow
Edward D. Anwyl
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator

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  • This invention relates to a line scan circuit for a cathode ray tube display apparatus and more particularly to such a line scan circuit incorporating a novel phase detector.
  • a phase-locked oscillator is synchronized with the incoming horizontal synchronization (H-sync) pulses to provide a control signal to the line output circuit.
  • H-sync horizontal synchronization
  • This ensures that oscillation is maintained in the absence of the H-sync signal, for example, during maintenance in the case of a display terminal, or, in the case of a TV receiver, when untuned, and noise on the incoming signal is smoothed out.
  • the phase relationship between the output and input is very precisely maintained to prevent line tearing and other picture defects.
  • Flyback voltage pulses occur at the terminals of the yoke of the cathode ray tube (CRT) between successive horizontal scans of the electron beam while the screen is blanked. Due to component tolerances and temperature effects, the flyback voltage pulses may be broadened and unless the broadened pulse falls within the blanking period, picture defects can occur. Conventionally, this problem has been overcome by designing the CRT circuits to allow a broad blanking period between the line scans: however, this has a deleterious effect on the efficiency of the display.
  • An object of the present invention is to provide an improved CRT line scan circuit.
  • FIG. 1 is a block diagram showing a line scan circuit.
  • FIG. 2 shows the relationship between various waveforms and illustrates the effect of the present invention compared to a conventional circuit.
  • FIG. 3 shows a pulse-shaping circuit arrangement for use in the phase detector of FIG. 1.
  • FIG. 4 shows a circuit arrangement for logically combining the pulses produced in the circuit arrangement of FIG. 3.
  • FIGS. 5 and 6 show the relationship between various waveforms produced in the circuits of FIGS. 3 and 4.
  • FIG. 7 shows a delay network which can be used to guard against the so-called dead-space condition.
  • a CRT line scan circuit comprises an input 1 for receiving horizontal synchronization (H-sync) pulses and an output 2 at which a line scan waveform is produced, resulting in line flyback pulses.
  • a phase detector 3 receives the H-sync pulses and the flyback pulses and has its output connected to an integrator 4 which, in turn, is connected to a voltage controlled oscillator (VCO) 5.
  • VCO voltage controlled oscillator
  • the output of the voltage controlled oscillator 5 is connected to the line output stage 6 of the line scan circuit.
  • the circuit thus acts as a phase-locked oscillator (PLO), the presence of the integrator 4 identifying the PLO as a type 2 servo, that is there are two integrations in the loop.
  • PLO phase-locked oscillator
  • the integrator characteristic is designed to ensure loop stability.
  • phase detector 3 is of novel design and will be described more fully below. However, before describing the phase detector in more detail, it will be convenient to refer to FIG. 2 which illustrates various waveforms which occur within a CRT line scan circuit.
  • waveform 7 represents the H-sync pulse while waveform 8 represents data being displayed on the CRT screen.
  • line scan period 9 the electron beam will be blanked and unblanked as it scans across the screen in accordance with the data to be displayed.
  • the beam will flyback while blanked and then during the line scan period 11 will again be blanked and unblanked in accordance with the displayed data.
  • the beam is moved under the influence of the line flyback pulse represented by waveform 12 in FIG. 2.
  • timing of the line flyback pulse 12 is determined by the leading edge of the H-sync pulse 7.
  • the line flyback pulse will in some cases be widened as represented by the dotted waveform 13.
  • the circuits are designed to accommodate this broadening effect by allowing a sufficiently long blanking period, but it is desirable to shorten the blanking period as much as possible to make the beam available for data display for as high a proportion of the time as possible. If, however, the blanking period is shortened, the broadened pulse can extend into the line scan period 9.
  • the rate of change of current in the yoke of the CRT is proportional to the voltage so that if the line flyback pulse encroaches on the line scan period, there will be distortion of the data being displayed.
  • the line scan waveform is derived from both the leading and trailing edges of the H-sync pulse. Not only does this center the line flyback pulse in the line blanking period, but it ensures accurate centering of the data being displayed on the CRT screen and mitigates the deleterious effects of broadened flyback pulses.
  • This is represented by the waveform 14 in FIG. 2. It will be seen that with the same broadening of the flyback pulse as represented by waveform 13, there is no encroachment on the line scan period 9. If broadening is very extensive, any non-linearity due to the tails of the flyback pulse will appear as a symmetrical distortion of the picture: this is less obvious to the eye than assymetrical distortion.
  • FIGS. 3 and 4 illustrate the phase detector 3 of FIG. 1 which is designed to compare the phase of the line flyback pulse with both the leading and trailing edges of the H-sync pulse in accordance with the present invention.
  • the line flyback pulses from the line output stage 6, FIG. 1 are applied to an input 15. Pulses appearing at the input 15 are applied to the input of a Schmitt trigger 16 through a resistor 17. Diodes 18 and 19 connected between a voltage supply of +5 volts and ground ensure that the voltage levels are appropriate for the Schmitt trigger 16 which may be constituted by the Schmitt trigger in a Texas Instruments SN 7414 integrated circuit.
  • the output from the trigger 16 is labelled B and represents a shaped flyback pulse which is a square pulse whose leading and trailing edges coincide with those of the line flyback pulse. This signal (B) is used as the timing reference.
  • the line flyback pulses are also applied to a second Schmitt trigger 20 through a resistor/capacitor differentiating network 21, 22, diodes 23 and 24 again ensuring voltage level compatability for the trigger and subsequent logic.
  • the resistor 21 and capacitor 22 may be arranged as an integrator with resistor 21 connected between terminal 15 and the input to Schmitt trigger 20 and capacitor 22 connected in parallel with diode 24 to ground.
  • the output of the Schmitt trigger 20 is labelled C and represents a signal that changes state shortly after the peak of the flyback pulse. Since the peak is prone to variation in shape, some jitter is present on signal C. It is not, therefore, used as a timing reference, but only to distinguish between the leading and trailing edges of the shaped flyback signal B.
  • Schmitt trigger 20 is conveniently provided by the integrated circuit SN 7414 which also provides trigger 16. This circuit provides inverted outputs and to obtain the outputs B and C shown in FIG. 3, inverters 39, 40 are required.
  • FIG. 4 shows how the H-sync (A), shaped flyback (B) and flyback center or distinguishing (C) signals are combined to produce "early” and "late” signals which are applied to the integrator 4, FIG. 1.
  • the circuit of FIG. 4 comprises four logical AND blocks 25 to 28 which are each labelled with the appropriate logical combination (Boolean notation) which will result in an output.
  • logic block 25 will give an output when the logical combination A AND NOT B AND NOT C is present at its input.
  • the outputs of the logic blocks 25 and 26 are combined in an OR gate 29 to give the "early” pulse and the outputs of the logic blocks 27 and 28 are combined in an OR gate 30 to give the "late” pulse.
  • the NOT A, NOT B, and NOT C signals are obtained by means of invertors 31 to 33 respectively.
  • the circuit of FIG. 4 can be formed using a Texas Instruments SN 74153 integrated circuit, the numbers in brackets representing the pin numbers of that integrated circuit. Should the 74153 circuit be used, the outputs of the Schmitt triggers 16 and 20 of FIG. 3 would be connected respectively to pins numbered (2) and (14) of the integrated circuit. There are two inverters within this integrated circuit which are connected to the pins numbered (2) and (14) and, in practice, comprise the inverters 39 and 40 of FIG. 3.
  • the phase detector compares the phases of the input signals on both leading and trailing edges. Any difference in length of the two pulses when the pulses are in the correct phase results in an "early" pulse at one edge and a "late” pulse at the other edge of equal duration.
  • FIG. 5 shows, on the left hand side, the waveforms for the case where pulse A is shorter than pulse B and, on the right hand side, waveforms for the case where pulse A is longer than pulse B.
  • FIG. 6 shows the waveforms which occur when the flyback pulse is out of phase, occuring late or early with respect to the H-sync pulse.
  • the time integral of the difference between the "early” and “late” pulses is generated by the integrator 4 and is supplied to VCO 5 as an error signal which is used to bring the line flyback pulse into the correct phase relationship with the H-sync pulses.
  • the desired comparison of the integrals of the early and late pulses can be effected in any convenient way, for example, by use of a class B charge pump integrator having two current sources controlled by the early and late pulses, with the two sources connected in parallel with respect to a capacitor.
  • pulses A and B are of precisely equal length, it is necessary to guard against the "dead space" condition. This can be done by introducing a delay in certain of the A signal paths.
  • FIG. 7 shows how this delay may be introduced by using a number of inverters 34 to 36 and a resistor/capacitor network 37, 38. These circuits are provided on the aforementioned integrated circuit SN 7414. The numbers in brackets represent the pin numbers of the SN 74153 integrated circuit of FIG. 4.
  • the main advantage of using 2-edge phase detection is that the line flyback pulse is forced to center itself on the horizontal synchronization pulse. Any widening of the flyback pulse takes place equally on the leading and trailing edges so that consequently the picture remains centered on the CRT screen. Twice as much widening can be tolerated before the flyback encroaches on the picture area, or alternatively the allowance for widening can be halved. Any non-linearity due to the tails of the flyback pulse appears as a symmetrical distortion of the picture which is less obvious to the eye than the asymmetrical distortion of the prior art.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
  • Details Of Television Scanning (AREA)
  • Transforming Electric Information Into Light Information (AREA)
US06/080,889 1979-08-15 1979-10-01 Line scan circuits for cathode ray tube displays Expired - Lifetime US4283662A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB7928391A GB2056823A (en) 1979-08-15 1979-08-15 Line scan circuit for crt display
GB28391/79 1979-08-15

Publications (1)

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US4283662A true US4283662A (en) 1981-08-11

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US (1) US4283662A (fr)
EP (1) EP0024476B1 (fr)
JP (1) JPS5630367A (fr)
BR (1) BR8005053A (fr)
CA (1) CA1141041A (fr)
DE (1) DE3067418D1 (fr)
GB (1) GB2056823A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686567A (en) * 1984-09-28 1987-08-11 Sundstrand Data Control, Inc. Timing circuit for varying the horizontal format of raster scanned display
US4885638A (en) * 1982-03-31 1989-12-05 Ampex Corporation Video device synchronization system
CN102088541A (zh) * 2009-12-02 2011-06-08 康佳集团股份有限公司 一种视频行同步的恢复方法、装置及电视机

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682121A (en) * 1985-02-04 1987-07-21 International Business Machines Corporation Phase discriminator and data standardizer
US4754330A (en) * 1985-04-03 1988-06-28 Hazeltine Corporation Display deflection control loop
JPS6287443A (ja) * 1985-10-09 1987-04-21 日本磁力選鉱株式会社 製鋼スラグの処理方法
US4872055A (en) * 1987-02-04 1989-10-03 U. S. Philips Corporation Line synchronizing circuit in a picture display device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979640A (en) * 1975-07-30 1976-09-07 Gte Sylvania Incorporated Horizontal deflection system
US4028729A (en) * 1975-03-25 1977-06-07 Bell & Howell Company Provision and display of video signals

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3891800A (en) * 1971-03-16 1975-06-24 Philips Corp Line time base in a television receiver
JPS535014B2 (fr) * 1972-08-18 1978-02-23
JPS57701B2 (fr) * 1973-05-04 1982-01-07
NL169811C (nl) * 1975-10-03 1982-08-16 Philips Nv Beeldregelsynchronisatieschakeling, alsmede televisieontvanger daarvan voorzien.
NL7714033A (nl) * 1977-12-19 1979-06-21 Philips Nv Televisie-ontvanger met een lijnsynchroniseer- schakeling.

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028729A (en) * 1975-03-25 1977-06-07 Bell & Howell Company Provision and display of video signals
US3979640A (en) * 1975-07-30 1976-09-07 Gte Sylvania Incorporated Horizontal deflection system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4885638A (en) * 1982-03-31 1989-12-05 Ampex Corporation Video device synchronization system
US4686567A (en) * 1984-09-28 1987-08-11 Sundstrand Data Control, Inc. Timing circuit for varying the horizontal format of raster scanned display
CN102088541A (zh) * 2009-12-02 2011-06-08 康佳集团股份有限公司 一种视频行同步的恢复方法、装置及电视机

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Publication number Publication date
DE3067418D1 (en) 1984-05-17
CA1141041A (fr) 1983-02-08
JPS6147026B2 (fr) 1986-10-17
EP0024476B1 (fr) 1984-04-11
JPS5630367A (en) 1981-03-26
GB2056823A (en) 1981-03-18
BR8005053A (pt) 1981-02-24
EP0024476A1 (fr) 1981-03-11

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