1317474 12064twf2.doc/d 97-04-09 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種視訊資料存取方法，且特別是 關於一種高效能之視訊資料存取方法。 疋 【先前技術】 、，隨著科技的發達’人們對於高晝質影像的追求也曰益 ，加’以致如液晶電視、電漿電視、電腦監視器·..等顯示 器也日益趨向於具有高解析度。為了配合高解析度顯示器 對於大量影像資料的需求，使得影像訊號處理電路之記憶 體控制器需要大量存取記憶體中之視訊資料。因此，如何 提高記憶體控制器對於記憶體中之視訊資料的存取效 能’乃成為一不可忽視之課題。 一請參考第1圖所示，其為一種影像訊號處理電路方塊 示意圖。圖中顯示，此影像訊號處理電路首先會自如光碟 機、電腦等提供影像之裝置的視訊端子接收類比視訊訊號 Video-in，然後經類比數位轉換器（Anal〇g t〇 Digital1317474 12064twf2.doc/d 97-04-09 IX. Description of the Invention: [Technical Field] The present invention relates to a video data access method, and more particularly to a high performance video data access method.疋[Previous technology], with the development of technology, 'people's pursuit of high-quality images is also beneficial, so that LCDs, plasma TVs, computer monitors, etc., etc. are also increasingly tending to have high Resolution. In order to meet the demand for a large amount of image data in a high-resolution display, the memory controller of the image signal processing circuit requires a large amount of access to the video data in the memory. Therefore, how to improve the memory controller's accessibility to video data in memory is a problem that cannot be ignored. Please refer to FIG. 1 , which is a block diagram of an image signal processing circuit. The image signal processing circuit firstly receives an analog video signal Video-in from the video terminal of the device providing the image, such as an optical disk drive or a computer, and then passes through an analog digital converter (Anal〇g t〇 Digital).
Converter，簡稱ADC) no轉換為數位型式的視訊訊號， 再猎由位準調整器（Level Adjuster) 120調整至適當的 訊號位準’而分別送至三維梳型資料控制器（3Dc〇mbdata controller) 130、党度色度解碼器（γ/c decoder) 160 和記憶體控制器（memory controller) 140。記憶體控制 器140則將接收之數位視訊資料寫入記憶體15〇，以暫存接 收之數位視訊資料。 1317474 12064twf2.doc/d 97-04-09Converter, referred to as ADC) no conversion to digital type of video signal, and then calibrated by level adjuster (Level Adjuster) 120 to the appropriate signal level 'and sent to the 3D comb data controller (3Dc〇mbdata controller) 130. A party chrominance decoder (γ/c decoder) 160 and a memory controller 140. The memory controller 140 writes the received digital video data to the memory 15 to temporarily store the received digital video data. 1317474 12064twf2.doc/d 97-04-09
另一方面，圖中之亮度色度解碼器（Y/C dec〇der) 160會經由記憶體控制器14〇讀取儲存之數位視訊資料，並 配合，自位準調整器12〇與三維梳型資料控制器13〇之資 料解碼產生党度色度資料並傳送至記憶體控制器H 記憶體控制1114_將接收之亮度色度資料寫入記憶體 150，以暫存接收之亮度色度資料。 此外，圖中之反交錯資料控制器（De_interlaceData Controller) 170也會經由記憶體控制器14〇讀取儲存之亮 度^度I料’並將資料排序為所需的資料格式後，輸出至 反父錯處理器（De—interlace Processor) 180。反交錯 處理器180會將所輸人的龍作反交錯處理，再將處理^ 的非交錯資料傳送至記憶體控糖14G。記憶體控制哭⑽ f將接收之非交錯資料寫入記憶體150，以暫存接收之非 ^錯資料。而顯示控制器（Display c〇ntr〇Uer)⑽ 藉由記憶體控制器丨4〇讀取暫存之非交錯資料，並加以虑 理（如縮放影像或晝面影像調整等）後輸出至顯示器。处 2述說明中可知，影像訊號的處理必需對記&體做 =的存取動作。因此，如何提高記憶體控制轉於記情 體中之視訊資料的存取效能，以提高對記憶體的存取二 利用率、化硬體料f路及降低系統的操作時脈= 十分重要之課題。 貝待 【發明内容】 有鑑於此’本發明之目的是提供—種視訊資料存取方 1317474 12064twf2.doc/d 97-04-09 由高效能的記憶體存取方法，而提高對記憶體 利料、簡化硬體設計電路及降低系統的操作 Η寺脈。 為達上歧其他目的，本發明提供—祕訊資料存取 、二可_於存取具有至少兩個記,it區塊之記憶體的視 =資料，其巾當記憶體本㈣财至少兩個記憶組(Bank) ^每-記憶组即可為—記龍塊，而#記憶體本身只有 一個記憶組時，每—記㈣塊可由—記憶體或記憶模組來 組，:此視訊資料存取方法包括下列步驟：接收—數位視 訊資料；以及將接收之數位減㈣依次輪流g人記憶體 之不同記憶區塊中。 當欲讀取儲存之數位視訊資料時，則可依相同之順 序’而依次輪流讀取儲存於記憶體之不同記憶區塊中的數 位視訊資料’以供後續亮度色度解碼處理。 本發明另提供一種視訊資料存取方法，可適用於存取 具有至少兩個記憶區塊之記憶體的視訊資料，其中當記憶 體本身即具有至少兩個記憶組（Bank)時，每一記憶組即可 為一記憶區塊，而當記憶體本身只有一個記憶組時，每一 記憶區塊可由一記憶體或記憶模組來組成。此視訊資料存 取方法包括下列步驟：接收一亮度色度資料；以及將接收 之亮度色度資料依次寫入記憶體之一記憶區塊，且當寫完 一圖場之亮度色度資料時，將下一圖場之亮度色度資料依 认寫入s己憶體之另一記憶區塊。 當欲讀取儲存之亮度色度資料時，則依次輪流讀取儲 1317474 97-04-09 12064twf2.doc/d 存於記憶體之不同記憶區塊中的亮度色度資料，來取得不 同圖場之相同位置像素的資料，以利於反交錯處理。 本發明又提供一種視訊資料存取方法，可適用於存取 具有至少兩個記憶區塊之記憶體的視訊資料，其中當記憶 體本身即射至少_記憶⑽ank)時 ，每一記憶組即可 二，憶區塊’而當記憶體本身只有-個記憶組時，每-^隐區塊可由—記憶體或記憶漁綠成。此視訊資料存 包括下列步驟：接收非交錯資料；以及將非交錯資 料依輪流寫人記憶體之不同記憶區塊。 而π取儲存之非父錯資料時，則可依相同之順序， #資=流f Γ儲存於記憶體之不同記憶區塊中的非交 錯貧枓，以供後續處理與顯示。 rT A /、』在存取則一記憶組後之轉換等待週期 系統的操作ϊγ細可簡化硬體設計魏及降低 顯易ί讓其他目的、特徵、和優點能更明 說明如下：、糾土實施例’並配合所附圖式，作詳細 實施方式】 以下將以具有4個記憶組（Bank)、列位址長度⑴立 1317474 97-04-09 I2〇64twf2.doc/d 70、行位址長度8位元、資料寬度為32位元之64m位元容量 的同步動態隨機存取記憶體（SDRAM)來說明，其中將每 一記憶組視為一記憶區塊。當然，如熟習此藝者所知，以 上之特定規格的記憶體只是為了說明及瞭解本發明，而非 只施本發明所必須者。例如，可以依不同需求來選擇具有 不同記憶組數之記憶體，或當記憶體僅有一個記憶組時， 可以使用多個記憶體或記憶模組來實現，此時，每一記憶 體或記憶模組即為本實施例中之記憶區塊。 請參考第2圖所示，其為根據本發明較佳實施例之記 憶體配置示意圖。在本實施例中係假設第1圖之影像處理 電路需要暫存4個圖場（Field)的資料，一般而言，交錯式 掃描之一個圖框（Frame)包含兩個圖場，但無論需暫存之 圖場數為何，只要相應變更記憶體配置，即可將其應用於 各種不同之場合。 如第2圖所示，此記憶體150具有Banld、Bank2、Bank3 及Bank4等共4個記憶組，每一記憶組有2048個列位址及 256個行位址’每一記憶位址的資料寬度為32位元，因此， 其總容量為64M位元。其中，為配合第1圖之影像處理電路 的需求，亦即，暫存數位視訊資料、亮度色度資料及非交 錯資料等需求，因而將記憶體150劃分為3D comb、 Deinterlace與Display等不同記憶區，每一記憶區分別儲 存數位視訊資料、亮度色度資料及非交錯資料。此外，每 一記憶區共可儲存Fieldl〜Field4等共4個圖場之資料，其 配置則分別參考第2圖所示。當然，如熟習此藝者所知， 1317474 12064twf2.doc/d 97-04-09 其配置順序是可以任意變化的，例如圖中之3D comb、On the other hand, the luminance chrominance decoder (Y/C dec〇der) 160 in the figure reads the stored digital video data via the memory controller 14 ,, and cooperates with the self-level adjuster 12 〇 and the three-dimensional comb. The data controller of the type data controller 13 decodes and generates the party colorimetric data and transmits it to the memory controller H. The memory control 1114_ writes the received luminance chrominance data into the memory 150 to temporarily store the received luminance chrominance data. . In addition, the de-interlace data controller (De_interlaceData Controller) 170 in the figure also reads the stored brightness ^I material' through the memory controller 14 and sorts the data into the required data format, and then outputs it to the anti-parent. De-interlace Processor 180. The deinterlacing processor 180 deinterlaces the input dragons and transmits the non-interlaced data of the processing to the memory control sugar 14G. Memory Control Cry (10) f Writes the received non-interlaced data to the memory 150 to temporarily store the received non-error data. The display controller (Display c〇ntr〇Uer) (10) reads the temporarily stored non-interlaced data by the memory controller 〇4〇, and takes care (such as scaling image or kneading image adjustment) to output to the display. . As can be seen from the description in Fig. 2, the processing of the video signal must be performed on the access & Therefore, how to improve the access performance of the video data in the memory control to improve the accessibility of the memory, the utilization of the hard material, and the operating clock of the system are important. Question. In view of the above, the object of the present invention is to provide a video data access party 1317474 12064twf2.doc/d 97-04-09 by a high-performance memory access method, and improve the memory Material, simplify the hardware design circuit and reduce the operation of the system. For other purposes, the present invention provides - access to secret information, and access to data having at least two records, memory of the it block, and the memory of the memory (four) is at least two Each memory group (Bank) ^ per-memory group can be - long block, and # memory itself has only one memory group, each - (four) block can be grouped by - memory or memory module: this video data The access method comprises the steps of: receiving-digital video data; and subtracting the received digits (four) in turn into different memory blocks of the g-person memory. When the stored digital video data is to be read, the digital video data stored in different memory blocks of the memory may be sequentially read and reproduced in the same order' for subsequent luminance chroma decoding processing. The invention further provides a video data access method, which is applicable to accessing video data of a memory having at least two memory blocks, wherein each memory when the memory itself has at least two memory groups (Bank) The group can be a memory block, and when the memory itself has only one memory group, each memory block can be composed of a memory or a memory module. The video data access method includes the steps of: receiving a luminance chrominance data; and sequentially inputting the received luminance chrominance data into a memory block of the memory, and when writing the luminance chrominance data of a field, The luminance chrominance data of the next field is written into another memory block of the suffix. When the stored luminance and chrominance data is to be read, the luminance and chrominance data stored in the different memory blocks of the memory are sequentially read and read to obtain different fields. The data of the same position pixel to facilitate deinterlacing. The invention further provides a video data access method, which is applicable to accessing video data of a memory having at least two memory blocks, wherein each memory group can be used when the memory itself is at least _memory (10) ank) Second, the memory block 'and when the memory itself has only one memory group, each - ^ hidden block can be - memory or memory fish green. The video data includes the steps of: receiving non-interlaced data; and writing non-interlaced data to different memory blocks of the human memory in turn. When π is used to store non-parent data, the non-intermittent inferiority stored in different memory blocks of the memory can be processed and displayed in the same order. rT A /, 』After accessing a memory group, the conversion wait period system operation ϊ γ fine can simplify the hardware design and reduce the ease. ί Let other purposes, features, and advantages can be more clearly explained as follows: The embodiment will be described in detail with reference to the drawings. The following will have four memory groups (Bank), column address length (1), 1317474 97-04-09 I2 〇 64 twf2.doc/d 70, row position A synchronous dynamic random access memory (SDRAM) having a bit length of 8 bits and a data width of 32 bits and a 64 m bit capacity is illustrated, wherein each memory group is regarded as a memory block. Of course, as is known to those skilled in the art, the memory of the specific specifications is only intended to illustrate and understand the invention, and not to practice the invention. For example, the memory with different memory groups can be selected according to different needs, or when the memory has only one memory group, multiple memory or memory modules can be used, in this case, each memory or memory The module is the memory block in this embodiment. Please refer to FIG. 2, which is a schematic diagram of a memory structure according to a preferred embodiment of the present invention. In this embodiment, it is assumed that the image processing circuit of FIG. 1 needs to temporarily store data of four fields. Generally, one frame of the interlaced scan includes two fields, but What is the number of temporary map fields, as long as the memory configuration is changed accordingly, it can be applied to a variety of different occasions. As shown in FIG. 2, the memory 150 has four memory groups, Banld, Bank2, Bank3, and Bank4, and each memory group has 2048 column addresses and 256 row addresses' data of each memory address. The width is 32 bits, so its total capacity is 64M bits. In order to meet the requirements of the image processing circuit of FIG. 1 , that is, temporarily storing digital video data, luminance chrominance data and non-interlaced data, the memory 150 is divided into different memories such as 3D comb, Deinterlace and Display. The area, each memory area stores digital video data, luminance chrominance data and non-interlaced data. In addition, each memory area can store a total of four fields of Field1~Field4, and the configuration is shown in Figure 2. Of course, as is familiar to those skilled in the art, 1317474 12064twf2.doc/d 97-04-09 can be arbitrarily changed in order of configuration, such as the 3D comb in the figure.
Deinterlace與Display等3個記憶區之配置亦可如第3圖 (a)〜（f)等各種不同之配置方式。 請配合第1圖及第2圖所示，當第1圖之記憶體控制器 140欲將接收之數位視訊資料寫入記憶體15〇時，可以將數 位視訊資料儲存於第2圖之3D comb記憶區。為了達到最佳 之存取效能，其寫入方式可以如第2圖所示地將數位視訊 資料依次輪流寫入記憶體之不同記憶組，以便可以在 存取前一記憶組（如Bankl)後之轉換等待週期（Turn Around Cycle)時，繼續地存取另一記憶組（如Bank2)之資 料’而無須浪費等待之週期。其中，數字卜2、3、4...... · 等係代表每一次存取記憶體之資料順序，其資料量可以為 以突發（burst)模式寫入之包括1、2、4或8個記憶位址的 批次資料。 當第1圖之亮度色度解碼器160欲經由記憶體控制器 140來讀取儲存之數位視訊資料，以便進行亮度色度解碼 B寸，則可依寫入時相同之順序，而依次輪流讀取儲存於記 憶體150之不同記憶組中的數位視訊資料，以供後續亮度 色度解碼處理時使用。 當第1圖之亮度色度解碼器160解碼產生亮度色度資 料並傳送至記憶體控制器14〇後，記憶體控制器14〇則可以 將亮度色度資料儲存於第2圖之Deinterlace記憶區。如第 2Q所示地為了考慮將來可以有效率地讀取儲存於纪恃 體150之不同圖場的亮度色度資料，因此，在將接收^ 1317474 12064twf2.doc/d 97-04-09 度色度資料寫入記憶體150時，係將亮度色度資料依次寫 入記憶體150之一記憶組（如Bankl)，且當寫完—圖場「二 _之亮度色度資料時，將下—圖場(如 度色度資料依次寫入記憶體15〇之另一記憶組（如 Bank2)，以便暫存接收之亮度色度資料。 故當第1圖之反交錯資料控制器丨7 〇欲經由記憶體控 制器140來讀取儲存之亮度色度資料，以便進行反交錯處 理時丄則可依:欠輪流讀取儲存於記憶體15G之不同記憶組 中的亮度色度資料’而取得不關場之相同位置像素的 料i以利於反交題理時制。且如前述地在讀取亮度色 度貝料時，係可以高效率地讀取^錢浪費連續讀取 記憶組之轉換等待週期。 此外’當第1圖之記憶體控制器140欲將接收自反交錯 處理器刚之非交錯資料寫人記憶體150時，便可以將非交 錯資料儲存於第2圖之Display記憶區。同樣地，為了達到 最，之存取效能’其寫人方式係如第2圖所示地將非交錯 育料依次輪流寫人記憶體15G之不同記憶組（如圖中之卜 mm資料），以便可以在棘前—錄組(施咖） ^ 、 I週期時，繼續地存取另一記憶組（如Bank2) 之— 貝料二2無須浪費等待之週期。 p : ΐ1圖之顯不控制器190欲經由記憶體控制器140 來項取儲存之非交钙 序，來依次卜、時’則亦可依寫人時相同之順 m仙'哨取儲存於記憶體150之不同記憶組中的 非父錯資料’以供後續顯示處理時使用。 1317474 12 064twf2.d〇c/cj 97-04-09 雖Mi本發明已以較佳實施例揭露如上，然其並非用 二任何熟習此技藝者，在不脫離本發明之精;, 和耗圍内，畜可作各種之更動與潤飾，因此本 範圍當視_之申請專職圍所界定者鱗。t之保護 【圖式簡單說明】 第1圖係顯示-種影像訊號處理電路方塊示音圖。 第2圖係顯示根據本發明較佳實施例之記憶體配置示 思圖。 體轉树賴錄劇4料同記憶 【主要元件符號說明】 100 :類比數位轉換器 120 :位準調整器 130 .二維梳型資料控制哭 140 :記憶體控制器 15 0 .記憶體 160 :亮度色度解碼器 170 :反交錯資料控制器 180 :反交錯處理器 190 :顯示控制器The configuration of three memory areas, such as Deinterlace and Display, can also be configured in various ways, such as (a) to (f) in Figure 3. Please refer to FIG. 1 and FIG. 2 . When the memory controller 140 of FIG. 1 wants to write the received digital video data into the memory 15 , the digital video data can be stored in the 3D comb of FIG. 2 . Memory area. In order to achieve the best access performance, the writing method can sequentially write the digital video data into different memory groups of the memory as shown in FIG. 2, so that after accessing the previous memory group (such as Bankl) During the Turn Around Cycle, the data of another memory group (such as Bank2) is continuously accessed' without wasting the waiting period. Among them, the number 2, 3, 4, ..., etc. represent the order of data accessing each memory, and the amount of data can be written in burst mode including 1, 2, 4 Or batch data for 8 memory addresses. When the luminance chrominance decoder 160 of FIG. 1 wants to read the stored digital video data via the memory controller 140 for performing luminance chrominance decoding B-inch, it can be sequentially read in the same order as when writing. The digital video data stored in different memory groups of the memory 150 is used for subsequent luminance chroma decoding processing. When the luminance chrominance decoder 160 of FIG. 1 decodes and generates the luminance chrominance data and transmits it to the memory controller 14 记忆, the memory controller 14 储存 can store the luminance chrominance data in the Deinterlace memory region of FIG. . As shown in the 2Q, in order to consider the future, the luminance chromaticity data stored in the different fields of the corpus callosum 150 can be efficiently read, and therefore, the color will be received at 1317474 12064 twf2.doc/d 97-04-09 When the degree data is written into the memory 150, the luminance and chrominance data are sequentially written into one memory group of the memory 150 (such as Bankl), and when the image field "two ray luminance chromaticity data is written, the next _ The field (such as the chrominance data is sequentially written into another memory group of the memory 15 (such as Bank2) to temporarily store the received luminance chrominance data. Therefore, when the de-interlaced data controller of Figure 1 is 〇7 When the stored luminance chrominance data is read by the memory controller 140 for deinterlacing, the illuminance chromaticity data stored in the different memory groups of the memory 15G can be read in the following manner. The material i of the pixel at the same position of the field is closed to facilitate the counter-processing time. As described above, when reading the luminance chrominance material, the conversion waiting period of the continuous reading memory group can be read with high efficiency. In addition, 'When the memory controller 140 of Figure 1 is intended to receive When the deinterlacing processor writes the human memory 150 just after the non-interlaced data, the non-interlaced data can be stored in the Display memory area of Fig. 2. Similarly, in order to achieve the most, the access performance is as follows. In the second figure, the non-interlaced feeds are sequentially written in different memory groups of the human memory 15G (as shown in the figure), so that it can be in the front of the spine-recording group (Shi) ^, I cycle, Continue to access another memory group (such as Bank2) - Betting 2 2 does not have to waste the waiting period. p : The display controller 190 of Figure 1 wants to access the stored non-crossing calcium sequence via the memory controller 140. In order to follow the same time, the same non-parent data stored in the different memory groups of the memory 150 can be used for subsequent display processing. 1317474 12 064twf2. D〇c/cj 97-04-09 Although the invention has been disclosed in the preferred embodiments as above, it is not intended to be used by those skilled in the art, without departing from the spirit of the invention; Make a variety of changes and refinements, so this scope is defined as the application of the full-time definition The protection of t [simplified description of the drawings] Fig. 1 shows a block diagram of a video signal processing circuit. Fig. 2 is a diagram showing the memory configuration according to a preferred embodiment of the present invention. Recording 4 material and memory [main component symbol description] 100: analog digital converter 120: level adjuster 130. two-dimensional comb data control cry 140: memory controller 15 0. memory 160: luminance chrominance decoding 170: de-interlaced data controller 180: de-interlacing processor 190: display controller