JPS61500637A - Video display system with increased horizontal resolution - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] with increased horizontal resolution Video display system The present invention relates to a video display system, and more particularly to a video display system. It relates to a device for improving the resolution of a system.

2. Description of prior art To this day, users have never been able to access information stored or generated by computers. A variety of information data using an interactive computer system that can be operated. display system has been proposed and adopted.

This information may include text, graphs, faxes, videos, etc. . With the advent of VLSI circuits in the past few years, low-cost microprocessors The Sessa system is now available for widespread use. For this reason, today central databases and the general public can use these systems to access information. is now considered to be reasonable in terms of cost.

Today, there are two information display systems in the telecommunications industry that use a central database. Stems, view data and teletext have been introduced; The potential demand is huge. In the Pyudata system, video data Both parties have the ability to display pages of text and images on a display. Interactive services can be provided. In the teletext system, video One-way circular communication that displays pages of text and graphics on a display Information services are provided.

At the customer's endpoint for both video data and teletext systems It is necessary to provide some type of electronic module with screen control information. Ru. An example of such a module is described in U.S. Pat. No. 4,396,989. explained. This type of module assembles textual and graphical information. controls for ringing and display on the customer's display terminal (e.g., a regular TV receiver).

The usual approach to displaying this textual and graphical information is local memory called cut brain memory or full frame buffer A video display circuit with video memory is used. This typical On a typical screen, the device refreshes on the order of 60 times per second, The local memory containing the image description is transferred to external circuitry located within the electronic module. Therefore, it is retained. This can be avoided, resulting in bandwidth savings. becomes possible.

Existing view data and teletext using full frame buffer In a system, video memory typically has N pixels per pixel (PEL). It is designed to have 2N colors, so it is possible to display 2N colors. It is. When a display with H horizontal PELs and V vertical PELs can be requested requires NXHXV pit video memory. Also, the horizontal decomposition of 2H If a capable display is required, twice this number of bits in video memory is required. Become.

The horizontal resolution of existing display devices is limited due to the limited horizontal scanning frequency. cannot be easily increased.

For this reason, the number of horizontal PELs on the screen of a home TV receiver is Although it has a large resolution, it is limited to about 256. Therefore, the corresponding horizontal frequency scan and video display without increasing memory requirements. It is desirable to increase the horizontal resolution of the ray device and take full advantage of this resolution capacity. Ru.

Summary of the invention The present invention enables color video processing without proportionally increasing the size of video memory. To provide a device for doubling the apparent resolution of a display system. This outfit The system stores one or more pieces of data in video memory for each PEL on the screen. It is required to add bits. If the decryption logic uses this added one or more more than or equal to the number of bits represented by that bit for the horizontal and vertical PEL. color information to be displayed should be displayed at the current border, like on a normal device. or after being delayed by a fraction of a PEL clock cycle. Determines what should be displayed on the offset border. The invention is detailed below. and will become more apparent from the accompanying drawings.

Brief description of the drawing Figure 1 shows an arbitrary line segment of a PEL drawn using a standard bit-brane. Fig. 2 shows the details of the PBL arrangement according to the invention; Figure 3 shows the information display system. A schematic circuit diagram suitable for operation according to the method of the invention is shown: FIG. FIG. 3 is a timing diagram showing waveforms of various signals used in the present invention.

detailed description Displaying color images on a video display system is very common. A typical method is to maintain a description of the image in local memory.

This local memory is associated with the display terminals and is usually referred to as video memory. It will be revealed. Memory is stored in a bit-brain or full-frame buffer. It is organized to correspond to the PEL of the screen on a 1:10 basis. For example, a certain The image was displayed in 16 colors using 256 horizontal PBL x 200 vertical PFJL. If not, memory organized as 256x200 addresses is typically used.

Here, each address accesses 4 bits (2'=16 bits). synchronization and the decoding logic sequentially reads these memory locations during the reference clock read cycle. to access. In each read cycle, the video drive circuit This 4-bit output is the color information signal required by the display terminal (e.g. for example, red, green, and blue voltage levels).

Figure 1 shows an arbitrary line of PEL drawn using a conventional bit-brane. The details of the segment are shown. In this drawing, for the two vertical steps of horizontal steps H of the same size are taken, resulting in a very jagged line. Ru. Therefore, with conventional bit-brain resolution, the smoothness of drawing this image is It turns out that there are limits to.

Fig. 2 shows the bit for each PBL according to the present invention with one pit added to the brain. Thus, details of any line segment of the drawn PEL are shown. vertical step V is the same size as before, but the horizontal step size H is reduced by half and the As a result, it can be seen that a much smoother image is provided. this device To get the same results without using is necessary. This means that the certain image mentioned above has 256 horizontal PEL Easy to understand by looking at an example of displaying in 16 colors using direct PEL can. In this example, 256 x 200 x 4 = 204,800 bits Memory is required. In order to obtain the same horizontal resolution with known equipment, Mori: Double the size, 512X200X4=409.600 Bits are required. But according to the new device, the memory is 256X20ox 5 = 256,000 pitts, just a 25% increase, not a 100% increase. It only requires an increase of cents. This effect becomes even more pronounced when there are many colors. . A display system that uses 256 colors and requires 8 bits per PBL. In the system, the bit increase with the present invention is only 12.5 percent.

The extra bits do not explain the color information; they explain how the bits of color information are explained. Carry location information regarding what should be interpreted. Location information relative to the screen is usually bit Determined by synchronization and decoding circuitry rather than stored within the brain . However, in this device, this additional bit is also located within the bit-brane, The decoding logic determines the horizontal PEL and vertical PEL by its bits. color information to be displayed should be displayed at the current border as in conventional devices. , or the color information is delayed by a few PEL clock cycles. used to determine whether to avoid plotting on offset boundaries.

The circuitry required to implement the device according to the present invention in an information display system The logic is very simple, and if we add one bit per PEL to Figure 6, An example is shown below. Furthermore, this additional one pit can be used for any given color index. The addition of ensuring that the output is always at least 1 and that there are only lock cycles. give the advantages of This increased dwell time is often due to visual display Ensure that the frequency response of the equipment (e.g. television receiver) cannot be exceeded. It is necessary to

Starting with the explanation of Figure 3, the standard is to run at a PEL speed of N PELs per second. Clock signals are typical timing and synchronization circuits in information display systems. is supplied onto line 11 from These circuits and decoding circuits also use the same clock. The video memory 20 is sequentially addressed in sequence, and the rising edge timing of this clock signal is It is assumed that the outputs of bit brains 21 to 24 are also stable before the edge. do. This uses the clock signal on line 11 to generate memory addresses. This can easily be achieved by a small delay from the clock used.

The positional information that determines how the bits of color information should be interpreted is It is included in the gate brain 24 and connected to the inverter 30 and the AND gate through the line 12. is provided to one of the two inputs of gate 31 and to flip-flop 40. line When the position information signal on 12 is 0, AND gate 62 has an inverter as an input. Logic 1 signal from the data controller 30 through the clock on line 11 to the flip-flop 4. 0 clock input and the remaining inputs of AN, D gate 31.

The position information present during the previous clock cycle is stored in the Q of flip-flop 40. C that can be reflected in the output (If the output is logic 1, it means that the output was not active in the previous clock cycle.) The signal on pin 12 indicates a zero, and the output of AND gate 32 At the rising edge of the clock signal, the high value is passed through the zero gate 34 to the register 60. is loaded with the appropriate color values. The output of register 60 contains color index information. - to a lookup table 70 where the appropriate color is selected. digital a The analog converter 80 converts the digital output of the lookup table 70 into a CRT display device. analog signals used to drive red, blue, and green guns (not shown). exchange.

When the position information signal on line 12 is a logic 1, the output of AND gate 31 is In the middle of that clock cycle, the position information signal is a logic 1, and the position information signal is a logic 0. Data is input to register 60 after half a clock cycle compared to when Load. The position information signal was set to logic 1 in the previous cycle, and in the current cycle When a logic 0, no new color information is loaded. This logic is a register A truth table showing the effect of 60 on the output is shown below, where Yu is currently il indicates the previous clock cycle. Pl is Ku Indicates the position bit output during the period of the lock cycle, vl is the cycle i shows the color value output during the period of .

color index Pi Pi+1 cycle 1 cycle Breath+1Q OVi Vi Vi+I Vi + 10 1 V i V i V i V i + 11 0 viiv i vi Vi 11ViIViViVi+1 If (Pi, Pi + 1) = (1, 0), V1+1 is determined as the output. Please note that this will not be provided.

This means that for this, vl is the clock cycle in the second half of cycle 1. This is because only one-half has to be provided as output. Color fingers mentioned above The requirement that the duration of the number output be at least one cycle may apply to certain visual displays. Assuming it is not needed in the play equipment, in this case we can simplify the logic and use the truth table realize that it is possible to fix it.

Diagram 4 is used in the circuit logic shown in Figure 6 or generated using this circuit logic. FIG. 3 is a timing diagram showing the waveforms of some specific signals. This is the clock waveform shows the signal on line 11 from which all timings of this logic circuit can be derived.

Once every clock cycle, the color value (this is the number of pits per PEL) ) and location bit P are accessed. fang As shown in Figure 4, when P is logic 0, the color value is clock cycle The color index output is latched into register 60 at the rising edge of the clock. This occurs roughly coinciding with the first edge of the stack. On the other hand, when P is logical 1, The error value is latched in the middle of the cycle and as a result corresponds to this cycle. The PEL to be used will be shifted by 1/2 PEL. This color information is 17 The ability to shift by 2 PEL provides an apparent increase in horizontal resolution. Ru.

This video display system may be modified without departing from the spirit and scope of the invention. It is possible to achieve this by making many modifications to the system. As an example of this modification By generalizing the above technique, we can define the position of the legend for each PEL in the bit-brane. It is also possible to store information. These legend bits are accessed in order as described above. The bits in the legend are accessed here, but not just for a single 1/2 delay. A delay of 2R can be described. For example, if R=2, 4 delays are possible. These are, for example, 0.1/4.1/2 of PEL and 3/4 slow. You can specify the extension.

This has the effect of increasing the apparent resolution by a factor of four. The 256X200 address in the previous example resolution using conventional methods for screens that require 4 pits per PEL. In order to quadruple becomes. However, using the method according to the invention, 256X200X6=507 , 200 bits. Accordingly, the invention departs from the scope of the appended claims. The present invention can be implemented in many embodiments other than those specifically described.

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Claims (1)

[Claims] 1. A device that receives data from a source; and both horizontal and vertical coordinates. received from said data source including a device for producing color image data with The data is assembled into a video in the form of a color image. In a video display system for displaying on a video display, The stem is horizontal position offset data representative of the received data; and The color image data (21-23) and the position offset data (24) The position offset data is horizontal of the color image data in the first state. Provide an offset value to change the value of the coordinate, and change the color in the second state. Do not provide an offset value to change the value of the horizontal coordinate of the image data. a video camera, characterized in that it includes a device (30-60) for assembling Oday display system. 2. In the video display system according to claim 1, for storing the color image data and the position offset data in memory. device (20); and a device for accessing said memory and refreshing said video display; (60) A video display system further comprising (60). 3. In the video display system according to claim 1, The assembling device assembles the color image data onto the video display. By temporally delaying the display of the color image data in the horizontal direction, A video display system characterized in that it provides said offset value to a reference value. Mu. 4. In the video display system according to claim 3, A plurality of positions where the position offset data can be displayed on the video display. characterized in that it contains one data bit for each of the horizontal and vertical coordinate positions of video display system. 5. In the video display system according to claim 2, The memory further includes a first memory section for storing the color image data. a second memory section for storing the position offset data; and a shift register for selectively receiving the color image data; The output of the register is the state of the position offset data from the second memory section. in response to a first state, the position offset data is set to the video display in a first state. The horizontal display of the color image data on the ray is delayed in time, while , in the second state, there is no time delay in displaying the color image data. A video display system characterized by: 6. In the video display system according to claim 5, The color image data for each of the plurality of horizontal and vertical coordinates is stored on a video device. A video display system characterized by including pixels that can be displayed on a display. stem. 7. In the video display system according to claim 6, The time delay consists of one half of a clock cycle, and the clock cycle It is specified that it is one dwell time for color image data at the horizontal coordinate position of video display system. 8. In the video display system according to claim 7, The positional offset data includes one data bit for each pixel. bit display system. 9. Assembles data received from data sources and colors this data. - A method for displaying an image on a video display in the form of an image, the method comprising: receiving said data from said source; horizontal position representing said received data; Color image data with both target and vertical coordinates and horizontal position offset a step of generating data; and a step of generating the color image data and the positional offset. The position offset data is set to the color image data in the first state. Provides an offset value for changing the horizontal coordinate value of the data in the second state. and provide an offset value for changing the value of the horizontal coordinate of the color image data. A method comprising steps for assembling for ease of use. . 10. A method according to claim 9, in which the assembling step Lani A step that stores the color image data and position offset data in memory. and a step that accesses the memory and refreshes the video display. A method characterized by comprising steps.