JPS62127975A - Picture memory controller - Google Patents

Abstract

PURPOSE:To attain data write of plural picture elements at a high speed by updating m sets (m<=2<n>; n is a positive integer) of values taken by high-order n bits of column address data once in each data write cycle according to the page mode. CONSTITUTION:The m sets of values taken by the high-order n bits of the column address data are updated once at each data write cycle according to the page mode (m<=2<n>; n is a positive integer). The value of the most significant bit of the column address data is updated only once sequentially at each data write cycle to write drawn picture data by 2 lines, that is, by one row. That is, the data write at the page mode is executed by updating the most significant bit WA7 of the column address data WA0-WA7 from 0 to 1 at each data write cycle. Since the drawn data is written on plural picture elements at once, the data write speed is nearly doubled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image memory randomization device, and more particularly to an image memory randomization device for writing multiple pixels.

[Technical Background of the Invention] Generally, there are two types of pixels used in an image memory (hereinafter referred to as a frame memory) that stores drawing data for one frame. One is one dot, which is the smallest unit of the device itself, and is called one physical pixel (hereinafter referred to as a physical pixel). The other one is a collection of several vertical and horizontal dots of the above physical pixels, which is a logical one.
It is called a pixel (hereinafter referred to as a logical pixel).

For example, if we focus on the pixel size in the vertical direction (row direction) of the Videotex system, this corresponds to the size of 2 physical pixels on a high-density screen, and corresponds to the size of 1 physical pixel on a standard screen. Therefore, when writing data on a standard screen, it is necessary to first write drawing data to the upper line of each row, and then write the same data to the lower line. FIG. 9 shows this situation. In FIG. 9, Vt is the physical pixel size in the row direction, and y2 is the logical pixel size which is twice the physical pixel size. When writing data on the standard screen, a row address is specified using the logical pixel size y2 as a row unit.

Note that the above data writing is generally performed by software of a microprocessor.

[Problems in the Background Art] However, as described above, in the configuration in which data is written for each line on a standard screen in a device that is used for both standard screens and high-density screens, compared to data writing in a device that is dedicated to I semi-screens, The data writing process of the microprocessor is doubled. As a result, when image information is sent at high speed, the data writing speed is slower than the information transmission speed, resulting in a problem that real-time data writing cannot be performed.

[Object of the Invention] The present invention has been made in order to cope with the above-mentioned circumstances, and an object of the present invention is to provide a memory control device that can write data to a plurality of pixels at high speed.

[Summary of the Invention] In order to achieve the above object, the present invention writes each data in accordance with the page mode to m (m≦2''; n is a positive integer) values that the upper n bits of column address data can take. By updating once per cycle, drawing data is written for m pixels in units of rows or columns in each data write cycle in the row or column direction.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, 11 is a frame memory. This frame memory 11 is I1 for writing drawing data.
It is a dual port memory with a 0 port and a serial port for reading drawing data for image display.

The display configuration of the frame memory 11 viewed from above is shown in FIG. As shown in the figure, the frame memory 11 has 512 physical pixels in both the column direction (horizontal direction) and the row direction (vertical direction). In terms of the row direction, the logical pixel size of the standard screen corresponds to two physical pixel sizes as described above, and a row address is specified using this as one row.

Further, the frame memory 11 has a 4-pit configuration, and assuming that this corresponds to a pattern of 4 bits in the column direction, the frame memory 11 has 128 column addresses per line. Therefore, on a standard screen, the frame memory 11 has 256 column addresses per row.

From the above, in the frame memory 11 of FIG. 2, both row addresses and column addresses can be accessed using 8-bit address data.

Here, looking at the column addresses per row of the standard screen, each column address on the second line is equal to each column address on the first line.
The value is the sum of 28. Therefore, the column address data on the second line of each row can be obtained by converting the most significant bit 1- of the column address data on the first line from 0 to 1.

This embodiment focuses on this point, and in each data write cycle, the value of the most significant bit of the column address data is sequentially changed to 1.
By updating the data once, two lines of drawing data, that is, one minute of drawing data, are written in each data write cycle.

Specifically, the most significant bit of the column address data is set to 0, the drawing data is written to the first line, the most significant bit is set to 1, and the drawing data is written to the second line. , is repeated for each data write cycle.

Such data writing processing is possible by using a dynamic RAM as the frame memory 11 and by adopting a page mode method for taking in address data to this memory 11.

Here, the page mode method is a method for accessing a plurality of pieces of data by keeping the row address constant and giving a plurality of column addresses to the dynamic RAM.

Now, returning to FIG. 1, the data writing process as described above will be specifically explained. In FIG. 1, address data for writing is row address data WAa to WArs,
Both column address data WAo=WA7 are generated by the microprocessor 12. Column address data WAa output from this microprocessor 12 = WA7
The most significant bit WA7 is fixed at 0, and its value is switched using the OR circuit 13. That is, the OR circuit 13 is supplied with the most significant bit WA7 and the data conversion signal ACHG. This signal ACHG is given from the timing generation circuit 14, and in the first half of each data write cycle (when writing the first line), the signal ACHG is
In the second half of the first half (at the time of fortune-telling on the second line), it becomes 1. Therefore, the output of the OR circuit 13 becomes ○ in the first half of the write cycle and 1 in the second half, and this is the column address data WAo.
~Used as the most significant bit WA7 of WA7.

Here, to explain the timing generation circuit 14, this circuit 14 outputs address data for 1 to the memory 11 in accordance with a write signal WR from the microprocessor 12 and a basic clock CP obtained by decoding the count value of a display counter (not shown). Create various timing signals to be imported into the system. Further, this timing generation circuit 14 switches the contents of the timing signal between the high-density screen mode and the standard screen mode in accordance with the write mode signal WMOD given from the microprocessor 12. That is, in the former mode, the normal timing is created to capture row address data and column address data once each in each data write cycle, and in the latter mode, the page is created to capture column address data multiple times (twice in this example). Create mode timing.

FIG. 3 shows one data write cycle in page mode. Data writing for the standard screen will be explained with reference to FIG. Row address data WAa =WA
ts and column address data WAo to WA7 are simultaneously output from the microprocessor 12 onto the address bus, and these are stored in the address buffer 15.1.
6 is used to provide the gate signal ROW17 from the timing generation circuit 14. Note that the address buffer 16
The most significant bit WA7 of the column address data WAG-WA7 outputted from the OR circuit 13 is the most significant bit WA7.

The address selector 17 selects address data from the address buffers 15 and 1f3 when writing data for a standard screen or high-density screen, and selects the display address from the display counter when reading data for image display. Select data RAo~RA7゜RAa~RA+s,
It is applied to the frame memory 11. This control is performed according to a control signal REF decoded from the count value of the display counter.

1-inclusive address data given to frame memory 1 WA-WA7. WA8 to WAts are taken into the memory 1 in accordance with row 1 column address strobe signals RASW and CASW applied from the timing generation circuit 14. As a result, address data WAo = WA7
．． Drawing data Do given from the microprocessor 12 to the address specified by WAa to WAts
~D3 is outdated. Note that the write pulse W for this write is given from the timing generation circuit 14.

As shown in FIG. 3, the column address strobe signal RASW is output twice in one write cycle in the column direction.
At the second occurrence, the data conversion signal ACHG becomes 1, and the drawing data is written to the second line.

Note that the above-mentioned write row 1 column address strobe signal R
ASW and CASW are supplied to the memory 11 by the strobe 1g selector 18 in accordance with the control signal REF as an alternative to the read row and 2 column strobe signals QRASR and CASR obtained by decoding the count value of the display counter. It has become.

Data writing for a high-density screen requires a column address strobe signal C in one data writing cycle, as shown in FIG.
This is done by normal write processing that outputs the ASW once. Comparing the data write cycle in FIG. 4 with the data write cycle in FIG. This is realized by applying a weight signal WT.

Here, the relationship between writing data to frame memory 11 and reading data from memory 11 will be explained. For example, the memory 11 is a RAM boat consisting of a memory cell array of 256 bits (64 words x 4 bits) and 256 bits (64 words x 4 bits).
When configured with a dynamic RAM having a serial port consisting of a 6 word x 4 bit data register,
As shown in Fig. 5, the data transfer process is performed once every two horizontal scans by the data transfer cycle, which transfers 256 words x 4 bits of data from the 64 words x 4 bits memory cell array to the data register. Just go. Therefore, once data transfer processing is performed, the time until the next data transfer cycle can be spent on refreshing and writing. The relationship between the display period and the write cycle period is shown in FIG. 6. If the write cycle period is outside the transfer cycle period and the refresh period,
Can be set anywhere. Therefore, setting the write cycle period is very easy.

The drawing data transferred to the 256 word x 4 bit data register as described above is read out in 4 bits in parallel according to the lock SC as shown in FIG. This readout output is taken into the parallel/serial conversion circuit 1♦ in accordance with the load pulse LD, and serially read out bit by bit from this circuit 19 in accordance with the display clock CP.

Note that, as shown in FIG. 6, the control signal @REF is O during the write cycle period and 1 during the data transfer cycle period and the refresh cycle period.

As detailed above, in this embodiment, in each data write cycle, the most significant bit WA7 of column address data W A a to W A 7 is updated from 0 to 1 to perform data writing in page mode. This is what I did.

Therefore, according to this embodiment, since drawing data can be written to multiple pixels at once, the data writing speed can be approximately doubled compared to conventional data writing processing, and image information can be transmitted. Even at high speeds, real-time data writing can be performed. FIG. 8 shows a comparison between the conventional data write process A and the data write process B of this embodiment.

Further, in this embodiment, the microprocessor 12 only needs to output the column address data W A a to W A 7 of the first line, and the column address data W A of the second line.
o~WA7 is OR circuit 13 and timing generation circuit 14
Since the data is automatically created by the microprocessor 12, the data writing process in the microprocessor 12 can be halved compared to the conventional method.

In the above explanation, a memory with a built-in data register has been described as the frame memory 11, but it is also possible to connect a register to the memory that can store drawing data for display only during the page mode access time in each data write cycle. good.

Further, the column address data may be updated by an exclusive OR circuit instead of the OR circuit 13.

Furthermore, this invention is applicable not only to data writing using two lines as one line, but also to data writing in general to 2n lines (n is a positive integer yil).
) can be applied to data writing in one line. in this case,
Column address data may be updated with respect to the upper n bits thereof. However, it is of course possible to stop updating column address data in the middle of 2n and make m (m≦2n) lines one row.

Furthermore, in the original embodiment, multiple lines in the row direction were combined into one line, but by changing the correspondence between the display screen and memory, multiple pixels in the column direction were combined into one line.
May be used as a column.

[Effects of the Invention] According to the present invention, drawing data can be written into a plurality of pixels at once in each data writing cycle, so data writing ability can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure shows a memory configuration of one embodiment, and FIGS. 3 and 4 are timing charts for explaining the operation of one embodiment.
FIG. 5 is a diagram for explaining the image display of FIG. 1, FIGS. 6 to 8 are timing charts for explaining the operation of one embodiment, and FIG. 9 is for explaining conventional data reading. This is a diagram. 11... Frame memory, 12... Microprocessor, 13... OR circuit, 14... Timing generation circuit, 15.16... Address buffer, 17 Address selector, 18... Strobe signal selector . Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A row address is specified in units of rows or columns of m (m≦2^n; n is a positive integer) physical pixels in the row or column direction, and drawing data can be written in page mode. an image memory, a row address generating means for generating address data specifying a row address of the image memory, and a means for generating address data specifying a column address of the image memory, the top n of the address data being m that the bit can take
column address generation means for updating the value of 1 once in each data write cycle according to the page mode; An image memory control device comprising: data writing means for loading data into the image memory according to a page mode and writing drawing data in units of rows or columns in the row or column direction in each data writing cycle.