JPH0369090A - Dual port ram for picture - Google Patents

Abstract

PURPOSE:To suppress the increase of the amount of a hardware and to directly output serial data, which are put in the order of pixels, by providing a parallel / serial converting circuit with sort function and a selector. CONSTITUTION:When data D0-D3 are written, the data D0-D3 are fetched to an input / output buffer 35 by a write enable signal WE. Addresses A0-A7 inputted from an address buffer 30 are decoded by row and column decoders 32 and 33 and memory arrays 34-0 to 34-3 are selected. Then, the data D0-D3 are parallelly written. When serial data ESO are read out, the memory data for the unit of the row of the memory array selected by the decoder 32 are transferred to data registers 36-0 to 36-3 and stored by an output enable signal OE and serial clocks SCK and SOE (serial OE signal). Then, the data are sent to a parallel/serial converting circuit 37 and pixel data are rearranged in the order of the pixels, outputted synchronously with the SCK, selected by a selector 38 and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an image dual port R constituting a frame memory (video memory) of a bitmap display device.
It concerns AM (Random Access Memory).

(Prior Art) Conventionally, a bitmap display device maps characters and figures displayed on a screen such as a CRT display to a frame memory that stores the image displayed on the screen pixel by pixel, and converts it into a bit pattern. This is a device that is expanded and displayed, and an example of its internal configuration is shown in FIG.

FIG. 2 is a block diagram of a conventional bitmap display device. This device is equipped with a CPU (central processing unit) or a processor 1 dedicated to graphics, and the processor 1 includes an interface circuit 2 and a frame memory 3.
, a video signal generation circuit 4, and a CRT display 5 are connected thereto.

In this bitmap display device, a processor 1 creates pixel data (pixel data) to be displayed on a CRT display 5 and stores it in a frame memory 3 via an interface circuit 2.
periodically converts the pixel data from parallel to serial and sends it to the video signal generation circuit 4. Then, the video signal from the video signal generation circuit B4 is sent to the CRT display 5.
The data is sent to the CRT display 5 and displayed on the screen thereof.

Conventionally, frame memory access of processor 1 and CRT
To avoid conflicts with frame memory reading for display and improve frame memory access efficiency of the processor 1, or to omit a parallel/serial conversion circuit that generates serial data to be supplied to the video signal generation circuit 4. A dual port RAM for images has a data input/output port for the processor interface and a serial data output port for the video signal generation circuit 4.
Frame memory is often configured by An example of its configuration is shown in FIG.

FIG. 3 is a block diagram showing a conventional image dual port RAM.

This dual port RAM for images has addresses AO to A.
7, and the address buffer 10 has an address pointer 11 . A row address decoder 12 and a column address decoder 13 are connected. A plurality of memory arrays 14-0 to 14-3 are connected to the row address decoder 12 and the column address decoder 13, and each memory array 14-O to 14-3 has a
An input/output buffer 15 for parallel data DO to D3 is connected. In addition, each memory array 14-0 to 14-
Data registers t6-0 to t6-3 are connected to t6-0 to t6-3, respectively.
A plurality of parallel/serial conversion circuits 17-0 to 17-3 are connected to address pointer 3 and address pointer 1. An output buffer 18 for serial data SOO to SO3 is connected to the parallel/serial conversion circuits 17-O to 17-3. Also, a plurality of control signals RAS.

One read/write control circuit is provided for generating various internal control signals from CAS, WE, DTloE, SCK, and SOE.

In this image dual port RAM, the row address decoder 12 selects the row direction of the memory arrays 14-1 to 4-4, and each of the memory arrays 14-0 to 14-3
The pixel data read out row by row is stored in data registers 16-O to 16-3. Data register 16-
The data in O to 16-3 is sent to the parallel/serial conversion circuit 17 whose address is specified by the address pointer 11.
-0 to 17-3, the data is converted into serial data and then output from the output buffer 18. FIG. 4 shows an example of the configuration of a plain frame memory using this type of dual port RAM for images.

FIG. 4 is a block diagram of a conventional plane frame memory constructed using the image dual-baud RAM shown in FIG. 3.

This frame memory includes four image dual port RAMs 20-0 to 20-3 shown in FIG. It is connected to the interface circuit 2 shown in the figure, and also to the video signal generation circuit 4 shown in FIG. 2 via the parallel/serial conversion circuit 22.

An example of the storage format of pixel data in this frame memory is shown in FIG.

As shown in FIG. 5, when data to be displayed on the CRT display 5 is sent from the interface circuit 2 to the image dual port RAMs 20-0 to 20-3, consecutive pixel data are sent to multiple memory arrays. 14-0
-14-3... are divided and stored. The data read out row by row from each memory array 14-0 to 4-3 is transferred to the parallel/serial conversion circuit 17.
-0~17-3... Serial data SOO~
Converted to SO3... and each output buffer■
8... (see Figure 3). These serial data SOO to SO3... are converted into continuous pixel data by the parallel/serial conversion circuit 22 in FIG.
sent to.

(Problems to be Solved by the Invention) However, the dual port RAM for images with the above configuration
When configuring a plain frame memory using , the following problems occurred.

Conventional dual port RAM for images 20-0 to 20-3
Then, there are internal parallel/serial conversion circuits 17-O to 1.
7-3, in order to generate a video signal, the output from each image dual port RAM 20-0 to 20-3 is required, as shown in FIGS. A parallel/serial conversion circuit 22 is required to serially convert the pixel data, which increases the hardware amount (
The problem was that it was difficult to reduce the circuit size.

Furthermore, in a bitmap display device having a frame memory having such a configuration, the parallel/serial conversion circuits 22 described above are required for the number of planes of the frame memory. There is a problem in that it is difficult to increase the number of colors displayed simultaneously or the degree of gradation, and it has not been possible to obtain a technically satisfactory result.

The present invention solves the problem of the conventional technology, which is that it is difficult to reduce the amount of hardware required for a plain frame memory, and it is difficult to realize multi-color display or multi-gradation display with a small amount of hardware. dual port ram
It provides:

(Means for Solving the Problems) In order to solve the above problems, the present invention temporarily stores pixel data read out row by row from a plurality of memory arrays in a data register, and then converts the stored data into serial data. Parallel/serial conversion that arranges pixel data output from the data register in pixel order and then converts it into serial data in a dual-port image RAM that configures the frame memory of a bitmap display device. The circuit, the serial data input from the outside and the parallel/
A selector is provided for selecting data from among the output serial data of the serial conversion circuit using a selection signal.

(Function) According to the present invention, as described above, the image dual port R
Since we configured AM, the parallel/serial conversion circuit is
After arranging the data successively outputted row by row from a plurality of memory arrays in the order of pixels, it is converted into serial data and given to the selector. The selector selects one from serial data from the parallel/serial conversion circuit and serial data input from the outside based on a selection signal.
The function is to select one and output it to the outside. This results in
It is possible to reduce the amount of hardware when configuring a plain frame memory. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a configuration block diagram of a dual port RAM for images showing an embodiment of the present invention.

This dual port RAM for images has addresses AO to A.
7, and an address pointer 31 for address designation, and a row address decoder 32 and a column address decoder 33 for address decoding are connected to the output side of the address buffer 30. A plurality of memory arrays 34-0 to 34-3 whose memory addresses are selected by the row address decoder 32 and column address decoder 33 are connected,
Furthermore, an input/output buffer 35 for parallel data DO to D3 and a plurality of data registers 36-o to 36-3 are connected to the memory arrays 34-o to 34-3.

Data registers 36-O to 36-3 are memory array 3
It temporarily stores read data from 4-0 to 34-3, and a parallel/serial conversion circuit Z with a sorting function is connected to the output side of the address pointer 31 and the output side of the address pointer 31.
137 is connected. This parallel/serial conversion circuit 37 has a function of combining output data from each data register 36-0 to 36-3, arranging it according to the order of pixels, and converting it into serial data. Its output side is connected to input terminal A of selector 38.

In addition to the input terminal A, the selector 38 has input terminals B, which input external serial data ESIO to ESI2, respectively.
It has control terminals So and SL to which C, D and selection signals 5ELO and 5ELl are respectively input, and an output terminal Y, and the output terminal Y is connected to three output buffers for serial data ESO. This selector 38 receives a selection signal 5E.
L.O.

5ELL, the output serial data of the parallel/serial conversion circuit 37 and external serial data ESIO to E
] 2 and outputs the selected one, and is composed of a multiplexer and the like.

In addition, this dual port RAM for images includes read/
A write control circuit 40 is provided.

This read/write control circuit 40 receives a plurality of control signals (
(row address strobe signal RAS, column address strobe signal CAS, write enable signal WE, data transfer/output enable signal DT10E, serial clock SCK, serial output enable signal SOE, etc.) , is a circuit that outputs various internal control signals at predetermined timings.

Next, the operation shown in FIG. 1 will be explained with reference to FIG. 6.

Note that FIG. 6 is a conceptual diagram of data arrangement in the parallel/serial conversion circuit 37 in FIG. 1.

In FIG. 1, when writing data DO to D3, write enable signal WE causes data DO to D3 to be written.
3 is taken into the human output buffer 35. Addresses AO to A7 input from address buffer 30 are decoded by row address decoder 32 and column address decoder 33, and memories in memory arrays 34-0 to 34-3 are selected. The input/output buffer 3 is added to the selected memory.
Data Do to D3 from No. 5 are written in parallel.

When reading serial data ESO, output enable signal OE, serial clock SCK,
First, memory data (pixel data) in units of rows in the memory arrays 34-O to 34-3 selected by the row address decoder 32 are stored in the data registers 36-0 to 36- by the serial output enable signal SOE and the serial output enable signal SOE.
3 and stored. Data register 36-0~
The pixel data in 36-3 is sent to the parallel/serial conversion circuit 837 at a predetermined timing.

As shown in FIG. 6, the parallel/serial conversion circuit 37 converts pixel data dO to d48. from each data register 36-0 to 36-3. di~d49. d2~d50
．． d3 to d51 are rearranged in pixel order. Thereafter, in synchronization with the serial clock SCK, the parallel/serial conversion circuit 37 indicated by the address pointer 31
The data do, di, d2, . . . therein are serially output and sent to the input terminal A of the selector 38.

The selector 38 selects the serial data inputted to the input terminal A and one of the external serial data ESIO to ESI2 inputted to the input terminals B, C, and D, respectively, to the selection signals on the control terminals SO and Sl. Select according to skin surface based on 5ELO and 5ELL.

The data selected by the selector 38 is output from the output terminal Y, and is output from the output buffer 39 to the outside in the form of serial data ESO in response to the serial output enable signal SOE.

FIG. 7 is a schematic block diagram of a plane frame memory constructed using the image dual port RAM shown in the construction drawing.

This plain frame memory includes four image dual port RAMs 50-0 to 50-3 shown in FIG.
For example, the memory arrays 34-0 to 34-3 in the memory arrays 34-0 to 34-3 in FIG.
Connected to 2. Furthermore, the output of each parallel-serial conversion circuit 37 in the three image dual port RAMs 50-O to 50-2 is transferred to one image dual port R.
It is assigned (connected) to the external input of the parallel/serial conversion circuit 37 in the AM50-3.

FIG. 8 is a selection timing diagram of the serial data output of FIG. 7, and the operation of FIG. 7 will be explained with reference to this diagram.

For example, the data from the interface circuit 2 in FIG. 2 is similar to the conventional plain frame memory shown in FIG.
It is divided and stored in a plurality of memory arrays 34-0 to 34-3. However, when data is serially output, each image dual port RAM 50-
The parallel/serial conversion circuits 37 in 0 to 50-3 put their output data in pixel order. Furthermore, the output of each parallel/serial conversion circuit 37 in the image dual port RAM 50-0 to 50-2 is converted to the parallel/serial converter circuit 37 in the image dual port RAM 50-3.
Since the data is assigned to the external input of the converter circuit 37, if the data to be output to the output buffer (see reference numeral 39 in FIG. 1) is switched using the selector 38 at the timing shown in FIG.
For example, the serial data ESO to be supplied to the video signal generation port #I4 in FIG.
-3 can be output directly.

This embodiment has the following advantages.

(i) The image dual port RAM shown in FIG. 1 is replaced by the conventional parallel/serial conversion circuit 17-0 to
This can be realized by replacing 7-3 with a parallel/serial conversion circuit 37 with a sorting function and a selector 38, so that only a slight increase in the amount of hardware is required compared to the conventional one.

(11) The image dual port RAM shown in FIG. 1 can directly output serial data ESO arranged in pixel order. Therefore, if this is used to configure the plain frame memory shown in FIG. 7, the conventional parallel/serial conversion circuit 22 shown in FIG. 4 can be omitted, and the hardware amount of the entire frame memory can be reduced.

Note that the present invention is not limited to the illustrated embodiment; for example, the internal circuit of the dual port RAM for images shown in FIG.
Various modifications are possible, such as changing the entire plane type frame memory using M to other same-station configurations.

(Effects of the Invention) As explained in detail above, according to the present invention, since a parallel/serial conversion circuit with a sorting function and a selector are provided, pixels can be arranged in the order of pixels while suppressing an increase in the amount of hardware. Serial data can be output directly. Therefore, by constructing, for example, a plain frame memory using this dual port RAM for images, the hardware amount of the entire frame memory can be significantly reduced.

[Brief explanation of drawings]

Figure 1 shows a dual port R for images showing an embodiment of the present invention.
2 is a block diagram of the configuration of a conventional bitmap display device, FIG. 3 is a block diagram of a conventional dual port RAM for images, and FIG. 4 is a block diagram of the dual port RAM for images shown in FIG. 3. 5 is a diagram showing an example of the storage format of pixel data in FIG. 4, FIG. 6 is a conceptual diagram of data rearrangement in FIG. 1, and FIG. FIG. 1 is a block diagram of the configuration of a plain frame memory using FIG. 1, and FIG. 8 is a selection timing diagram of serial data output in FIG. 31...Address pointer, 32...
Row address decoder, 33... Column address decoder, 34-a to 34-3... Memory array,
36-0 to 36-3... Data register, 37
...Parallel/serial conversion circuit, 38...
... Selector, 50-○ to 50-3 ... Dual port RAM for images. Dual photo RAM for images according to the embodiment of the present invention. Figure 5

Claims (1)

[Claims] A frame memory of a bitmap display device, which has a function of temporarily storing pixel data read out row by row from a plurality of memory arrays in a data register, and then converting the stored data into serial data and outputting the serial data. In the image dual port RAM that constitutes the image data register, there is provided a parallel/serial conversion circuit that arranges the pixel data output from the data register in pixel order and then converts it into serial data; A dual port RAM for images, characterized in that it is provided with a selector that selects one from among the serial data output from the serial conversion circuit using a selection signal.