JPH0844617A - Image processor - Google Patents

Abstract

PURPOSE:To display images while switching a multilevel image and a binary image by using one image memory by mixedly designating the storage addresses of the digital image data of the multilevel image and/or the binary image to one image memory. CONSTITUTION:Memory cells 6A-6D secure a memory area while dividing it into two pictures for gradation image areas 7A and 7B and one picture for a binary image area 8. When dealing with a monochromatic video signal, the amount of data for one scanning line is set at 512 picture elements, the number of valid scanning lines for the video signal is set at 480, and the data of 512X480 picture elements are used as the image data of one frame. In this case, even when two pictures for 512X480X8 bits are secured, remaining data for 512X512X1 bits can be used for the binary image memory area 8, and the memory cells 6A-6D are effectively utilized. Thus, the memory areas of the gradation image areas 7A and 7B and the binary image area 8 are secured in one frame buffer, and both the images can be independently processed.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIG. 8) Problem to be Solved by the Invention Means for Solving the Problem (FIGS. 1 to 6) Action (FIG. 7) Example (FIGS. 1 to 7) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and in particular, it can be applied to an image processing apparatus capable of displaying digital image data of both multi-valued images and binary images.

[0003]

2. Description of the Related Art Conventionally, in an image processing apparatus, an analog video signal is analog-digital converted and temporarily stored in a frame buffer, the stored data is digital-signal processed, and the result is digital-analog converted to a monitor. The output is displayed. DRAM (d
dynamic random access memory) etc. is used to store image data for each frame and at a predetermined video rate 30
It is designed to read and write (read / write) at high speed in [frame / sec].

When the frame buffer is used for both multi-value (grayscale) image display and binary (bitmap) image display, the frame buffer is formed as an image memory structure dedicated to a grayscale image as a first method, for example. Then, as shown in FIG. 8, by rewriting the contents of the table in the look-up table installed before the input of the digital analog converter in the case of the grayscale image and in the case of the binary image,
The grayscale image display and the binary image display are switched and displayed.

As a second method, an image memory dedicated to displaying a grayscale image and an image memory dedicated to displaying a binary image are prepared so that the output of image display can be switched according to the purpose. Here, for example, the gradation is 8 bits 256
Expressed in terms of gradation, a binary image in which one pixel is one bit can be configured with 1/8 the capacity of the grayscale image per surface. Alternatively, one image memory is used as the grayscale image mode and the binary image mode.

[0006]

By the way, according to the first method, when the image memory is set to the binary image display, in the case of 8 bit gradation, one gray image having a capacity of eight screens of the binary image is displayed. The minute image memory area must be dedicated to the binary image. Therefore, in the binary image, the image memory area corresponding to the capacity of eight screens can be used only for one screen of the binary image, and there is a problem that the use efficiency of the image memory is reduced.

In the second method, since the image memory other than the grayscale image memory is provided exclusively for the binary image, the number of image memories (DRAM) used increases. When the mode is selectively switched to grayscale image display or binary image display, the memory usage efficiency is optimized, but both grayscale and binary images are stored in either grayscale or binary only. There was a problem that it could not be displayed without changing the configuration.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose an image processing apparatus capable of displaying a switched image by a multivalued image or a binary image using one image memory.

[0009]

In order to solve such a problem, in the present invention, digital image data of a multivalued image and / or a binary image is stored, and the digital image data is subjected to image processing to obtain a multivalued image or a binary image. In an image processing device (1) for switching between images and displaying images by an image display means,
An image memory (6A to 6) for storing digital image data
D) and an image memory means (3) having an input / output buffer memory (10A to 10D) for digital image data, and a multi-valued image and / or 2 by designating a row address and a column address for the digital image data.
Address generating means for generating a storage address of the value image (2
0) and output image switching means (30) for switching the digital image data from the image memory means to a multi-valued image or a binary image and reading it.

[0010]

The digital image data of the multi-valued image or the binary image is switched by specifying the storage addresses of the digital image data of the multi-valued image and / or the binary image in a single image memory (6A to 6D). It is possible to display an image as a result and efficiently use the storage capacity of the image memory.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes an image processing apparatus as a whole, in which a digital video signal sent from a host processor 2 is temporarily stored in a frame buffer 3 and then
Random read / write is performed and digital signal processing is performed. The digital video signal subjected to the digital signal processing is sequentially and continuously read, digital-analog converted by the digital analog conversion circuit 4, and sent to the display 5 as a monochrome composite video signal (hereinafter referred to as a video signal) for image display. .

As shown in FIG. 2, each of the memory cells 6A to 6D forming the frame buffer 3 has 1 [Mbit.
It is a dual port DRAM composed of four DRAMs having a storage capacity of [s], and has a total storage capacity of 4 [Mbits]. These memory cells 6A to 6D have 51 memory areas.
2 × 480 × 8 [bits] grayscale image areas 7A and 7B 2
Area and 1 of 512 × 512 × 1 [bit] binary image area 8
It is secured by dividing it into areas and areas.

When handling a monochrome video signal, the scanning line 1
The data amount for lines is 512 pixels, and the number of effective scanning lines of the video signal is set to 480 in consideration of the distortion of the data in the peripheral portion deviated from the center of the image input device (not shown).
Data of × 480 pixels is used as one frame of image data. At this time, the grayscale image 512 x 480 x 8 [bits] is 2
Even if the surface area is secured, the remaining 512 × 512 × 1 [bit] data can be used as the binary image memory area, and the memory cells 6A to 6D are effectively used. Like this one
Grayscale image areas 7A and 7B in one frame buffer 3
It is possible to secure the memory area of the binary image area 8 and process both images independently.

As shown in FIG. 3, the frame buffer 3 of the dual port DRAM capable of simultaneously supporting the image display on the display 5 and the access from the two circuits for the data processing is provided in the serial register buffer register. Thus, four serial memories 10A to 10D (SAM) each having a storage capacity of 4 × 512 [bits] are built in corresponding to the respective memory cells 6A to 6D. The data transferred from the memory cells 6A to 6D of the frame buffer 3 to the SAMs 10A to 10D via the transfer gate 11 are mutually transferred with the memory cells 6A to 6D in units of any one row. This SAM 10A-10
D can operate independently of the ports on the side of the memory cells 6A to 6D except when transferring data. Therefore, by using this as a buffer for serial access for display, the memory cells 6A to 6D side can perform normal DR.
It can operate in the same way as AM.

RAS (row address strobe) addresses of the memory cells 6A-6D are designated by the row decoder 13 via the address input buffer 12 for the memory cells 6A-6D. Then, the column decoder 14 specifies a CAS (column address strobe) address. Here, when an image is displayed using the image data of the memory cells 6A to 6D, the image data designated by the RAS address and the CAS address is counted by the address counter 15 by the serial clock (SC) of the external input. , After serial-to-serial conversion by the serial data selector 16, receives the serial-out enable signal (SOE) and outputs the serial-out S of the serial input / output buffer 17.
It is output from O1 to SO4.

In the frame buffer 3, the address generation circuit 20 shown in FIG. 4 responds to the video signals sent from the scanning lines (A0 to A8) with RAS in accordance with the grayscale image and the binary image, respectively. An address and a CAS address are designated. That is, in the case of a gray image in which one pixel has 8 bits, the address corresponding to the scanning lines A0 to A8 is directly designated as the RAS address.
As shown in FIG. 5, memory cells 6A to 6D to SAM1
The image data once stored in 0A and 10B is SAM1.
4 [bits] each are read out from 0A and 10B, 512 columns of 8 [bits] pixel data are addressed and read out, and are sent as one line of image data every time the RAS address is incremented. It

Further, as shown in FIG. 6, in the case of a binary image, the image data once stored in the memory cells 6A to 6D in the SAMs 10A to 10D are read out by 4 [bits] for 16 columns. That is, by designating the scanning line addresses A0 to A3 for the CAS addresses CA5 to CA8, 16 [bits are set for one column of the memory cells 6A to 6D.
s] pixel data is addressed. CA from now on
One line of 512 [bits] image data is formed by 32 columns of S addresses, and 16 lines of this image data are designated every time the RAS address is incremented. As a result, the CAS address designated by the address generation circuit 20 is always 0 in the case of a grayscale image, but is accessed in multiples in the case of a binary image.

The RAS of the video signal is synchronized with the scanning line by the 8-bit binary counter 21 by the horizontal synchronizing signal H _sync . That is, the addressing of the image data is started by an initial value of 8 bits which is set in the counter in synchronization with the LOAD signal S ₁ for which the data movement (LOAD) condition is set. For a video signal of a binary image, a scan line address A is set as a data movement holding (HOLD) condition.
1, A2, A3, one among any of A4 holds data detent the Yotsute counter HOLD signal S _h is set to hold the data movement time is 1.

The RAS of the 8-bit video signal synchronized by the 8-bit binary counter 21 is designated by an address of 9 [bits] including RA0 for setting an even or odd field of interlaced scanning. RAS and CA
S is an address selector 22, which is switched by a RAS / CAS switching signal S1 and is set to R of the memory cells 6A to 6D.
An AS address and a CAS address are designated.

When the grayscale image and the binary image stored in the frame buffer 3 are output, the image data is switched by the output switching circuit 30 shown in FIG. 7 and output to the display 5. When the image data of the frame buffer 3 is transmitted from the serial input / output buffer 17, the 8-bit bus line is switched between the grayscale image and the binary image via the transceiver 31 and transmitted. In the case of a grayscale image, it is output to the display 5 via the digital analog conversion circuit 4 via the bus line 32, and in the case of a binary pixel, it is sent to the shift registers 34A and 34B via the bus lines 33A and 33B and then to the digital. Analog conversion circuit 4
Is output to the display 5 via.

The transceiver 31 has a DIR (directio)
n) According to the read / write signal S2 for the memory cells 6A to 6D input to the terminal 35, the memory cells 6A to 6D
The writing and reading operations for 6D are switched.
Further, a selection signal S3 for the grayscale image regions 7A and 7B and a selection signal S4 for the grayscale image regions 7A and 7B and the binary image region 8 are sent to the gate terminal 36 via the NOT circuit 37 and the NAND circuit 38. The image display switching signal S5 based on the output result selects the image display memory area.

When outputting a binary image, the grayscale and binary selection signal S5 becomes high level H, and the AND circuit 39
Dot clock CLK via shift register 34A
And 34B clock (CLK) terminals 40A and 40B
Send to. Further, a pulse PLS which is output once for 16 pulses of the dot clock CLK is sent from the counter 41 to the LOAD terminals 42A and 42B. Further, in the data display period, the horizontal synchronizing signal H _{sync is applied} to the AND circuit 4
3 to CLR terminals 44A and 44B.

The shift registers 34A and 34B are connected by the SO (serial out) terminal 45A of the shift register 34A and the SI (serial in) terminal 46B of the shift register 34B, and are connected to the SO terminal 45B of the shift register 34B from the SO terminal 45B.
The value image data is sent to the digital analog converter 4 by 1 [bit] at a time. SI terminal 46 of shift register 34A
A is grounded to ground.

In the above structure, the memory cells 6A to 6A
The RAS address and the CAS address of the image data stored in D are designated by the address generation circuit 20. Here, when the grayscale image data is addressed to the memory cells 6A to 6D, the storage addresses of the grayscale image data are RAS addresses (RA1, RA2, RA3, RA4, RA5, R).
(A6, RA7, RA8) as the initial value (0, 0, 0,
0, 0, 0, 0, 0) is designated. Next, 8 [bits] pixel data is counted by the 8-bit binary counter 21, and one line 51 synchronized with the horizontal synchronizing signal H _sync
2 The RAS address of the image data of each bit is the scan line A0.
~ Grayscale image area 7A or 7B corresponding to address A8
Specified in. At this time, each line always starts from the CAS address 0.

Further, the binary image data is transferred to the memory cells 6A to 6A.
When addressing D, the RAS address (RA
1, RA2, RA3, RA4, RA5, RA6, RA
(7, RA8) as the initial value (0, 0, 0, 0, 1,
1, 1, 1) is designated. As a result, the HOLD condition for binary image addressing is released, and the image data is addressed to the binary image area 8. That is, the RAS address of the binary image area is designated next to the RAS address at which the grayscale image area ends. At this time, the CAS address (CA1, CA2, CA3, CA4, CA5, CA
6, CA7, CA8) is (0, 0, 0, 0, A0, A
1, A2, A3).

Here, the CAS address is shifted by 1 every time 16 bits of pixel data are written by RA4 counted every 16 bits. Further, the scanning line addresses A0 to A3 set to the CAS address count the pixel data of 16 bits per column for 32 columns.
16 lines of pixel data of a binary image of 512 [bits] per line are addressed to the binary image area 8 for each RAS address.

Thus, in one memory cell 6A to 6D, the binary image area 8 can be generated together with the grayscale image areas 7A and 7B. At this time, when the RAS address is generated, the LOAD signals S ₁ and LOAD of the counter
Initial value 8 set in the counter in synchronization with D signal S _l
HOLD signal S for holding the bit and counter
_h is divided into a grayscale image and a binary image, and the horizontal synchronization signal H
8-bit binary counter 21 with _sync as clock
By generating an address using, it is possible to share many parts of the circuit. Further, as for the CAS address, as shown in FIG. 4, by inputting to the dual port DRAM separately for the grayscale image and the binary image,
Similar to the case of RAS address generation, the circuit can be shared.

In this way, the image data of the grayscale image and the binary image stored in the memory cells 6A to 6D is read out by the control of the host processor 2. That is, in FIG. 7, when the read / write signal S2 of high level H is first input to the DIR terminal 35 of the transceiver 31, the reading of image data is selected. Here, the grayscale image area 7A
When reading out the image data of, the image switching signal S5 of the high level H is sent to the gate terminal 36 by the selection signal S3 of the gray level image region of the low level L and the selection signal S4 of the gray level of the low level L and the binary image. To be done. As a result, the image data of the grayscale image area 7A is sent to the digital analog conversion circuit 4 by the bus line 32 in synchronization with the dot clock CLK, and displayed as a grayscale image on the display 5.

Next, when the image data of the grayscale image area 7B is read out, the low level L image is selected by the high level H grayscale image area selection signal S3 and the low level L grayscale and binary image selection signal S4. The switching signal S5 is sent to the gate terminal 36. As a result, the image data of the grayscale image area 7B is sent to the digital analog conversion circuit 4 via the bus line 32, and is displayed on the display 5 as a grayscale image.

When the image data of the binary image is read out, the high-level H image switching signal is selected by the high-level H grayscale image area selection signal S3 and the high-level H grayscale and binary image selection signal S4. S5 is sent to the gate terminal 36. At this time, the selection signal S4 is simultaneously changed to the AND circuit 3
9 and the AND circuit 43, and a logical product is obtained between the dot clock CLK and the horizontal synchronizing signal H _sync .

As a result, the output from the AND circuit 39 is the clock terminals 40A and 40B as the clock CLK signal.
Sent to The output from the AND circuit 43 is sent to the inverting input clear terminals 44A and 44B as a signal for setting the data display period consisting of the horizontal synchronizing signal _Hsync . At this time, an output of 1 pulse for 16 pulses of the clock CLK is inverted input from the counter 41 to L level.
It is sent to the OAD terminals 42A and 42B.

As a result, the serial memories 10A to 10D
16 [bits] worth of data for each data access from the shift register 3 via the bus lines 33A and 33B.
4A and 34B. The shift registers 34A and 34B temporarily store this 16 [bits] worth of data, then perform parallel-to-serial conversion as image data of a binary image, and sequentially send the image data 1 [bit] at a time to the digital-analog converter 4. .

According to the above structure, the memory cells 6A to 6D of the dual port DRAM of 1 [Mbits] are 512 × 48.
0 × 8 [bits] gray image areas 7A and 7B
By dividing the area into one area of the binary image area 8 of 512 × 512 × 1 [bit] and storing the grayscale image and the binary image in a mixed manner in one image memory, the image is stored in one image memory. Therefore, the grayscale image and the binary image can be switched for image output, and the storage area of the 4 [Mbits] DRAM can be efficiently used without waste.

In the above embodiment, the case where a monochrome video signal is used as the video signal stored in the image memory has been described, but the present invention is not limited to this.
Color video signals may be stored. Further, in the above-mentioned embodiment, the case where the grayscale image and the binary image are switched and displayed by the image processing apparatus using the composite video signal has been described, but the present invention is not limited to this, and is widely applied to general graphic terminals. It can be used for. For example, when it is used for an X terminal which is recently used as a UNIX computer terminal, it is possible to construct a binary bit map screen independent of the gray screen or the color screen.

In the above embodiment, the case where the dual port DRAM is used as the frame buffer has been described, but the present invention is not limited to this, and a multi port memory such as a triple port may be used.

[0037]

As described above, according to the present invention, by storing digital image data of a multivalued image and / or a binary image mixedly in one image memory, the multivalued image or the binary image data can be stored.
It is possible to realize an image processing apparatus capable of switching the value images and displaying the images and efficiently using the storage capacity of the image memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a memory configuration of a frame buffer.

FIG. 3 is a block diagram showing a configuration of a dual port frame buffer.

FIG. 4 is a block diagram showing address designation by an address generation circuit.

FIG. 5 is a block diagram showing processing by a register for displaying a grayscale image.

FIG. 6 is a block diagram showing processing by a register for displaying a binary image.

FIG. 7 is a block diagram showing a data output switching circuit.

FIG. 8 is a graph showing the contents of a lookup table for a grayscale image and a binary image.

[Explanation of Codes] 1 ... Image processing device, 2 ... Host processor, 3 ...
Frame buffer, 4 digital analog converter, 5 ...
Display, 6A, 6B, 6C, 6D ... Memory cell, 7A, 7B ... Gray image area, 8 ... Binary image area, 10A, 10B, 10C, 10D ... SAM, 11
...... Transfer gate, 12 ...... Address input buffer, 13 ...... Row decoder, 14 ...... Column decoder,
15 ... Address counter, 16 ... Serial data selector, 17 ... Serial input / output buffer, 20 ... Address generation circuit, 21 ... 8 bit binary counter,
22 ... Address selector, 30 ... Data output switching circuit, 31 ... Transceiver, 32, 33A, 33B ...
Bus line, 34A, 34B ... Shift register, 35
...... DIR terminal, 36 ... Gate terminal, 37 ... NOT
Circuit, 38 ... NAND circuit, 39, 43 ... AND circuit, 40A, 40B ... clock terminal, 41 ... counter, 42A, 42B ... LOAD terminal, 44A, 44B
... CLR terminal, 45A, 45B ... SO terminal, 46
A, 46B ... SI terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G06F 15/64 450 G

Claims (2)

[Claims] 1. Digital image data of a multivalued image and / or a binary image is stored, the digital image data is subjected to image processing, and the multivalued image or the binary image is switched to display an image by an image display means. In the image processing apparatus, an image memory means having an image memory for storing the digital image data and an input / output buffer memory for the digital image data; and a row address and a column address for the digital image data are designated to obtain Address generating means for generating a storage address of the multi-valued image and / or the binary image, and output image switching means for switching the digital image data from the image memory means by the multi-valued image or the binary image and reading the digital image data. An image processing device comprising: 2. The image memory has a storage capacity of 1 [M
bits] of the first, second, third, and fourth DRAMs, and the address generation circuit causes the row address to correspond to the scanning line 480 [bits] of the image display means and the column. The address is set to 512 [bi
ts], the unit digital image data for the first and second DRAMs and the third and fourth DRAMs have a density value of 8 bits for two screens of the multi-valued image. A storage address is designated, and the storage address of the digital image data of the binary image of 16 scanning lines is set for each row address using the next row of the storage address of the multi-valued image as a start row address. Second,
2. The image processing apparatus according to claim 1, wherein the address is specified as a 32 row address.times.512 column address of the third and fourth DRAMs.