TWI250531B - Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation - Google Patents

Abstract

Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

Description

</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> And generally referred to herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit memory device and a method of operating the same, and more particularly to a circuit and method for testing an integrated circuit device. [Prior Art] Integrated circuit memory devices are widely used in many commercial and consumer applications. A widely used integrated circuit memory device is a dynamic random access memory (DRAM). At present, a synchronous (10) 10 (10) 趟 趟 device has been designed which is capable of reading and writing data in synchronization with the rising or falling edge of the clock signal. In addition, double data rate (DDR) SDRAM devices have been designed, which can read and/or write data in response to both rising and falling edges of the clock signal, thereby being higher than conventional The frequency of SDRAM (also known as single data rate (sdr) sdram) operates. Those skilled in the art will appreciate that the term "data rate" as used herein means the number of bits transmitted by a memory device to an external input/output terminal or transmitted from an external input/output terminal in one clock cycle. 0 1 is the same as the conventional SDR SDRAM and the conventional DDR SDRAM. Both SDRAMs include a row address strobe (BL) and a row address strobe (CAS) delay (cl) of size 2. Therefore, as shown in FIG. 1, for BL=4 and CL two m々sdram, the data Q0, Q1, Q2 and Q3 of 4 bits are read in response to a read command R of 93587.doc 1250531, wherein Each bit of data Q0-Q3 is output in response to the rising edge of a clock CLK. Similarly, in response to a write command W and in response to the rising edge of the clock CLK, the data of 4 bits is sequentially input. In contrast, as shown in FIG. 1, for a DDR SDRAM, the stored data Q0-Q3 are output from the memory device in response to both the rising edge and the falling edge of a data strobe signal (DQS). The data strobe signal itself is generated by the clock signal CLK. Similarly, data D0-D3 is written into the memory device in response to a write command and in response to both the rising and falling edges of DQS, thereby achieving a double data rate compared to SDR SDRAM. The design and operation of SDRAM devices, including SDR SDRAM devices and DDR SDRAM devices, are well known to those skilled in the art and need not be described in detail herein. Higher data rates make it difficult for us to test high frequency memory devices such as DDR SDRAM. It may also be particularly difficult to test lower frequency test equipment such as test equipment designed to test SDR SDRAM to high frequency memory devices such as DDR SDRAM. For example, U.S. Patent No. 5,933,379, to the assignee of the present application, to the assignee of the present application, provides a method and circuit for testing semiconductor memory devices operating at high frequencies (Method and Circuit for Testing a Semiconductor Memory Device Operating at High Frequency)" The name of a Park et al. As described in the invention summary of Park et al., the patent discloses a circuit for testing a semiconductor memory device, the circuit comprising: a delay controller for controlling the delay of an external clock signal; an internal row address generator , which is used to generate a row address signal in a memory device; and a 93587.doc 1250531 nuclear scratchpad for a _ ^ king chess nickname. The circuit for testing a semiconductor 5 memory device also includes a _ address decoder for decoding an output address signal of a row address generator; a memory cell Buying or writing data; an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the late technology system - the feed input buffer; and a data output buffer Device. Further, a frequency multiplier is used to generate an internal clock signal which is "η" times the frequency of the frequency component clock signal of the internal clock signal. By providing the above improvements, the high frequency memory device can be tested using conventional test equipment. U.S. Patent No. 6,163,491 to Iwotomo et al., "Synchr〇n〇us Semiconductor Memory Device Which Can Be Inspected Even With Low Speed Tester" - Iwotomo The name of the invention. As described in the abstract of the invention by Iwotomo et al., the patent discloses a synchronous semiconductor memory device comprising a prefetching selector for receiving pre-fetch selectors respectively corresponding to even and odd addresses. The first and second memory cells read the first and second data for rotation to a data input/output terminal. The prefetch selector sequentially outputs the first data and the second data to the data input/output terminal in one clock cycle during normal operation, and determines whether the first data and the second data match in the test mode, and The determination result is output to the data input/output terminal in one clock cycle. Finally, U.S. Patent 6,212,113 to Mader describes a "semiconductor memory device input circuit (Semiconductor Memory Device Input 93587.doc 1250531).

Circuit)" The name of a Mader invention. As described in the abstract of Mader, the patent discloses a double data rate (DDR) memory device that can be constructed to be tested on a conventional memory tester. The DDR memory can include: a DDR input circuit, a single data rate input circuit, a word line control circuit, a bit line control circuit, and a memory cell array. A normal write operation can be implemented using a DDR input circuit. Test write operations can be performed using the SDR input circuit. This configuration allows the DDR memory device to be tested on a conventional SDR memory tester. However, it may still be difficult to test high frequency memory devices such as DDR SDRAM because the high frequency memory device may have a small effective data window tolerance that may be caused by process variations in the device fabrication line. Therefore, even if high-frequency test equipment such as DDR SDRAM can be used to test high-frequency devices such as multiple DDR SDRAMs that may be difficult to actually test in parallel, DDR SDRAM is still possible. SUMMARY OF THE INVENTION An integrated circuit memory device,

A clock signal having a rising edge and a falling edge. Some embodiments of the present invention provide an integrated circuit memory device comprising: flattening a mountain at a first data rate,

93587.doc l25〇53l: The first data rate is generated according to the rising edge and the falling edge of the clock signal, and the second data rate is generated only by the rising edge or the falling edge. In other embodiments, the = is configured to output the plurality of data bits in parallel via the corresponding plurality of first data lines: the output circuit is configured to pass through the normal operation mode Corresponding plural second data lines output the plurality of data bit serials to the external end at the beacon rate, and in the measured operation mode, the corresponding plurality of second data = the low The plurality of billet bits 7L are serially output to the external terminal at the second material rate of the first data rate. Correspondingly, in the test mode of operation, a certain (4) embodiment of the present invention can accommodate (4) the memory cell array operating at a data rate, and (4) allowing the wheel circuit to have a second data rate lower than the first data rate. Output the data to the external terminal. As such, the data window can be expanded to test one (for example) DDR sdram using SDR SDRAM test equipment, and/or multiple sdr sdrams can be tested in parallel on SDR SDRAM test equipment. Some implementations of the present invention are installed. In an example, the output circuit is configured to: in the test mode of operation, copy a first portion of the plurality of data bits output in parallel by the memory cell array to be lower than the second data rate Data rate outputting the first portion of the plurality of data bits to the external terminal in tandem, and copying the _parts of the plurality of bin bits outputted in parallel by the memory cell array to be lower than the first The second data rate of a data rate rotates the second partial string 93587.doc -10 - 1250531 of the plurality of data bits to the external terminal. More specifically, a certain memory cell array is configured to output the plurality of B 平行 in parallel via a corresponding plurality of first data: a first lean rate, including: - a multiplexer, the structure thereof The read buffer for multiplexing the data to the corresponding plurality of second data lines; the read buffer is configured to output the second data lines to the external terminal. Bayco Serial Out + In some such embodiments, the multiplexer is configured to: in a squat, mate a corresponding first stomach green to a corresponding second data line, and In the first-sub mode of the test operation mode, the corresponding even-thin-thin material (four) is combined to the corresponding even second data line and the corresponding second data line of her neighbor, and in the second sub-mode of the test operation material The odd first data line should be lightly coupled to the corresponding odd second data line and the corresponding adjacent even second data line. The library is intended to be tightly understood. The terms "even" and "odd" are used herein to refer to alternate data lines, and are not related to the greedy line number representation used to indicate the data line. In some embodiments, the multiplexer includes: a first switch configured to couple a respective even-numbered first-beat line to a corresponding even-numbered second data line in the first sub-mode, a second switch 'constructed to combine a corresponding odd-numbered data line to a corresponding odd second data line in the second sub-mode; and first equalizing power: (4) for In the first and second sub-modes, a corresponding odd-numbered brother-two gongs are spliced to the corresponding second data line of the corresponding field. A mode register set may also be provided, the mode register set may be responsive to a plurality of command signals and configured to generate the first and second test mode signals to the 93587.doc -11 - 1250531 multiplexer They are placed in the first and third sub-modes of the test operation mode. In other embodiments, the multiplexer is configured to: 'couple the corresponding first-data line to a corresponding second data line in the normal mode of operation: in the first mode of the test mode of operation, a corresponding first data line is coupled to a corresponding second data line; and in the second sub-mode of the test mode of operation, 'corresponding odd and even number-data lines are tapped to the corresponding even and odd numbers Second data line. In these embodiments, the output buffer is responsive to a normal operating mode: a first internal clock signal, the first internal clock signal is generated in response to a rising edge of the clock signal; and a second internal clock signal The second internal clock signal is generated in response to a falling edge of the clock signal and may be only one of the first internal clock signal or the second internal clock signal in the first and second submodes of the test mode of operation . It should be understood that the terms "up" and "down" used in this article are used to indicate different edges in the day-to-day face number, which are interchangeable. Moreover, in the embodiments, the multiplexer can include: a _ switch configured to couple the _ corresponding first data line to a corresponding one in the normal mode and in the first sub mode And a second switch configured to couple and couple the corresponding odd and even first data lines to the corresponding even and odd second data lines in the second sub mode. At the same time, in some implementations, the output buffer includes: a corresponding plurality of registers, ', the corresponding temporary storage is configured to store the data from the corresponding first data line' And a latch associated with a respective pair of adjacent registers, a corresponding latch configured to latch data from a first adjacent register in response to the first internal clock signal and The second internal time 93587.doc -12- 1250531 clock signal to latch from a second adjacent device may also include - parallel to the poor column. The output buffer ^ ^ , 益 , 忒 parallel to serial converter in the hanging operation (four) towel can be (4) - 5 within the tiger = the first and second operating sub-mode only due to the first and i an internal clock signal one. In another such method of the present invention, the output circuit is in a normal operation mode: upper =: a first internal clock signal, responsive to the clock signal ... r; and a second internal clock The signal, which is generated in response to the == falling edge at that time, and in the test mode of operation, the output: number. Two-body: the internal clock signal and the second internal clock are passed through the corresponding plurality of strips:: two in the memory cell array configuration * the plurality of data bits W circuit includes - round = 35 in the apple It is expected to be the terminal of the material department. In a two-example embodiment, the rim σσ should be: - the first internal clock rn in the mode can be due to =; and the second internal clock signal, which responds to a falling, 彖 彖 and is in the test A mode of operation mode should be the first internal clock 俨', only test the operation mode H sub-mode, then ❹(4)--in=^^^^^^^^^^^^^^^^^^^^ The buffer includes: a corresponding plurality of temporary storages 2 = = a temporary register configured to store a read from a corresponding first data line and a latch associated with the corresponding - pair of adjacent registers, A 93587.doc -13- 1250531 corresponding latch is configured to latch the data from the -1st adjacent register in response to the first internal clock signal and to latch from the first internal clock signal The second adjacent register is the one that is in the middle of the register. In a normal mode of operation, the latch can be waited for the latch, the first and the second clock. During the mode only due to [and the second internal material, the signal - in the second operational submode The other is only due to the other of the first and first internal clock signals. According to still further embodiments of the present invention, the output circuit is on the normal operating mode i = the first internal clock signal, which is responsive to The clock signal = edge; and a second internal clock signal, which is generated in response to the falling edge of the tiger at that time, and in the in-service mode, the output electrical-internal clock signal is divided by the first parent: it is generated from The first knives - an internal clock signal, which is generated from the internal clock signal of the second ridge. More specifically, in some embodiments, the output buffer can be responsive in a normal mode of operation: - a first internal clock The first internal clock signal generates a 'and-second internal clock signal in response to the rising edge of the clock signal, and the second internal clock is generated as a falling edge of the tiger' and can be tested in the operating mode V; n part of the clock signal and the clock signal. In some embodiments, the younger brother... _ ^ knife with &lt; brother one internal time double / ±: = points: the second internal clock signal of the member of the frequency is the first - Internal::, 'Li L唬 and 5 Haidi - Internal Time Half of the clock signal. In addition, a --divide circuit can also be provided, which is configured to use the rising edge of the plastic clock signal and the test mode selection signal to generate the internal clock signal of the second 93587.doc 1250531. A second frequency dividing circuit can be provided for generating a first two-part clock signal in response to a falling edge of the clock signal and a test mode select signal. In some embodiments, the first frequency dividing circuit includes a first The first frequency dividing circuit includes: a second frequency divider, the first frequency divider can be responsive to the falling of the clock signal, and the frequency divider can be responsive to the rising edge of the clock signal and the test mode signal. And a test mode signal; and a delay element responsive to the second frequency divider. Other embodiments of the present invention provide an operation having a configuration for outputting a plurality of data bits in parallel at a data rate A method of integrating a memory device of a memory cell array. In accordance with some embodiments of the present invention, the plurality of data bits are serviced from the memory cell array to the foreign material terminal at the first data rate in the normal mode of operation. In the test mode of operation, the plurality of data bits are output from the memory cell array to the external terminal at a second data rate lower than the first data rate. In the methods of the various embodiments of the present invention, embodiments similar to those of the above embodiments may also be provided. [Embodiment] Hereinafter, the present invention will be described as a plurality of different shapes, and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided solely to provide a thorough and complete disclosure of the present invention. In the drawings, the size and relative dimensions of the elements may be exaggerated for clarity. Moreover, each of the embodiments described and illustrated herein also includes embodiments of complementary conductivity types. Throughout the text, the same number refers to the same component 93587.doc 1250531. Figure 2 is a block diagram of an integrated memory device and method of operation in accordance with various embodiments of the present invention. As shown in Fig. 2, an integrated circuit memory device 2 includes a memory cell array 2H configured to output a plurality of data bits in parallel at a first feed rate DR1. The design of the memory cell array 2&quot; has been well known to those skilled in the art and need not be repeated here. Still referring to Fig. 2, an output circuit 213 is configured to: in the normal mode of operation, the data rate DR1 outputs the plurality of data bits in series. In the test mode of operation, the plurality of data bit strings 歹J are output to the external terminal 217 at a second data rate DR2 lower than the first material rate. In other words, as shown in FIG. 2, dr2 is less than (10). It should be understood by those skilled in the art that in some embodiments of the present invention, a plurality of memory cell arrays 1 may be provided in a single integrated circuit memory device. The output circuit 2 i 3 and/or a plurality of external terminals 2丨7. In addition, the function and circuit of the output packet 213 and the circuit and/or the output circuit can be copied for each s MSC array 211 and/or external terminal 211 and the circuit can be v σ 卩The ground is shared by a plurality of memory cell arrays 211 and/or external terminals 217. Still in Fig. 2, in some embodiments of the present invention, the memory cell array 2i is configured to, and, by the corresponding plurality of first data lines 2 12, output a plurality of data in parallel at a first data rate. Bit. Since &amp;, for each bit-bit of the parallel output from the memory cell array, there is a - data line 2 i 2 . In addition, in a certain κ embodiment, the wheel circuit 213 is configured to use the chrome flute corresponding to the wheel circuit 2 Π _ in the normal operation mode 93587.doc 1250531. The second lean line 214 has a plurality of data bits at the first Becco rate at the test operation, and the rounding to the outer end 2", and the data line 214", the corresponding plurality of strips in the output circuit The second shell line 214 outputs a number of shell elements in series below the first data ^ by Zhao Yuci, the second poor material rate DR2 of the Fengfeng R1, to the death 1, 1, and 217. Thus, for example, four first data lines 212 and four second data lines 214 can be used. ^ ^ ^ ^ The integrated circuit memory device and the operation/block diagram. In general, moxibustion male ^, Pi Tian Di ·, see Figure 3, an output circuit 31 3

Xe is used in the test mode of operation (4) P memory cell array 211 parallel input: number: poor: the first part of the bit, so that the number is lower than the first capital; The first part of the data bits == external terminal 217. The output circuit 313 is also configured to: in the measurement &quot;H&apos; hard one of the plurality of material bits output in parallel by the memory cell array 211 - Qiu A to ^ 灵双贝弟一. The second portion of the plurality of data bits is serialized to the output terminal at a second data rate lower than the first data rate. More specifically, the tongue &apos; is shown in Fig. 3. The memory cell array 211 is configured to output a plurality of lean bits in parallel at a first data rate by a corresponding plurality of first data lines 212. In Figure 3, the first data line 212 is labeled RDI〇_〇-RDIO. However, in other embodiments, fewer or more than one of the first data lines 212 may be used. In addition, as shown in FIG. 3, the output circuit 313 includes -multi_3131. The multi-guard 31 is configured to multiplex the read data on the first data line 212 to the corresponding plurality of second data lines. 2 i 4 (labeled D〇-〇_D〇-3 in Figure 3). The output circuit 3 i 3 also includes 93587.doc 1250531 - an output buffer H313b configured to output the resource_column on the second secondary line do-g_do-3 to the external terminal 217. At the same time, only four second data buffers 2 and 214 are shown in FIG. However, fewer or greater numbers of second data lines can be used. More specifically, as shown in FIG. 3, the multiplexer 313 is configured to: in a normally operating chess style, as shown by the upper third of the multiplexer 3Ua, a corresponding first data line 212 The coupling $. ^ is coupled to a corresponding second data line 214, and in the first mode of the test mode of operation, also known as test mode 1, which is shown in the middle of the multiplexer 3 13a In the evening of the Gongxi ^ Ί one knife), the corresponding even number of brothers and one poor material line are combined to the corresponding even second data line and the corresponding number of younger brothers in the field, the poor material line 'and in the test mode of operation The second sub-mode (also known as test mode 2, which is shown in the lower third of the multiplex 3|3 ** 313a), couples the corresponding odd first data to the Millennium into the corresponding The odd second data line and the corresponding adjacent even second data. ^ ^ ^, 枓 line. It should also be understood that more than two test modes can be supported. Correspondingly, as shown in FIG. 3, in the proper ten operation mode, the first data line RDIO is coupled to the corresponding second needle thread DO, thereby at a first data rate (eg, DDR SDRAM data rate, έ μ The mountain mussels are caught early and provide output from the output buffer 313. During the first test mode or the first sub-mode + ώ _ fruit, the data from the even first data lines RDIO-0 and RDIO 2 are back to V, and the next day can be controlled to even and odd second. The data line DO_〇_D〇3 is such that the resource is supplied from the side shell to the output buffer state 3 1 3 b in a replica form and thereby a second lower than the first Lebeco rate The data rate (eg SDR SDRAM data rate) round + noon) is output to the external terminal 2 1 7 . Finally, in the second test mode or the second sub-mode, the data on the first data lines RDIO 1 93587.doc -18-1250531 and RDI〇_3 are simultaneously copied to the odd and even second data lines. On DO-0-DO-3, the data is provided to the output buffer pass at a second rate lower than the first data rate. By &amp;, in the test mode, the output window of the output buffer 313b is enlarged compared to the data window of the data read from the memory array 211, and is doubled in some embodiments. As a result, the UDrsdram test equipment and/or multiple SDR test equipment can be tested for SDRAM due to the expansion of the data window. Still referring to FIG. 3, the -mode register set (_) 315 can be configured to generate the first and second test mode signals Xiang, ΤΜ2 in response to the plurality of command signals to place the multiplexer 313a in the test operation. In the first and second submodes of the mode. The command signals may include a column of address control signals (RASB), a row of address strobe signals (CASB), a write-once signal (web), and a number of address signals. Since the MRS 3 15 is provided in the integrated circuit memory device 300 of some embodiments of the present invention, the test can be performed after the package. 4 is a schematic illustration of a multiplexer 313 (e.g., multiplexer 313a shown in FIG. 3) that may be provided in accordance with some embodiments of the present invention. As shown in FIG. 4, the multiplexer 313a includes a first switch 42A configured to set a corresponding even first data line RI)I 〇 〇, Rm 在 in the first sub mode (TM1). One 2 is coupled to the corresponding even-numbered two data lines D〇_0, D0-2; a second switch 430 is configured to place a corresponding odd first data line RDI0 in the second sub-mode (TM2)— 1. RDI0-3 is coupled to a corresponding odd second data line DO-1, DO-3; and a equalization circuit 440 is constructed for use in the first and 93587.doc -19-1250531 second submode A corresponding odd second data line d〇j, d〇” is coupled to a corresponding adjacent even second data line D〇—〇, D〇—2. Correspondingly, as shown in FIG. 4, the first read data RDI〇_G and RDI0_2 generated by the memory cell array 211 on the first data line 212 are respectively converted into the second data according to the first test mode signal (tm i). The second read data on the line 214 is d〇_〇, D〇−2°, and the equalization circuit 44G is activated to enable each-to-even/odd second read data (DO-0/1, DO_2/3). Both remain at the same level, while the second switch 43A for receiving the second test mode signal (TM2) is deactivated. The odd-numbered read data RDIQ_丨 and RDIq-3 can also be processed in the same way, so that the effective data window of the output data DOUT can be expanded to twice the normal mode. In the normal mode, the equalization circuit 44 is deactivated. 5 is a timing diagram corresponding to a normal operation mode and a test operation mode of reading data from a self-memory material according to some embodiments of the present invention (such as the embodiment described above with reference to FIGS. 3 and 4). . As shown in Fig. 5, in the normal mode, the read data DO_D3 is transmitted to the external terminal _〇υτ in response to the rising edge L of the falling edge of a clock signal (clk). In addition, as shown in FIG. 5, in the test mode towel, the even and odd data (D〇_0/2, DO_丨/3) are respectively transmitted in the data window W2 which is expanded by two in response to the rising edge of an external clock signal. To the external terminal D〇UT. Figure 6 is a more detailed timing diagram illustrating the operation that can be performed by an output circuit in accordance with an embodiment of the present invention (e.g., the embodiment described in connection with Figures 3-5). As shown in Figure 6, a first internal clock The LDQ-F is generated in response to the rising edge of the clock signal CLK. One 筮^^ ° The internal clock signal CDQ~8 is generated by the falling edge of the clock CLK. In the positive hanging type, the round out 93587.doc -20· 1250531 The data DO-D3 should be transmitted to the external terminal D〇UT according to the CDQ-F and CDQ-S signals corresponding to the rising and falling edges of the clock signal. In test mode 1, since the even and odd data remain at the same level, the output data D0 and D2 are transmitted to the external terminal d in an expanded data window. In test mode 2, the output is also (10) and Similar work is provided. Those skilled in the art should also understand that the DOUT output of the test mode and the test mode 通常 usually occurs when the phase is found in mutually offset clock cycles, rather than as shown in Figure 5 and Figure 6. In the same or overlapping clock cycles. The clock cycles that are not overlapped in FIG. 5 and FIG. 6 are in order to compare the normal mode with the test mode and not to extend the width of the A timing chart. 4 Release the 龙(()) Memory: The method. In general, in such embodiments, the memory cell array can: - have a clock signal with rising and falling edges. In normal, the output circuit can be generated by the library in the form of an internal clock signal and the second internal time n8, the fourth internal clock signal is generated in response to the clock edge. - An apostrophe such as &amp; + ° A Jl rising edge is generated in response to a falling clock signal. However, in the test mode of operation, the input should be the first internal clock signal or the second internal, only the mouth, in the test mode of operation, the data bit can be output lower than the data rate. . The second rate of the arrest rate, more specifically, the same as the seven, see Figure 7, in these embodiments, including more than one m of the multiplexer 73 city: ^ ^ ^ ^ mode, such as (For example) multiplexer 7 - three-point operation: a corresponding first - data line corresponding second data I: will be 93587.doc 1250531 and in the first D of the test mode of operation, such as more m3a (9) _= (also referred to as test mode in Figure 7 - data line 212 • combined to one phase; ... shown, will be - corresponding first model 々 > Chu _ μ 0 brother a shell line. Finally, in the test The operator cries, (also referred to as test mode 2 in Figure 7), as shown in the lower part of the multi-°° a--, the corresponding odd data line 212 is coupled and coupled to 5_ and even One (four) selects the even and odd second data lines 214. Still shows the succession of Figure 7, the output circuit also sighs an output buffer. In the forward mode of operation, the output buffer 7 an internal clock signal CDQ F , potted plastic library in 昧妒 ^ * Yingdi, and - brother two internal clock signal CDq-s, which responded to the decline of the edge. In the test of the talents of the tester L in the first mode of operation and Ϊ"; \ Specifically, in the test and the first sub-mode, the output buffer 733b only responds to the two internal clock signals or the: internal clock signal. In some implementations, as shown in FIG. 7, in the test mode of operation, The output buffer disables the second internal clock signal cDq_s in the first and second submodes of the test mode of operation only in response to the » brother: the clock signal CDQ_p. Accordingly, Figure 7 illustrates how the mode is in test mode. The second clock signal C^Q_S is deactivated, and the effective data window of the output data d〇ut of the output buffer (10) is compared with the effective data window of the read data 〇_〇RDIO-3 outputted by the § memory cell array 211 The window is expanded by a predetermined value, for example, doubling. Thereby, the output buffer is not manipulated by the second internal clock signal cdqs, so that the read data Dq_g_Dq-3 can be output to the external terminal 217 with the expanded active data window. Figure 8 is a schematic illustration of a multiplexer embodiment 93587.doc -22-1250531 (e.g., multiplexer 733a of Figure 7) in accordance with the embodiments of the present invention. As shown in Figure 8, the multiplexer Unit - circle 20, which is constructed for use in i-normal mode Coupling a corresponding first data line Rdi〇-3 to a corresponding second data line D〇_〇_d〇-3 in the first sub-unit (TM1); a second switch 83〇, the structure thereof For combining the corresponding odd and even first resources (four) in the second sub-mode (top 2) to the corresponding even and odd second data lines. Therefore, the first data line 212 is generated by the memory cell array. The first read data (RDIO_〇_RDI〇_3) is correspondingly transmitted to the second data line 2 i 4 (DOJ)_D〇_3 in response to the first test mode signal. Similarly, each first read data (RDI〇_〇-RDI〇_3) generated by the memory cell 2Π on the first data line 2]2 is correspondingly transmitted to the adjacent side according to the second test mode signal (tm2). The second data line 2l4 (D〇i/D〇〇, D〇3/DO-2). Figure 9 is a schematic illustration of an output buffer (e.g., output buffer 733b shown in Figure 7) in accordance with the embodiments of the present invention. More specifically, as shown in FIG. 9, the output buffer 733b includes: a corresponding plurality of registers 910a-910d' wherein the corresponding register is configured to store a read from a corresponding first data line 212. Take the data; associated with the corresponding one-time temporary crying (four) a / ring, 910c / 910d - latch 9 heart, fiber, a corresponding latch 920a · · constructed to respond to the first - internal clock signal γ 2, called to latch the data from the - 1st adjacent register and in response to the second internal clock signal S CLK, 2nd s clk) to latch the data from a second her neighbor register; - constitute - multiplex The parallel-to-serial converter of the 930's parallel-serial converter can be plasticized in the normal operation mode. 93587.doc -23- 1250531 in the (four) registers 92〇a, 920b, the first and second internal clocks The signal, while during the 4th first and second operational submodes, the multiplexer only responds to one of the first and second internal clock signals. / More specifically t, the second read data on the second read data line 214, DO_0-DO-3, is transmitted to the scratchpad 91〇a-910d in response to the internal clock signal line. In the normal operation mode, the data D〇-〇&D〇-i stored in the upper part of the memory unit 91〇a, 910b in Fig. 9 corresponds to the first rising edge and the younger: the falling edge clock (1st F CLK^lSt s CLK) is sequentially transmitted to the first-latch If 92Ga, and each of the data stored in the bottom two registers 91 (^, 9(10), DO-2 and 00-3, is in response to the second The rising edge and the second falling edge clocks WF CLK and W s CLK) are sequentially transmitted to the second latch 920b. Therefore, in the normal operation mode, each data 输出 3 is output to the external terminal 217 in response to the first and second internal clock signals (cdq_f1, CDQ-S) sequentially activated. However, in the test mode of operation, even the data DO_0 and DO-1 stored in the upper two registers 91〇a, 91卟 in FIG. 9 correspond to the first rising edge and the first falling edge clock 〇st f And the occurrence of lstS CLK) is sequentially transmitted to the first latch 92Qa, and only the data DO_〇 is transmitted to the external terminal 217 at a second data rate lower than the first data rate, which is only the first The internal clock cdq-f starts. In addition, even if each of the data stored in the bottom two registers 91〇c, 91〇d DO-2 and DQ-3 also corresponds to: rising edge and second falling edge clock (π CLK and 2nd S CLK) The occurrence is sequentially transmitted to the second latch, and only the tribute DO-2 is transmitted to the external terminal 217 at a second data rate lower than the first data rate in the normal mode. In other words, the valid data window is expanded by inputting the next rising edge clock (CDQ-!^) for the data d〇—2 93587.doc -24-1250531 and outputting the lean material DO_υ ^4 ='. In the first: test mode (), per-to-read data deletion, 3 is also converted into the second read data 〇〇_〇'2. Then, the 'data (10)-^ is transmitted to the foreigner, 'Wuzhi 21 7'. Therefore, in the two test modes (TM1, TM2), all data RDIO_〇_RDI〇-3 can be output to the outside. Figure 9 also shows a logic circuit 940 which can be used as a clock CDQ_S. During the test mode, the falling edge = system-time phase, the money release is in normal operation _ and during the test = period (for example) the embodiment shown in Figures 7-9 is used to generate the output data. If the response may be in response to the clock period 'rounding circuit 733 clock signal CDQF and two: = rising edge, the first - internal &amp; amp &amp; - θ should be generated by the falling edge of the % buckle signal CLK The second internal clock is used as a data bit - ηη, and the complex data, such as R a _D3, is serially outputted to an external terminal at the first data rate. During the test mode period, D θ 1〇 is shown in the lower part, and the output circuit 733 is only due to the shore clock signal or the second internal clock “= internal internal-internal clock signal CDQf:=t: Demonstrated as due to the test mode only period, the even ~ / lower 〇 points are shown in the data on the first - data speed Γ / line D0- ° and D 〇 2 low:: However in test mode 2 It is also possible to execute the class = even test line. Therefore, the operation during the recipe (7) shown in the formula 1 can be the same as in the test simulation, except that the test pattern 2 is used to rotate the data D1. 93587.doc -25 - 1250531 and D3. * and to Figure 13 show an integrated circuit memory device and method of operation according to still further embodiments of the present invention. As will be explained below, in these embodiments, the output circuit is The normal operation mode may be responsive to: a first internal clock signal generated in response to a rising edge of the clock signal; and a second internal clock signal generated in response to a falling edge of the clock signal. Wu Shizhong, the output circuit can alternately respond to the first internal clock And the clock signal of the part. More specifically, referring to FIG. 11, the memory cell array 2 I 1 is configured to output a plurality of data by using the first data to the data line 212 of the field 奵 k of the library The round-out circuit includes an output buffer = the round-out buffer 1143 is configured to output the data string to a further specific one and the right winter map, and the memory cell array 211 can be properly and more heavily than the Yi 4 The edge of the edge buffer. The output buffer U43 is in the middle of the "internal clock signal CDQ F, the soybean meal should be generated on the rising edge of the clock signal." and the number CDQ-S, The bean 燮廍 一 一 内 内 内 内 内 内 内 ; ; : : : : : : : : : : : : : In the fruit-measurement (10)1), the output buffer &quot;43 is only because of the first internal clock signal of the shore or the second inner ohm only responds to the first-internal clock (four) cd〇f: In the mode (such as mi / Q - F. In the test mode of the test mode shown in the test mode 2), the round out m η only due to the first - internal clock) #出, ...1143 - in the figure u&quot ;f... The other part of the clock signal is only for the second internal clock neDQ s. Therefore, in the figure, the test mode is Tiger Q~S. In the 犋 formula, each 93587.doc -26- 1250531 = Q_F and CDQ: Sk number can be alternately deactivated to expand the output data of the output buffer I ΐ 43. In some embodiments, the first internal clock pass ^ ^ ^ 1 port Q CDQ_F is deactivated in the second test mode and the second internal clock signal CDQ S is deactivated in the first test mode. By + _ ^ ^ Thus, the expanded data can be outputted by an expanded view ® . Figure 12 is a schematic diagram of the present invention; 丨 + one of the two known output buffers (e.g., the output buffer 1143 shown in Figure 11) holds the FI f gate ghost map. As shown in FIG. 12, the output buffer 1 M3 includes a plurality of registers 121 corresponding to the center (2) (10), wherein a corresponding register is configured for storing from a Japanese calendar, from the first, the 丨... The reading data of the first data line corresponding to the wood object '· and a latch 122 〇 a, 〖 with a corresponding pair of her neighbor registers (2) 〇a/121〇b, 12 Gu 21〇d Bezier mouth 1220b, one of the latches 122〇a is configured to be latched from a first Tianbi neighbor with a response to the first-rising edge and the first falling edge clock signal (ist f clk &amp; 1 S CLK) The data of the register i2n m〇b, the latch (10) is also configured to latch from a second field adjacent to the second rising edge and the second falling edge clock signal (2nd F CLK and 2nd S CLK) The data of the devices 121〇c, i2l〇d; a parallel-to-serial converter 123〇, which can respond to the latches 122〇a, i22〇b, and the first and second internal clock signals CDq in the normal operation mode -f, CDQ-S, and only one of the first and second internal clock signals during the first test operation, for example, only in response to CDQ-F, During the second operating sub-mode only the test result and the other of the first internal clock signal should be, for example, only in response to CDq-s. Figure 12 also shows logic circuits 124A and 125A that can be configured to disable the first clock signal CDq-f in the second test mode, respectively, and disable the second clock signal CDQ_S in the first test shank. . 93587.doc -27- 1250531 A timing diagram of an operation performed by, for example, the output circuits shown in Figs. 11 and 12 in accordance with the present embodiment. As shown in the upper third of Figure 13, in the normal mode, the output circuit can respond to the first and second internal clock signals CDQ p, CD 〇 S, - i flute - DQ-S -. The internal clock signal Q_(or CDQ_F') may be responsive to the rising edge of the clock signal CLK, while the second internal day (4) number CDQ_S (or (3) Q_s,) may be responsive to the clock signal ,edge. In the first test mode, as shown in the middle third of FIG. 13, the second internal clock signal CDQ_S is disabled, and the output circuit is only in response to the first internal clock signal CDQ - in the second test mode. As shown in the bottom third of Figure ^, the turn-out circuit only responds to the second internal clock signal (DQ-S'). Therefore, as illustrated in FIG. 12, the data stored in the scratchpad circuits 1210a, 12i〇c are responsive to the first and second rising edge clock signals (7)F CLK, WF CLK). It is transferred to latch circuits 1220a and 1220b. Thereafter, until the next internal clock signal (cdqj,) is outputted next time, the next data output is outputted until the next D〇2 is outputted, thereby expanding the effective data window. In test mode 2, the odd data stored in the register circuits 1210b, 1210d are transmitted to the latching crying circuits 1220a and 1220b in response to the first and second falling edge clock signals (1st S CLK, 2nd S CLK). . Thereafter, until the data do-3 is outputted after the second internal clock signal (CDQ-S') is next rising, the data DO-1' is always outputted, thereby expanding the effective data window of the odd data. 14-16 illustrate further integrated circuit placement and operation methods in accordance with further embodiments of the present invention. In general, in these embodiments, the output circuit can respond to a first internal clock signal in a normal mode of operation and - a second 93587.doc -28-1250531 internal clock signal, wherein the first internal clock number rises The result is that the _ ', θ %, is generated by the internal clock signal of the clock signal. However, the stomach should be in the clock signal and in the test mode 4, the one should be based on the first internal # output circuit, the minute signal generated by the ^^ number and one according to the grandfather - the brother of Jiashibei Internally, the internal clock signal generated by the clock is generated by the clock. In a certain sinus, the sinusoidal signal of the sinus, and the frequency of the crossover - the half of the frequency of the internal clock signal and the frequency of the second internal clock signal. ‘,,,. More specifically, as shown in Figure 14, you can use a bed w, ~ to show the example, to make the 'first in first out (10) 〇) register 146 储存 to store from, -2 12 Shell material. In the normal mode one, "铪" μ 勒, after the 1463 can be made because of the internal clock of the younger brother and the second brother w ‘ 5 tiger. However, in the test mode TM, the turn-up buffer is in response to the crossover look-up, and the second internal clock signal. Therefore, in the test mode, the Japanese vehicle can be buckled into the cutting frequency, for example, the clock frequency is equalized. Therefore, in the test mode, the output data d〇ut- of the output buffer 1463 can be enlarged by performing a frequency division on each cdqfacdqs letter. In other words, each internal = clock signal CDQWCDQ_S can be divided into a lower frequency in response to the test mode signal TM. Test Mode ^ Tiger can be generated by receiving a plurality of command signals (RASB, CASB, pins) and a pattern register set (deletion) of a number of address signals. Therefore, during the test mode, the data window of the output data can be expanded. The W and 15B are block diagrams of the divider circuit 93587.doc -29-1250531 for generating a frequency-divided internal clock based on the internal clock in accordance with the embodiments of the present invention. Specifically, as shown in FIG. 15A, a first frequency dividing circuit, ρ 冓 is used to generate a first inner clock signal that is frequency-divided according to the first internal clock signal and a test mode selection signal TM. 15B does not, a second frequency dividing circuit 1500b is configured to generate a frequency-divided second internal clock signal CDQ_S' due to the 第 第 知 唬 及 CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD CD In the embodiment, the first frequency dividing circuit 150A includes a first frequency divider l5i, which should be in the rising edge of the clock signal and the test mode. signal. In a (four) embodiment, the second frequency dividing circuit 15_ includes: a second frequency divider measuring responsive to a falling edge of the clock signal and a test mode signal; and a delay element 1530 responsive to Second divider (10). In some embodiments, the delay element 153G is used to increase the interval between the first and second divided clocks to enable the output of the external terminal 217 in an expanded effective data window. The output of the office. Figure 16 is a diagram according to Figure 14. See the figure ", - and: = times 丄〇 枓 枓 RDIO - 0 - RDIO 3 first i:: r 〇 register 1460" and then transmit half of the internal clock signal: (4) 146V thereafter: in normal mode In, as shown in Figure 16, CDQ S) to I - in response to the younger brother: the internal clock signal ((3) ^ and ° output output (four) Jay 1463 all the information. And in the test IL diagram half of the 'output buffer (4) 3 The output data D(10) is output according to the first- and second (four) clocks of the frequency division, so that the valid data window can be expanded. Since 1 = 93587.doc -30- 1250531, the output buffer can be halved in the embodiment t. The speed operates, and the cell array operates at full speed as in the normal mode. ~ Figure η - (d) Operation of various embodiments of the present invention - (d) Operational flowchart of a circuit recording device, the integrated circuit memory device has - Constructing a cell array for outputting a plurality of data bits in parallel at a first data rate. These operations can be performed using the embodiments shown in the above 2_16. As shown in Figure 17, when at block 171, select positive

In the normal mode, then a plurality of data bits are serially output from the memory cell array to an external terminal at a first data rate in block 1720. In block 1730, when the -test mode is selected, a plurality of data bits are then rotated out of the memory array to the external terminal in block (10) at a second data rate lower than the first data rate. Such operations may be performed in accordance with any of the embodiments of the invention described above, using the embodiments illustrated in Figures 2, 3-6, 7_1, U-13A, or 14-16. In the drawings and the description, several embodiments of the present invention have been disclosed, and the specific terms are used, but the terms are only used in a generic and descriptive sense, and are not intended to be limiting. The scope is set forth in the scope of the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a timing diagram of an operation performed by a conventional double data rate and a single data rate memory I; FIG. 2 is an integrated circuit memory crack according to several embodiments of the present invention; FIG. 3 is a block diagram of an integrated circuit memory device 93587.doc 31 1250531 and an operation method according to other embodiments of the present invention; FIG. 4 is a view of another embodiment according to the present invention. The schematic diagram of the multiplexer in the embodiment shown in FIG. 3; FIG. 5 and FIG. 6 are timing diagrams of operations that can be performed in the embodiments shown in FIGS. 3 and 4 according to various embodiments of the present invention; FIG. 7 is a block diagram of an integrated circuit memory device and a method of operation according to other embodiments of the present invention; FIG. 8 is a multiplexer according to another embodiment of the present invention, which can be used in the multiplexer of the embodiment shown in FIG. FIG. 9 is a schematic diagram of an output buffer that can be used in the embodiment shown in FIG. 7 according to other embodiments of the present invention; FIG. 1 is a second embodiment of the present invention, and may be embodied by the embodiment shown in FIG. When the homework is performed Figure 11 is a block diagram of an integrated circuit memory device and method of operation in accordance with still further embodiments of the present invention; Figure 2 is a block diagram of another embodiment of the present invention. Schematic diagram of an output buffer in the example; FIG. 1 is a timing diagram in the embodiment shown in FIGS. 11 and 12 according to other embodiments of the present invention; FIG. 14 is a further embodiment according to the present invention. FIG. 15A and FIG. 15B are block diagrams of a distributor circuit in the embodiment shown in FIG. 14 according to other embodiments of the present invention; FIG. 16 is a diagram of a distributor circuit according to the present invention; Still further embodiments are illustrated by the timing diagrams of the operations performed by the embodiments illustrated in Figures 15 and 93587.doc - 32-1250531 and FIG. 15B; FIG. 1 is a flowchart that can be performed in accordance with various embodiments of the present invention. Operation flow [Main component symbol description] CLK clock signal R Read command W Write command DQS Data strobe signal Q〇 Data Q1 Data Q2 Data Q3 Data D0 Data D1 Data D2 Data D3 Data 200 Integrated circuit memory Device 211 Memory Cell Array 212 First Data Line 213 Output Circuit 214 Second Data Line 217 External Terminal DR1 First Data Rate DR2 Second Data Rate

93587.doc -33 - 1250531 300 Integrated circuit memory device 313 Output circuit 313a Multiplexer 313b Output buffer 315 Mode register set RDI〇_0 First data line RDI〇_1 First data line RDIO_2 First Data line RDIO_3 First data line DO_0 Second data line DO_l Second data line DO_2 Second data line DO__3 Second data line RASB column Address control signal CASB Line address strobe signal WEB Write signal CDQ_F First internal clock Signal CDQ_S Second internal clock signal TM1 First test mode signal TM2 Second test mode signal 420 First switch 430 Second switch 440 Equalization circuit W1 Effective tribute window

93587.doc -34- 1250531 W2 expanded data window DOUT external terminal 733 output circuit 733a multiplexer 733b output buffer 820 first switch 830 second switch 910a register 910b register 910c register 910d register 920a latch 920b latch 930 multiplexer 940 logic circuit CDQ_S, second internal clock signal 1st F CLK first rising edge clock 1st S CLK first falling edge clock 2nd F CLK second rising edge clock 2nd S CLK second falling edge clock 1143 output buffer CDQ_F first internal clock signal 1210a register 1210b register 93587.doc -35- 1250531 1210c register 1210d register 1220a latch 1220b latch 1230 Parallel to serial converter 1240 logic circuit 1250 logic circuit TM test mode 1460 first in first out register 1463 output buffer 1500a first frequency dividing circuit 1510 first frequency divider 1500b second frequency dividing circuit 1520 second frequency divider 1530 delay element 93587.doc 36-

Claims (1)

1250531 X. Patent application scope: 1. 2. An integrated circuit device, comprising: a memory cell array, a plurality of g 4 m outputs a plurality of shell elements in parallel at a first data rate; and * The output circuit 'is configured to output the plurality of data bits in an external mode at the first rate in the normal mode of operation to: an external mode: in the test mode of operation - below the first data rate: The first billet rate outputs the plurality of data bit strings to the external terminal. 1 The integrated circuit device of claim 1, wherein the memory cell array is responsive to a clock signal of a rising edge and a falling edge, wherein the first data rate is generated according to both a rising edge and a falling edge of the clock signal, and Wherein the second data rate is generated only by one of a rising edge or a falling edge of the clock signal. The integrated circuit device of the monthly squad 1 , wherein the memory cell array is configured to perform a plurality of shell 兀 via a corresponding plurality of first data lines (four) first-data rate parallel input X, and wherein the output circuit structure For: in the normal operation mode, using the corresponding plurality of second data lines to serially output the plurality of data bits to the external end at the first data rate, and using the corresponding in the test operation mode The plurality of feed lines are serially output to the external terminal at the second data rate lower than the first data rate. (The request circuit! The integrated circuit device, wherein the output circuit is configured to: in the X call 4 operation type, copy the 93587.doc 1250531 parallel output of the memory cell array by a plurality of data bits _ 资 , , , 丨 口 「 「 「 「 「 「 「 「 「 「 「 「 「 「 「 「 「 「 「 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于a second portion of the plurality of data bits output by the memory cell array to obtain a second portion of the plurality of data bits at the second data rate of the data rate Partial serial output to the external terminal. 2 Integral 1 integrated circuit device 'where the memory cell array can respond to a clock with a rising edge and a falling edge of the clock, the output circuit can be due to the library ... The script operation mode responds to the internal clock signal of a younger brother, which responds to the clock signal of Shanghai, the farmer*, the generation, and a second internal clock letter 掇彳+ &quot; In the test operation, the second internal time of the output is a signal-to-section clock signal or an integrated circuit device of the:::1, wherein the memory cell array can be in the same manner as the rising edge and the falling edge of the memory cell, the 钤屮Φ °~8 in the The normal operation mode is 卞 / ' can be responded to: H part of the clock signal, a plastic should be produced on the rising edge of the side clock signal ..., nickname, which responds to the falling edge of the bell signal and is called in the clock mode兮 屮 屮 屮 々 々 , , , , , , , , , , , , 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二In the middle, the round-out circuit can be: "°J' 2 in the normal operation mode should be the rise of the clock signal two::::=, which sighs an internal clock letter 93587.doc 1250531 is) its In response to the clock transmission πτ政 k _ mode, the evaluation = ' and generated in the test number. Then according to the first internal clock, ',, the knife frequency of an internal clock signal And a frequency-divided second internal clock signal generated according to the first inner 8. L唬For example, the integrated circuit device of the first item: material:::, the memory cell array is configured to output the complex numbers in parallel via the corresponding plurality of packets - the data - the data rate - wherein the output circuit includes , mouth 兀, and the first data t ^ _ 夕工, its structure is used to multiplex the data of the continuation of the data, the ancestors of the ancestors L / forging to the corresponding number of bars second 9. 乜V And an output buffer 'which is configured to output the data string on the first-data line to the external terminal. The special brother-Bei Ruyi seeks the integrated circuit device of item 8: wherein the multi-two device is configured to: in the normal operation mode, 'couple a corresponding data line to 5 to a corresponding second data line And in the first mode of the test operation mode, the early first battle line ^ ^ sub-style, the corresponding even first line is consumed to the corresponding even second data line, and a f two in the test mode of operation : In the mode, the corresponding odd-number data line is merged to the corresponding second data line. 10 - an integrated circuit device comprising: ·, - memory (four) column 'is configured to output a plurality of data bits in parallel via a corresponding plurality of first data lines at a first tributary rate. And configured to output the plurality of data bits in series to the external material at the first barren rate in the normal operation mode, and to lower the first data in the test operation mode Rate 93587.doc 1250531 The second data rate serially outputs the plurality of data bits to the external: end: the output circuit includes: a multiplexer configured to read the first-data line Data multiplexing and multiplexing to a corresponding plurality of second breeding lines; and an output buffer configured to output the data series on the second data line to the external terminal; a set, which is responsive to a plurality of command signals and configured to generate the first and second test mode signals to place the multiplexer in the first and second sub-modes of the test mode of operation; The tool is constructed for: in the normal In the operational mode, a corresponding first lean line is coupled to a corresponding second data line; in the measurement. In the first submode of the mode of operation, the corresponding even first data line is coupled to the corresponding even second data line; and in the second submode of the test mode of operation, the corresponding odd first data line is coupled Up to the corresponding odd second data line, and comprising: a first switch configured to lightly couple an even number of data lines to a corresponding even second data line in the first sub mode; a switch that is configured to couple a corresponding odd first data line to a corresponding odd second data line in the second sub-mode; and an equalization circuit configured to be used in the first In the second sub-mode, the corresponding odd second data lines are coupled to a corresponding adjacent even-numbered data line. 11. The integrated circuit device of claim 9, further comprising: a set of mode registers, wherein the set of mode registers can be configured to generate the first and second test mode signals in response to the plurality of command signals The 93587.doc 1250531 submode=work &amp; is respectively set as the first and the i2th integrated circuit device of the test operation mode, which comprises a memory cell array, which is suitable for! A plurality of data bits are outputted by the corresponding plurality of first credit lines at a data rate of one brother and one data volume; an output % road is constructed for a plurality of data bits at a data rate (four) The first end of the element, and in the -test mode of operation: = output to - external terminal - secondary ancestor, n is lower than the younger one of the poor material rate of the mountain #山灵数贝科位兀 serial output to the Externally, the output circuit comprises: a basket one: the under-harvesting state, the structure is used to apply the μ. , the 蚪 工 after the work to the corresponding plurality of second negative material lines, and the wheel屮结施: j., ,, 11 idioms, whose structure is used to serially output the data on the second data line to the external terminal; , a mode register set, i can be at the place ~ y person - The port should be configured with a plurality of command signals and configured to generate the first and second test mode signals 'to place the multiplexer in the first test mode and the second sub mode respectively; wherein the multiplexer Constructed for: in the normal operation mode, a corresponding first data line is lighted to - corresponding a second data line; in the first-sub mode of the test mode of operation, combining the corresponding first data (4) to a corresponding second data line; and in the second sub-mode of the test mode of operation, corresponding The odd and even first data lines are coupled to the corresponding even and odd second data lines. 13. The integrated circuit device of claim 12, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge, wherein in the normal operation 93587.doc 1250531 mode, the output buffer is responsive to: - a first internal clock signal responsive to a rising edge of the clock signal; and a second internal clock signal responsive to a falling edge of the clock signal, in the first and second of the test mode of operation In the sub mode, the output circuit only responds to one of the first internal clock signal and the second internal clock signal. 14. The integrated circuit device of claim 12, wherein the multiplexer includes: a first switch configured to couple a corresponding first tributary line to a corresponding one in the first sub-mode a second data line; and a second switch configured to align the corresponding odd and even first data lines to the corresponding even and odd second data lines in the second sub-mode . 15. The integrated circuit device of claim π, wherein the output buffer comprises a plurality of corresponding registers, wherein a corresponding register is configured to store a read from a corresponding first data line. Data; a latch associated with a corresponding pair of adjacent registers, wherein a corresponding latch is configured to latch data from the contiguous register in response to a first clock signal and to respond to a second clock signal to latch data from the second neighbor register; and a parallel-to-serial converter that can wait for the latch, the first and second internal clocks in the normal operation mode The signal is only due to one of the first and second internal clock signals during the first and second operational sub-modes. The integrated circuit device of claim 1, wherein the memory cell array is configured to output the plurality of data bits in parallel at the first data rate via a corresponding plurality of first resources 93587.doc 1250531 feed lines And the output circuit includes an output buffer configured to output data to the external terminal string. 17. The integrated circuit device of claim 16, wherein the memory cell array is responsive to a clock signal having a rising edge and a falling edge, wherein in the normal operating mode, the output buffer is responsive to: a first internal clock a signal responsive to a rising edge of the clock signal; and a second internal clock signal responsive to a falling edge of the clock signal, the output being in a first sub-mode of the test mode of operation The circuit only depends on one of the first internal clock signal and the second internal clock signal. In a second sub-mode of the test mode of operation, the output circuit only depends on the first internal clock signal and the second internal clock signal The other one. 18. The integrated circuit device of claim 17, wherein the output buffer comprises: a corresponding plurality of registers, wherein a corresponding register is configured to store a read from a corresponding first data line Data; a latch associated with a corresponding pair of adjacent registers, wherein a corresponding latch is configured to latch data from a first adjacent register in response to a first clock signal and to react a second clock signal to latch data from a second adjacent register; and a parallel-to-serial converter that can wait for the latch, the first and second internals in the normal mode of operation a clock signal, and during the first operational sub-mode, the parallel-to-serial converter only responds to one of the first internal clock signal and the second internal clock signal during the second operational sub-mode, The other of the first internal clock signal and the second internal 93587.doc 1250531 clock signal should be used. 19. The integrated circuit device of claim 17, further comprising: - a mode register set, wherein the mode register set can generate a plurality of commands = number, and construct a poem to generate the first and second test mode signals, The μ output buffers are placed in the test mode mode, respectively. 20. The integrated circuit device of claim 16. wherein the memory cell array is responsive to: a clock signal having a rising edge and a falling edge, wherein in the normal operation, the output buffer is configurable. In response to a first internal clock signal, the first internal clock signal is generated in response to the rising edge of the clock signal of the clock signal; and a second internal time 4 signal is decreased in response to the clock 1d. The edge is generated, and in the test mode of operation, the output buffer is _divided by the H-part clock letter f-divided by: (iv) the clock signal. 21. The integrated circuit device of claim 20, wherein the frequency-divided first internal: "the child signal and the frequency-divided second internal clock signal are respectively the first internal clock signal and the flute" ..., 一半 half of the frequency of the first internal clock signal. 22. The integrated circuit of claim 20, further comprising: a mode register set, the 掇+封+^ 权 register set In response to a plurality of commands 4 ’ and configured to generate a modal mode signal, the output buffer is placed in the test mode of operation. 23·If the integrated circuit of claim 2 is installed, The method further includes: a first slot frequency circuit configured to generate the frequency-divided first internal 93587.doc 1250531 clock signal in response to a rising edge of the clock signal and a test mode selection partner; and a second score The frequency circuit is configured to generate the sub-@ lt lt; an internal chirp clock signal in response to the falling edge of the clock signal and the test mode selection signal. 24. The integrated circuit device of claim 23: Which of the first - The frequency circuit includes a first frequency divider, the first responsive to the rising edge of the clock signal and the test mode signal; and wherein the second frequency dividing circuit comprises: a second frequency divider, the second eight The frequency element may be responsive to the falling edge of the clock signal and the test mode signal; and a delay of 70 pieces, the delay element may be crying in response to the second frequency division. A operation-having-construction for the -first data Rate flat: A method of outputting an integrated circuit device of a memory cell array of a plurality of data bits, the method comprising: ???operating a plate type of the plurality of solid-depleted material bits from the memory cell at the first data rate The array serial output is output to the first test mode, and the first data rate lower than the first data rate is outputted from the memory cell array to the external terminal 26 · In the method of claim 25, the child is: in the sling operation mode, the multiplexed r-codes are output from the memory cell array to an external terminal at the first data rate: in the normal operation mode, Responding to the -clock signal (Iv) have edges ^ / -f the feed rate of the second plurality of data bits from the other port Xiang. The array of cells has been circumvented to the external terminal, and 93587.doc 1250531, wherein in the test operation mode, the plurality of data bits are lower than the data rate lower than the first data rate. The output from the (4) (4) (4) column to the external terminal includes: in the -test mode of operation, only the rising edge or the falling edge of the clock signal - the second data rate lower than the 料 = material rate And a plurality of data bits are outputted from the three-cell memory array to the external terminal. 27. The method of claim 25, wherein in the -test mode of operation - below the first-rate rate: data material (4) a plurality of data bits are serially output from the memory cell array to the external terminal : the second portion of the plurality of data bit data rates is serially outputted to the first portion of the copy that is rotated in parallel by the memory cell array to be a plurality of lower than the first material rate a second terminal of the data bit; and a second portion of the plurality of data bits outputted by the memory cell array to be lower than ^. The second data rate of the lean material rate outputs the plurality of data bits, the first portion of the beta bit only 7L, to the external terminal. 28. The method of claim 25, wherein the memory cell array responds to a clock signal having a rising edge and a falling edge; wherein in the normal operating mode, the plurality of data bits are from the memory at the first data rate The serial output to the external terminal includes: a first internal clock signal that produces ± in response to a rising edge of the clock signal and a 93587.doc -10- generated in response to a falling edge of the clock signal L25〇53l two internal clocks (4), with the first data transfer material, a plurality of data from the memory cell array serial output to an external terminal; and from the - test operation mode - below (four) - data And outputting, by the second data rate, the plurality of data bits from the memory cell array to the external terminal, including: only the first internal clock signal and the second internal clock signal, And outputting the plurality of data bits from the memory cell array to the external terminal at the second data rate of the first data. 29. The method of claim 25, wherein the memory cell array corresponds to a clock having a rising edge and a falling edge; wherein the plurality of data bits are at the first data rate in the -book operating mode Transmitting from the memory cell array to the external terminal includes: a first internal clock signal generated in response to a rising edge of the clock signal and a second internal portion generated in response to a falling edge of the clock signal a clock signal outputting the plurality of data bits from the memory cell array to an external terminal at the first data rate; and - wherein a test operation mode is lower than the first data rate And outputting, by the data rate, the plurality of data bits from the memory cell array to the external terminal: alternately responding to (4) the internal clock signal and the second internal clock signal to be lower than the first data rate The second data rate rotates the plurality of data bits from the memory cell array to the external terminal. 3 0. The method of claim 25 · 93587.doc 1250531 wherein the memory cell array responds to a signal; the clock with rising edge and falling edge is in a normal operation. The plurality of feed cells are output from the memory cell array to the external line end including: a first response to the rising edge of the clock signal: a partial clock signal and a response edge of the clock signal Generating an internal clock signal to output the plurality of data bits from the memory cell array to an external terminal at the first data rate; and - wherein a test operation mode is lower than the first And outputting, by the second data rate of the data rate, the plurality of data bits from the memory cell array to the external terminal, comprising: responding to the frequency-divided _inner clock generated according to the first internal clock L唬And the signal-divided second internal clock signal generated by the (IV) two internal clock signal, the plurality of data bits being from the memory cell array at a second data rate lower than the first data rate The method of claim 25, wherein the memory cell array is configured to output the plurality of data bits in parallel at the first data rate via the corresponding plurality of first data lines, and The memory device is configured to output the plurality of bits to an output terminal via a corresponding plurality of second data lines; wherein the plurality of data bits are at the first data rate in a normal operation mode Serializing the output from the memory cell array to an external terminal includes: coupling a corresponding first data line to a corresponding second data line in the normal operation mode; and 93587.doc 1250531 wherein a test operation mode In the middle of the one by one #一^^-...Haidi, the rate of the second rate of the feed rate, the data rate of the plurality of data bits from the 4 C memory array is serially outputted to the external terminal including: operating in the state of the oyster The first mode of the mode: in the mode, the corresponding even first data line is lightly coupled to the corresponding even second tributary line, and in the test mode of operation - the second sub = will correspond to the odd number The data line is coupled, and the corresponding second data line is. 32. The method of claim 25: wherein the memory cell array is configured to be used for slaves, and work by a plurality of first data lines corresponding to the first The data rate outputs the plurality of data bits in parallel, and the memory device is configured to output the plurality of bits to an output terminal via the corresponding plurality of second data lines, wherein in a normal operation mode In the normal operation mode, the corresponding first data line is included in the normal operating mode, wherein the data rate of the plurality of poor materials 7L is output from the memory cell array to the external terminal. Face to a corresponding second data line; and in a test mode of operation φ 宜(一) ^ Λ in a lower than the first data rate of the second sage rate, the plurality of carefully M y ^ 枓The bit is outputted from the memory cell array to the external terminal, and is included in the first sub-style of the test mode of operation, and the corresponding first ^ bead line is bonded to a corresponding second The feed line, and in the test operation 槿ΛΑ AI-style one brother two sub-mode, the corresponding countable and even number first carefully approved --, ^,, and the father is coupled to the corresponding even and odd brother two data line. 93587.doc