CN100474434C - Integrated circuit memory devices and operating methods configured to output data bits at a lower rate - Google Patents

Integrated circuit memory devices and operating methods configured to output data bits at a lower rate Download PDF

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Publication number
CN100474434C
CN100474434C CNB2004100794572A CN200410079457A CN100474434C CN 100474434 C CN100474434 C CN 100474434C CN B2004100794572 A CNB2004100794572 A CN B2004100794572A CN 200410079457 A CN200410079457 A CN 200410079457A CN 100474434 C CN100474434 C CN 100474434C
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Prior art keywords
clock signal
data
internal clock
transfer rate
data transfer
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CN1606091A (en
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李载雄
金致旭
姜尚锡
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • E—FIXED CONSTRUCTIONS
    • E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05C—BOLTS OR FASTENING DEVICES FOR WINGS, SPECIALLY FOR DOORS OR WINDOWS
    • E05C17/00—Devices for holding wings open; Devices for limiting opening of wings or for holding wings open by a movable member extending between frame and wing; Braking devices, stops or buffers, combined therewith
    • E05C17/02—Devices for holding wings open; Devices for limiting opening of wings or for holding wings open by a movable member extending between frame and wing; Braking devices, stops or buffers, combined therewith by mechanical means
    • E05C17/46—Devices for holding wings open; Devices for limiting opening of wings or for holding wings open by a movable member extending between frame and wing; Braking devices, stops or buffers, combined therewith by mechanical means in which the wing or a member fixed thereon is engaged by a movable fastening member in a fixed position; in which a movable fastening member mounted on the wing engages a stationary member
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • E—FIXED CONSTRUCTIONS
    • E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05B—LOCKS; ACCESSORIES THEREFOR; HANDCUFFS
    • E05B65/00—Locks or fastenings for special use
    • E05B65/08—Locks or fastenings for special use for sliding wings
    • E05B65/0864—Locks or fastenings for special use for sliding wings the bolts sliding perpendicular to the wings
    • E—FIXED CONSTRUCTIONS
    • E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05C—BOLTS OR FASTENING DEVICES FOR WINGS, SPECIALLY FOR DOORS OR WINDOWS
    • E05C17/00—Devices for holding wings open; Devices for limiting opening of wings or for holding wings open by a movable member extending between frame and wing; Braking devices, stops or buffers, combined therewith
    • E05C17/60—Devices for holding wings open; Devices for limiting opening of wings or for holding wings open by a movable member extending between frame and wing; Braking devices, stops or buffers, combined therewith holding sliding wings open
    • E—FIXED CONSTRUCTIONS
    • E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05C—BOLTS OR FASTENING DEVICES FOR WINGS, SPECIALLY FOR DOORS OR WINDOWS
    • E05C3/00—Fastening devices with bolts moving pivotally or rotatively
    • E05C3/02—Fastening devices with bolts moving pivotally or rotatively without latching action
    • E05C3/04—Fastening devices with bolts moving pivotally or rotatively without latching action with operating handle or equivalent member rigid with the bolt
    • E—FIXED CONSTRUCTIONS
    • E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05C—BOLTS OR FASTENING DEVICES FOR WINGS, SPECIALLY FOR DOORS OR WINDOWS
    • E05C5/00—Fastening devices with bolts moving otherwise than only rectilinearly and only pivotally or rotatively
    • E05C5/02—Fastening devices with bolts moving otherwise than only rectilinearly and only pivotally or rotatively both moving axially and turning about their axis to secure the wing
    • E—FIXED CONSTRUCTIONS
    • E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05C—BOLTS OR FASTENING DEVICES FOR WINGS, SPECIALLY FOR DOORS OR WINDOWS
    • E05C7/00—Fastening devices specially adapted for two wings
    • E05C7/02—Fastening devices specially adapted for two wings for wings which lie one behind the other when closed
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

IC memory devices include a memory cell array that is configured to output data bits in parallel at a first data transfer rate and an output circuit. The output circuit is configured to serially output the data bits to an external terminal at the first data transfer rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data transfer rate that is lower than the first data transfer rate in a test mode of operation. Accordingly, the memory cell array can operate at the first data transfer rate while allowing the output circuit to output data to an external terminal at the second data transfer rate that is lower than the first data transfer rate, in a test mode of operation.

Description

With integrated circuit memory devices and method of operating than the low velocity outputs data bits
The application requires the right of priority of the korean patent application NO.2003-0035906 that proposes on June 4th, 2003, so its disclosed content all is combined as reference here, just as its here by fully open.
Technical field
The present invention relates to integrated circuit memory devices and method of operating thereof, more specifically, relate to the circuit and the method that are used for the testing integrated circuits device.
Background technology
Integrated circuit memory devices is widely used in many commerce and user's application.A kind of integrated circuit memory devices that is widely used is exactly dynamic RAM (DRAM).Synchronous dram (SDRAM) device also designed to be able to rising edge of clock signal or negative edge synchronously reads and writes data.In addition, double data rate (DDR) (DDR) SDRAM device also be designed to rising edge by response clock signal and negative edge read and/or write data can be with the frequency operation higher than traditional SDRAM (being also referred to as single data rate (SDR) SDRAM).Those skilled in the art are understandable that, term " data transfer rate " is meant in a clock period, and storage arrangement can be to/the bit number that transmits from an outside I/O terminal.
The sequential chart that Fig. 1 compares for the operation to traditional SDR SDRAM and legacy ddr SDRAM.These two SDRAM comprise burst length (BL) that equals 4 and column address strobe (CAS) stand-by period (CL) that equals 2.Like this, as shown in Figure 1, for SDRRAM with BL=4 and CL=2, response sense command R and read 4 bit data Q0, Q1, Q2 and Q3, wherein each of data Q0-Q3 all is that the rising edge of response clock CLK is output.Similarly, response write command W, 4 bit data are along with the rising edge of clock CLK is sequentially imported.
On the contrary, also as shown in Figure 1, for DDR SDRAM, the data Q0-Q3 of storage is the rising edge of response data gating signal (DQS) and negative edge and exported from storage arrangement, and wherein this DQS itself generates according to clock signal clk.And, the response write command, therefore the rising edge of data D0-D3 response DQS and negative edge and be written in the storage arrangement so just can obtain to compare with SDR SDRAM the data transfer rate of twice.SDRAM Design of device and operation comprise SDRSDRAM device and DDR SDRAM device, all are that those skilled in the art are known, therefore need further not describe at this.
Because High Data Rate is difficult to test the high frequency memory device such as DDR SDRAM.Especially be difficult to use the testing apparatus (for example being designed to test the testing apparatus of SDR SDRAM) of relative low frequency to test high frequency memory device such as DDR SDRAM.For example, the U.S. Pat 5933379 (the assigned the application's of giving assignee) that is proposed by people such as Park has proposed a kind of " Method and Circuitfor Testing a Semiconductor Memory Device Operating at High Frequency ", annotates as the title of Park etc.Summary as people such as Park is annotated, and a kind of circuit that is used for the measuring semiconductor storage arrangement comprises the stand-by period controller that is used to control the external timing signal stand-by period, is used to generate the internal column address maker of storage arrangement column address signal and the mode register that is used for the generate pattern signal.This circuit that is used for the measuring semiconductor storage arrangement also comprises the column address decoder that is used for the OPADD signal of internal column address maker is decoded, be used to read or write the memory of data unit, be used for coming according to the output signal of stand-by period controller I/O control module, data input buffer and the data output buffer of the I/O of control store cell data.Also further provide to be used for generating and had " n " doubly to the frequency multiplier of the internal clock signal of the frequency of external timing signal.By above-mentioned improvement is provided, traditional testing apparatus can be used to test the high frequency memory device.
Described a kind of " SynchronousSemiconductor Memory Device Which Can Be Inpected Even With Low SpeedTester " by the United States Patent (USP) 6163490 that people such as Iwotomo propose, annotated as the title of Iwotomo etc.Summary as people such as Iwotomo is annotated, a kind of synchronous semiconductor memory device comprises respectively from corresponding to the preselected device that receives first and second data first and second memory cells of even summation odd address, and they is exported to data I/O terminal.This preselected device is in normal running, in the length of a clock period, first and second data are exported to successively data I/O terminal, determine in test pattern whether first and second data mate, and the result that will determine exports to data I/O terminal in the length of a clock period.
At last, described a kind of " SemiconductorMemory Device Input Circuit ", annotated as the title of Mader etc. by the United States Patent (USP) 6212113 that people such as Mader propose.Summary as people such as Mader is annotated, and discloses a kind of double data rate (DDR) (DDR) storage arrangement, and it can be configured in a normal memory tester that is used to test.This DDR storer can comprise DDR input circuit, single data rate input circuit, Word line control circuit, bit line control circuit and memory cell array.Can carry out normal write operation by selecting the DDR input circuit.Can test write operation by selecting the SDR input circuit.This design can so that the DDR storage arrangement can in common SDR memory tester, test.
Because the high frequency memory device can have relatively little effective data window edge, this edge may be caused by the processing variation in the device fabrillation line, therefore also is difficult to the high frequency memory device such as DDR SDRAM is tested.Therefore, even can use the high-frequency test equipment that is used for DDR SDRAM to test high-frequency device, in fact also be difficult to concurrently a plurality of DDR SDRAM devices be tested such as DDR SDRAM.
Summary of the invention
Some embodiments of the present invention provide integrated circuit memory devices, and this integrated circuit memory devices comprises the memory cell array that is configured to first data transfer rate and a plurality of data bit of line output.Output circuit is configured to export a plurality of data bit with first data transfer rate successively to exterior terminal in normal manipulation mode, and in test mode of operation, export a plurality of data bit successively to exterior terminal with second data transfer rate that is lower than first data transfer rate, wherein said output circuit be configured in first subpattern of test mode of operation with second data transfer rate that is lower than first data transfer rate to exterior terminal export successively from described memory cell array and a plurality of data bit of line output in first, and in second subpattern of test mode of operation with second data transfer rate that is lower than first data transfer rate to exterior terminal export successively from described memory cell array and a plurality of data bit of line output in second portion.In certain embodiments, this memory cell array response has the clock signal of rising edge and negative edge, wherein this first data transfer rate is that the rising edge and the negative edge of response clock signal simultaneously generates, and second data transfer rate is the rising edge of only response clock signal or a generation in the negative edge.In other embodiments, this memory cell array is configured to by corresponding a plurality of first data lines with first data transfer rate and a plurality of data bit of line output, and this output circuit is configured in normal manipulation mode by using corresponding a plurality of second data lines to export a plurality of data bit with first data transfer rate successively to exterior terminal, and in test mode of operation by using corresponding a plurality of second data lines to export a plurality of data bit successively to exterior terminal with second data transfer rate that is lower than first data transfer rate.
Therefore, some embodiments of the present invention can allow the memory cell array can be with first data transfer rate operation in test mode of operation, allow simultaneously output circuit with second data transfer rate that is lower than first data transfer rate to the exterior terminal output data.Therefore for example, can use SDR SDRAM testing apparatus to test DDR SDRAM and/or because data window has been exaggerated concurrent testing DDR SDRAM device on SDR SDRAM testing apparatus.
More specifically, in certain embodiments, memory cell array is configured to by corresponding a plurality of first data lines with first data transfer rate and a plurality of data bit of line output, and this output circuit comprises multiplexer and output buffer, this multiplexer is configured to give corresponding a plurality of second data lines with the sense data multiplex on first data line, and this output buffer is configured to the data on second data line are outputed to exterior terminal successively.
In certain embodiments, multiplexer is configured in normal manipulation mode each first data line is coupled to each second data line, in first subpattern of test mode of operation, each even number first data line is coupled to each even number second data line odd number second data line adjacent, and in second subpattern of test mode of operation, each odd number first data line is coupled to each odd number second data line even number second data line adjacent with each with each.Be understandable that term " even number " and " odd number " are used as expression data line alternately, and be used as the data line mark of represent data line and have nothing to do.In certain embodiments, this multiplexer comprises: first switch, and it is configured in first subpattern each even number first data line is coupled to each even number second data line; Second switch, it is configured in second subpattern each odd number first data line is coupled to each odd number second data line; And equalizing circuit, it is configured in first and second subpatterns each odd number second data line is coupled to each adjacent even number second data line.Mode register set also is provided, and it responds a plurality of command signals and is configured to generate first and second test mode signals, respectively multiplexer is placed first and second subpatterns of test mode of operation.
In other embodiments, this multiplexer is configured in normal manipulation mode each first data line is coupled to each second data line, in first subpattern of test mode of operation, each first data line is coupled to each second data line, and in second subpattern of test mode of operation, each odd and even number first data line cross-couplings is arrived each even number and odd number second data line.In these embodiments, this output buffer responds first internal clock signal and second internal clock signal in normal manipulation mode, in first and second subpatterns of test mode of operation, only respond in first internal clock signal or second internal clock signal, wherein the rising edge of this first internal clock signal response clock signal generates, and the negative edge of this second internal clock signal response clock signal generates.Be understandable that " rising " used herein is used to indicate the different edges of clock signal with " decline ", and can exchange mutually.
More specifically, in these embodiments, multiplexer can comprise: first switch, and it is configured in the normal manipulation mode and first subpattern each first data line is coupled to each second data line; And second switch, it is configured in second subpattern each odd and even number first data line cross-couplings be arrived each even number and odd number second data line.Also in certain embodiments, this output buffer comprises corresponding a plurality of register, wherein each register is configured to store the data of reading from each first data line, and latch, it links to each other with each adjacent register pair, each latch all is configured to respond first internal clock signal and latchs data from first adjunct register, and responds second internal clock signal and latch data from second adjunct register.This output buffer can also comprise parallel-to-serial converter, and it responds the latch and first and second clock signals in normal manipulation mode, and only responds in first and second internal clock signals one during the subpatterns in first and second operations.
Still be in the embodiments of the invention, output circuit responds first internal clock signal and second internal clock signal in normal manipulation mode, wherein the rising edge of this first internal clock signal response clock signal generates, the negative edge of this second internal clock signal response clock signal generates, and output circuit alternately responds first internal clock signal and second internal clock signal in test mode of operation.More specifically, in certain embodiments, memory cell array is configured to comprise output buffer by corresponding a plurality of first data lines with first data transfer rate and a plurality of data bit of line output and output circuit that this output buffer is configured to exterior terminal output data successively.
In certain embodiments, output buffer responds first internal clock signal and second internal clock signal in normal manipulation mode, in the first operation subpattern of test mode of operation, only respond in first internal clock signal or second internal clock signal, and only respond in first internal clock signal or second internal clock signal another in the subpattern in second operation of test mode of operation, wherein the rising edge of this first internal clock signal response clock signal generates, and the negative edge of this second internal clock signal response clock signal generates.In certain embodiments, output buffer comprises: corresponding a plurality of registers, and wherein each register is configured to store the data of reading from each first data line; Latch, it links to each other with each adjacent register pair, and each latch all is configured to respond first internal clock signal and latchs data from first adjunct register, and responds second internal clock signal and latch data from second adjunct register.Parallel-to-serial converter responds the latch and first and second internal clock signals in normal manipulation mode, in the first operation subpattern, only respond in first and second internal clock signals, and in the second operation subpattern, only respond in first and second internal clock signals another.
Still be according to other embodiments of the invention, this output circuit responds first internal clock signal and second internal clock signal in normal manipulation mode, and in test mode of operation, respond by first internal clock signal behind each frequency division of first internal clock signal generation with by second internal clock signal behind the frequency division of second internal clock signal generation, wherein the rising edge of this first internal clock signal response clock signal generates, and the negative edge of this second internal clock signal response clock signal generates.More specifically, in certain embodiments, this output buffer responds first internal clock signal and second internal clock signal in normal manipulation mode, and first internal clock signal in test mode of operation behind each frequency division of response and second internal clock signal behind the frequency division, wherein the rising edge of this first internal clock signal response clock signal generates, and the negative edge of this second internal clock signal response clock signal generates.In certain embodiments, the frequency of first internal clock signal behind the frequency division and second internal clock signal behind the frequency division is respectively half of frequency of first internal clock signal and second internal clock signal.
And, first frequency dividing circuit also is provided, it is configured to the rising edge of response clock signal and test mode select signal and first internal clock signal after generating frequency division.Second frequency dividing circuit can be provided, and it is configured to the negative edge of response clock signal and test mode select signal and generates first internal clock signal.In certain embodiments, first frequency dividing circuit comprises the rising edge of response clock signal and first frequency divider of test mode signal.Second frequency dividing circuit comprises second frequency divider of the negative edge of response clock signal and test mode signal and responds the delay element of second frequency divider.
Other embodiments of the invention provide a kind of method of operating of integrated circuit memory devices, and wherein this integrated circuit memory devices has the memory cell array that is configured to first data transfer rate and a plurality of data bit of line output.According to some embodiments of the present invention, in normal manipulation mode, export a plurality of data bit from described memory cell array successively to exterior terminal with first data transfer rate.In test mode of operation, export a plurality of data bit from described memory cell array successively to exterior terminal with second data transfer rate that is lower than first data transfer rate.Wherein successively exporting a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate in test mode of operation comprises: first subpattern of test mode of operation, successively export first a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate; And in second subpattern of test mode of operation, export two parts a plurality of data bit from memory cell array successively to exterior terminal with second data transfer rate that is lower than first data transfer rate.In method according to an embodiment of the invention, also can provide some be similar to above the embodiment of described embodiment.
Description of drawings
Fig. 1 is the sequential chart of the operation undertaken by traditional double data transfer rate and single data rate storage arrangement.
Fig. 2 is according to the integrated circuit memory devices of the embodiment of the invention and the block scheme of method of operating.
Fig. 3 be according to other embodiments of the present invention integrated circuit memory devices and the block scheme of method of operating.
Fig. 4 is the synoptic diagram that can use multiplexer in the embodiments of figure 3 according to other embodiments of the present invention.
Fig. 5 and 6 is the sequential chart according to the operation that can carry out in the embodiment of Fig. 3 and 4 of different embodiments of the invention.
Fig. 7 be according to other embodiments of the present invention integrated circuit memory devices and the block scheme of method of operating.
Fig. 8 is the synoptic diagram of the multiplexer among the embodiment that can be used in Fig. 7 according to other embodiments of the present invention.
Fig. 9 is the synoptic diagram of the output buffer among the embodiment that can be used in Fig. 7 according to other embodiments of the present invention.
Figure 10 is the sequential chart of the operation that can carry out in the embodiment of Fig. 7-9 according to other embodiments of the present invention.
Figure 11 be according to other embodiments of the present invention integrated circuit memory devices and the block scheme of method of operating.
Figure 12 is the synoptic diagram of the output buffer among the embodiment that can be used in Figure 11 according to other embodiments of the present invention.
Figure 13 is the sequential chart among the embodiment that can be used in Figure 11 and 12 according to other embodiments of the present invention.
Figure 14 be according to other embodiments of the present invention integrated circuit (IC) apparatus and the block scheme of method of operating.
Figure 15 A and 15B are for dividing the block scheme of the divider circuit among the embodiment that can be used in Figure 14 according to other embodiments of the present invention.
Figure 16 is for dividing the sequential chart of the operation that can carry out according to other embodiments of the present invention in the embodiment of Figure 14,15A and 15B.
Figure 17 is the process flow diagram according to the operation that can carry out of different embodiments of the invention.
Embodiment
Below with reference to accompanying drawings the present invention is illustrated more fully embodiments of the invention shown in the drawings., the present invention can have the different form of many kinds, and is not limited only to specific embodiment described here.More properly, provide these embodiment it will be apparent to one skilled in the art that, can be so that disclosed content more comprehensively and complete, and have given full expression to scope of the present invention.In the accompanying drawings, for the sake of clarity, the size and the relative size of parts have been exaggerated.And, describe here and each embodiment of illustrating also comprises its complementary conductivity type embodiment.Identical Reference numeral is represented identical parts in full.
Fig. 2 is according to the integrated memory devices of different embodiments of the invention and the block scheme of method of operating.As shown in Figure 2, integrated circuit memory devices 200 comprises memory cell array 211, and it is configured to the first data transfer rate DR1 and a plurality of data bit of line output.The design of memory cell array 211 it will be apparent to one skilled in the art that to be known and not to need here to be described in detail.
Still referring to Fig. 2, output circuit 213 is configured under normal manipulation mode, export a plurality of data bit with the first data transfer rate DR1 successively to exterior terminal 217, and under test mode of operation, export a plurality of data bit successively to exterior terminal 217 with the second data transfer rate DR2 lower than first data transfer rate.In other words, as shown in Figure 2, DR2 is less than DR1.Those skilled in the art are understandable that, in some embodiments of the invention, can comprise a plurality of memory cell arrays 211, a plurality of output circuit 213 and/or a plurality of exterior terminal 217 in single integrated circuit storage arrangement 200.And the functional and circuit diagram of output circuit 213 can be repeated by each memory cell 211 and/or exterior terminal 217, and/or also can be total by a plurality of memory cell arrays 211 and/or exterior terminal 217 at least in part.
Still referring to Fig. 2, in some embodiments of the invention, memory cell array 211 is configured to by corresponding many first data lines 212 with the first data transfer rate DR1 and a plurality of data bit of line output.Like this, for each from memory cell array and the position of line output one first data line 212 all arranged.And, in certain embodiments, under normal manipulation mode, output circuit 213 is configured to use in the output circuit 213 corresponding a plurality of second data lines 214 to export a plurality of data bit with first data transfer rate successively to exterior terminal 217, and under test mode of operation, corresponding a plurality of second data lines 214 are exported a plurality of data bit with the second data transfer rate DR2 lower than the first data transfer rate DR1 successively to exterior terminal 217 in the use output circuit.Like this, for example, just can use four first data lines 212 and four second data lines 214.
Fig. 3 be according to some embodiments of the invention integrated circuit memory devices and the block scheme of method of operating.Usually, referring to Fig. 3, output circuit 313 is configured to repetition by in the memory cell array 211 and the first of a plurality of data bit of line output, so that the first that exports a plurality of data bit successively to exterior terminal 217 with second data transfer rate lower than first data transfer rate under test mode of operation.This output circuit 313 also can be configured to repetition by in the memory cell array 211 and the second portion of a plurality of data bit of line output, so that export the second portion of a plurality of data bit successively to exterior terminal with second data transfer rate lower than first data transfer rate under test mode of operation.
More specifically, as shown in Figure 3, memory cell array 211 is configured to by corresponding many first data lines 212 with first data transfer rate and a plurality of data bit of line output.In Fig. 3, first data line 212 is identified as RDIO_0-RDIO_3., also can adopt still less in other embodiments or first data line 212 of greater number.And, as shown in Figure 3, output circuit 313 comprises multiplexer 313a, and this multiplexer 313a is configured to read on first data line 212 data multiplex is sent to corresponding a plurality of second data lines 214, and it is identified as DO_0-DO_3 in Fig. 3.This output circuit 313 also comprises output buffer 313b, and this output buffer 313b is configured to export the data on the second data line DO_0-DO_3 to exterior terminal 217 successively.Equally, only show four second data lines 214 among Fig. 3.But, can adopt still less or second data line of greater number.
More specifically, as shown in Figure 3, multiplexer 313 is configured in normal manipulation mode each first data line 212 is coupled to each second data line 214, as multiplexer 313a top 1/3rd shown in; In first subpattern of test mode of operation, each even number first data line is coupled to each even number second data line and each adjacent odd number second data line, also is known as test pattern 1 also shown in the centre 1/3rd of multiplexer 313a; In second subpattern of test mode of operation, each odd number first data line is coupled to each odd number second data line and each neighbouring even-numbered second data line, also be known as test pattern 2 and as multiplexer 313a following 1/3rd shown in.Will also be appreciated that the test pattern that also can support more than two.
Therefore, as shown in Figure 3, in normal manipulation mode, the first data line RDIO is coupled to the second corresponding data line DO, so as with first data transfer rate for example DDR SDRAM data transfer rate provide output from output buffer 313.During first test pattern or first subpattern, data from even number first data line RDIO_0 and RDIO_2 are repeated on the odd and even number second data line DO_0-DO_3, thereby these data are offered output buffer 313b with the form that is repeated, and therefore with than low second data transfer rate of first data transfer rate for example SDR SDRAM data transfer rate export exterior terminal 217 to.At last, in second test pattern or second subpattern, the data of odd number first data line RDIO_1 and RDIO_3 are repeated on the odd and even number second data line DO_0-DO_3, and therefore with second data transfer rate lower than first data transfer rate these data are offered output buffer 313b.In test pattern, and to be compared by the data window of the data of reading from memory cell array 211, the data window of the output data DOUT of output buffer 313b is exaggerated and is doubled in certain embodiments.Because data window has been exaggerated, therefore can use DDR SDRAM testing apparatus and/or many SDR SDRAM testing apparatus that DDRSDRAM is tested.
Still referring to Fig. 3, mode register set (MRS) the 315 a plurality of command signals of response also are configured to generate the first and second test mode signal TM1, TM2, thereby respectively multiplexer 313a are placed first and second subpatterns of test mode of operation.This command signal can comprise rwo address strobe signals (RASB), column address gating signal (CASB), write enable signal (WEB) and address signal.According to some embodiments of the invention, because MRS 315 is provided in integrated circuit memory devices 300, therefore can after encapsulation, test.
The synoptic diagram of the multiplexer 313 that can provide according to some embodiments of the present invention, for example the multiplexer 313a of Fig. 3 are provided Fig. 4.As shown in Figure 4, multiplexer 313a comprises first switch 420, and it is configured in first subpattern (TM1) each even number first data line RDIO_0, RDIO_2 are coupled to each even number second data line DO_0, DO_2.Second switch 430 is configured in second subpattern (TM2) each odd number first data line RDIO_1, RDIO_3 are coupled to each odd number second data line DO_1, DO_3.Equalizing circuit 440 is configured in first and second subpatterns each odd number second data line DO_1, DO_3 are coupled to each adjacent even number second data line DO_0, DO_2.Therefore, as shown in Figure 4, for responding first test mode signal (TM1), send the first sense data RDIO_0, the RDIO_2 that from memory cell array 211, generate on first data line 212 on second data line 214 the second sense data DO_0, DO_2 respectively.Simultaneously, this equalizing circuit 440 is activated, so that when the second switch 430 that receives second test mode signal (TM2) was released, (DO_0/1 DO_2/3) can remain on identical level to every antithesis/strange second sense data.Can similarly handle this odd number sense data RDIO_1, RDIO_3, make the effective data window of output data DOUT be amplified to the twice of normal mode.In normal mode, this equalizing circuit 440 is released.
Fig. 5 be according to some embodiments of the invention, from the storage arrangement described in for example Fig. 3 and 4 sequential chart of the normal and test pattern of the operation of sense data.As shown in Figure 5, in normal mode, the rising edge and the negative edge of response clock signal (CLK) send the data DO-D3 that reads to exterior terminal DOUT with effective data window W1.And, also as shown in Figure 5, in test pattern, the response external rising edge of clock signal, (DO_0/2 DO_1/3) sends exterior terminal DOUT respectively to even number and odd data with the data window W2 that amplifies.
Fig. 6 is the more detailed sequential chart of the operation carried out according to various embodiments of the invention, by the described output circuit of for example Fig. 3-5.As shown in Figure 6, the rising edge of response clock signal CLK generates the first internal clock signal CDQ_F.The negative edge of response clock signal CLK generates the second internal clock signal CDQ_S.In normal mode, the response and the rising edge and the consistent CDQ_F and the CDQ_S signal of negative edge of clock signal clk send output data DO-D3 to exterior terminal DOUT.In test pattern 1,, therefore send output data DO and D2 to exterior terminal DOUT with the data window that amplifies because the odd and even number data are maintained on the identical level.Also in test pattern 2, provide similar operation to output data D1 and D3.
Those skilled in the art are understandable that, the output DOUT in test pattern 1 and the test pattern 2 generally appears at each other offset clocks in the cycle, rather than in identical or overlapping clock period as illustrated in Figures 5 and 6.The overlapping clock period has been shown among Fig. 5 and 6, therefore can have compared, so that can further not amplify the width of sequential chart to normal and test pattern.
Fig. 7-10 has illustrated integrated circuit memory devices and method of operating according to other embodiments of the present invention.Usually, in these embodiments, the memory cell array response has the clock signal of rising edge and negative edge.In normal manipulation mode, output circuit responds first internal clock signal and second internal clock signal, wherein the rising edge of this first clock signal response clock signal generates, and the negative edge of this second clock signal response clock signal generates.But in test mode of operation, output circuit only responds in first internal clock signal or second internal clock signal.Therefore, in test mode of operation, can be with the second data transfer rate outputs data bits lower than first data transfer rate.
More specifically, referring to Fig. 7, in these embodiments, output circuit 733 comprises multiplexer 733a, this multiplexer 733a is configured in normal manipulation mode each first data line 212 is coupled to each second data line 214, as multiplexer 733a top 1/3rd shown in.In first subpattern of test mode of operation, in Fig. 7, also be known as in the test pattern 1, each first data line 212 is coupled to each second data line, shown in the centre 1/3rd of multiplexer 313a.At last, second subpattern of test mode of operation, in Fig. 7, also be known as in the test pattern 2, with each even number and odd number first data line 212 cross-couplings to each even number and odd number second data line 214, as multiplexer 313a following 1/3rd shown in.
Then Fig. 7 is described, also comprise output buffer 733b in the output circuit 733.In normal manipulation mode, output buffer 733b responds the first internal clock signal CDQ_F and the second internal clock signal CDQ_S, wherein the rising edge of this first clock signal C DQ_F response clock signal generates, and the negative edge of this second clock signal CDQ_S response clock signal generates.In test mode of operation, and especially in first and second subpatterns of test mode of operation, output buffer 733b only responds in first internal clock signal or second internal clock signal.In certain embodiments, as shown in Figure 7, in test mode of operation, output buffer only responds the first internal clock signal CDQ_F, and the second internal clock signal CDQ_S is disabled in first and second subpatterns of test mode of operation.
Therefore, how Fig. 7 illustrated in test pattern by forbidding second clock signal CDQ_S the effective data window of the output data DOUT of output buffer 733b be enlarged into a predetermined value, for example be the twice of the effective data window of the sense data RDIO_0-RDIO_3 that exports from memory cell array 211.Like this, output buffer 733b just can not operated by the second internal clock signal CDQ_S, so sense data DO_0-DO_3 just can be output to exterior terminal 217 with the effective data window that amplifies.
Fig. 8 is multiplexer embodiment according to the embodiments of the invention, for example the synoptic diagram of the multiplexer 733a of Fig. 7.As shown in Figure 8, this multiplexer comprises first switch 820, and this first switch is configured in normal mode and first subpattern (TM1) each first data line RDIO_0-RDIO_3 is coupled to each second data line DO_0-DO_3.Second switch 830 is configured in second subpattern (TM2) each odd and even number first data line cross-couplings be arrived each even number and odd number second data line.Therefore, respond first test mode signal (TM1), first sense data (RDIO_0-RDIO_3) that generates from memory cell array on first data line 212 is transferred to second data line 214 (DO_0-DO_3) respectively.Also have, respond second test mode signal (TM2), with first sense data (RDIO_0-RDIO_3) that from memory cell 211, generates on each first data line 212 be transferred to respectively the second adjacent data line 214 (DO_1/DO_0, DO_3/DO_2).
Fig. 9 is an output buffer according to the embodiments of the invention, for example the synoptic diagram of the output buffer 733b of Fig. 7.More specifically, as shown in Figure 9, output buffer 733b comprises corresponding a plurality of register 910a-910d, and each register is configured to store the data of reading from each first data line 212.Latch 920a, 920b link to each other with each adjacent register pair 910a/910b, 910c/910d.Each latch 920a-920b is configured to respond first internal clock signal (1 StF CLK, 2 NdF CLK) latchs data, and respond second internal clock signal (1 from first adjunct register StS CLK, 2 NdS CLK) latchs data from second adjunct register.Parallel-to-serial converter comprises multiplexer 930, response latch 920a, 920b and first and second internal clock signals in normal manipulation mode.This multiplexer 930 only responds in first and second internal clock signals during the first and second operation subpatterns.
In more detail, response internal clock signal INTCLK, the second second sense data DO_0-DO_3 that reads on the data line 214 is given register 910-910d by parallel transfer.In normal manipulation mode, response first is risen and the first decline clock (1 StF CLK, 1 StS CLK) appearance is stored in top two the register 910a of Fig. 9 and data DO_0 and the DO_1 among the 910b and is transferred to the first latch 920a successively, and responds the appearance (2 of second rising and the second decline clock NdF CLK, 2 NdS CLK), be stored in following two the register 910c of Fig. 9 and data DO_2 and the DO_3 among the 910d and be transferred to the second latch 920b successively.Like this, (CDQ_F, CDQ_S), each data DO_0-DO_3 is exported to exterior terminal 217 to respond first and second internal clock signals that activated successively in normal manipulation mode.But, in test mode of operation, rise and the first decline clock (1 even respond first StFCLK, 1 StS CLK) appearance, be stored in top two the register 910a of Fig. 9 and data DO_0 and the DO_1 among the 910b and be transferred to the first latch 920a successively, also have only data DO_0 to be given exterior terminal 217 with second data rate transmission lower than first data transfer rate, this is owing to have only the first internal clocking CDQ_F to be activated.And, rise and the second decline clock (2 though respond second NdF CLK, 2 NdS CLK) appearance, the data DO_2 and the DO_3 that are stored among following two register 910c and the 910d also are transferred to the second latch 920b successively, but also have only data DO_2 to be given exterior terminal 217 with second data rate transmission lower than first data transfer rate of normal manipulation mode.That is to say that data DO_0 is output, be transfused to up to the next one rising clock (CDQ_F) that is used for data DO_2.Like this, the active data window just has been exaggerated.Each first sense data RDIO_1,3 also is transferred to the second sense data DO_0,2 in second test pattern (TM2).Then, send data DO_0,2 to exterior terminal 217 with the data window that amplifies.Like this, all data RDIO_0-RDIO_3 just can (TM1 be outwards exported in TM2) at two kinds of test patterns.Fig. 9 also illustrates the logical circuit 940 that can be used to forbid decline clock CDQ_S during first and second test patterns.
Figure 10 is during normal manipulation mode and test mode of operation, for example uses the embodiment of Fig. 7-9 to generate the sequential chart of output data.Shown in the first half of Figure 10, during normal manipulation mode, the output circuit 733 response first internal clock signal CDQ_F and the second internal clock signal CDQ_S ', with first data transfer rate a plurality of data bit D0-D3 are exported to exterior terminal successively, wherein the first internal clock signal CDQ_F is the rising edge generation of response clock signal CLK, and the second internal clock signal CDQ_S ' is that the negative edge of response clock signal CLK generates.During test pattern, shown in the latter half of Figure 10, output circuit 733 only responds one of first internal clock signal or second internal clock signal, and shown in here is the first internal clock signal CDQ_F.Shown in the latter half of Figure 10, during test pattern 1, in the data of one of the second data line DO_0 of even number and DO_2 by with second data transfer rate output less than first data transfer rate.Though in Figure 10, do not illustrate,, can in test pattern 2, carry out similar operation yet except the data on odd number second data line DO_1 and DO_3 are transmitted to the even number p-wire.Therefore, except data D1 and D3 are output, the operation during the test pattern 2 can with test pattern 1 in identical.
Figure 11-13 explanation integrated circuit memory devices and method of operating according to other embodiments of the present invention.As described below, in these embodiments, in normal manipulation mode, output circuit responds first internal clock signal and second internal clock signal, wherein first internal clock signal is the rising edge generation of response clock signal, and second internal clock signal is that the negative edge of response clock signal generates.In test mode of operation, output circuit can also alternately respond first internal clock signal and second internal clock signal.More specifically, referring to Figure 11, memory cell array 211 is configured to by corresponding many first data lines 212 with first data transfer rate and a plurality of data bit of line output.This output circuit comprises and being configured to exterior terminal output data output buffer 1143 successively.
More specifically, still referring to Figure 11, memory cell array 211 responses have the clock signal of rising edge and negative edge.During normal manipulation mode, the output buffer 1143 response first internal clock signal CDQ_F and the second internal clock signal CDQ_S, wherein the first internal clock signal CDQ_F is the rising edge generation of response clock signal CLK, and the second internal clock signal CDQ_S is that the negative edge of response clock signal CLK generates.In first subpattern of test pattern (TM1), output buffer 1143 only responds one of first internal clock signal or second internal clock signal, here the just first internal clock signal CDQ_F shown in.In second subpattern of test mode of operation (TM1), shown in the test pattern among Figure 11 2, output buffer 1143 only responds another in first internal clock signal or second internal clock signal, here as shown in figure 11 only respond the second internal clock signal CDQ_S.
Like this, in Figure 11, by alternately forbid each CDQ_F and CDQ_S in test pattern, the effective data window of the output data DOUT of output buffer 1143 can be exaggerated.In certain embodiments, in second test pattern, forbid the first internal clock signal CDQ_F and in first test pattern, forbid the second internal clock signal CDQ_S.Like this, just can be with the window output sense data of amplifying.
Figure 12 is an output buffer according to some embodiments of the invention, for example the block scheme of the output buffer 1143 of Figure 11.As shown in figure 12, output buffer 1143 comprises corresponding a plurality of register 1210a-1210d, and each register is configured to store the data of reading from each first data line.Latch 1220a, 1220b link to each other with each adjacent register pair 1210a/1210b, 1210c/1210d.Latch 1220a is configured to respond first and rises and the first decline clock signal (1 StF CLK, 1 StS CLK) latch data, and latch 1220b also is configured to respond second and rises and the second decline clock signal (2 from the first adjunct register 1210a, 1210b NdF CLK, 2 NdS CLK) latchs data from the second adjunct register 1210c, 1210d.Parallel-to-serial converter 1230 responds latch 1220a, 1220b and the first and second internal clock signal CDQ_F, CDQ_S in normal manipulation mode, in the first test operation subpattern, only respond one of first and second internal clock signals, CDQ_F for example, and in the second test operation subpattern, only respond in first and second internal clock signals another, for example CDQ_S.Figure 12 has also illustrated logical circuit 1240 and 1250, and this logical circuit can be configured to forbid the first clock signal C DQ_F respectively in second test pattern and forbidding second clock signal CDQ_S in first test pattern.
Figure 13 is according to these embodiment of the present invention, the sequential chart of the operation that can be carried out by the output circuit of for example Figure 11 and Figure 12.As Figure 13 top 1/3rd shown in, in normal mode, output circuit responds the first and second internal clock signal CDQ_F ', CDQ_S '.The rising edge of first internal clock signal CDQ_F (or CDQ_F ') the response clock signal CLK, the negative edge of second internal clock signal CDQ_S (or CDQ_S ') the response clock signal CLK.In first test pattern, shown in the centre among Figure 13 1/3rd, the disabled and output circuit of the second internal clock signal CDQ_S ' only responds the first internal clock signal CDQ_F '.In second test pattern, shown in following 1/3rd among Figure 13, output circuit only responds second internal clock signal (DQ_S ').Like this, as shown in figure 12, the data DO_0 and the DO_2 that are stored among register circuit 1210a, the 1210c respond the first and second rising clock signals (1 StF CLK, 2 NdF CLK) is transmitted to latch circuit 1220a and 1220b.Afterwards, data DO_0 is output, and till the rising next time of first internal clock signal (CDQ_F '), this moment, next DO_2 was output, and made effective data window be exaggerated.In test pattern 2, the data DO_1 and the DO_3 that are stored among register circuit 1210b, the 1210d respond the first and second decline clock signals (1 StS CLK, 2 NdS CLK) is transmitted to latch circuit 1220a and 1220b.Then, data DO_1 is output, and till the rising next time of second internal clock signal (CDQ_S '), this moment, data DO_3 was output.Like this, make the effective data window of odd data also be exaggerated.
Figure 14-16 has illustrated other integrated circuit (IC) apparatus and method of operating according to other embodiments of the present invention.Usually, in these embodiments, during normal manipulation mode, output circuit responds first internal clock signal and second internal clock signal, wherein this first internal clock signal rising edge that is response clock signal generate and second internal clock signal to be the negative edge of response clock signal generate.During test mode of operation, first internal clock signal behind the output circuit response frequency division and two internal clock signals behind the frequency division, wherein first internal clock signal behind this frequency division be by first internal clock signal generate and second internal clock signal behind the frequency division is generated by second internal clock signal.In certain embodiments, the frequency of first internal clock signal behind the frequency division and second internal clock signal behind the frequency division is half of frequency of first internal clock signal and second internal clock signal.
More specifically, as shown in figure 14, in some embodiments of the invention, the data that first-in first-out (FIFO) register 1460 can be used to store from first data line 212.During normal mode, output buffer 1463 responses first and second internal clock signals., in test pattern TM, first and second internal clock signals behind this output buffer response frequency division.Like this, in test pattern, clock frequency is just by frequency division, for example is original half.
Like this, in test pattern, just can be by each CDQ_F and CDQ_S signal are carried out the Validity Test window that frequency division amplifies the output data DOUT of output buffer 1463.That is, response test mode signal TM, the frequency of each internal clock signal CDQ_F and CDQ_S is become lower frequency by frequency division.This test mode signal can generate from the mode register set (MRS) that receives a plurality of command signals (RASB, CASB, WEB) and address signal.Therefore, during test pattern, can amplify the data window of output data.
Figure 15 A and 15B are the block scheme that can be used to the frequency dividing circuit of the internal clocking after clock generates frequency division internally during the test pattern according to other embodiments of the present invention.Especially, shown in Figure 15 A, the first frequency dividing circuit 1500a is configured to respond the first internal clock signal CDQ_F and test mode select signal TM and the first internal clock signal CDQ_F ' after generating frequency division.Shown in Figure 15 B, the second frequency dividing circuit 1500b is configured to respond the second internal clock signal CDQ_S and test mode select signal TM and the second internal clock signal CDQ_S ' after generating frequency division.
More specifically, shown in Figure 15 A, in certain embodiments, the first frequency dividing circuit 1500a comprises first frequency divider 1510, the rising edge and the test mode signal of this first frequency divider response clock signal.Also have, in certain embodiments, the second frequency dividing circuit 1500b comprises the negative edge of response clock signal and second frequency divider 1520 of test mode signal, and the delay element 1530 that responds second frequency divider 1520.In certain embodiments, this delay element 1530 can be used to increase the time interval between the rising edge of clock behind first and second frequency divisions, so that can be with the output data of the output of the effective data window after amplifying exterior terminal 217.
Figure 16 is the sequential chart according to the operation of the embodiment of Figure 14,15A and 15B.Referring to Figure 14,15A, 15B and 16, data RDIO_0-RDIO_3 is stored in the fifo register 1460, and then responds internal clock signal and be transmitted to output buffer 1463.Afterwards, in normal mode, shown in the first half of Figure 16, respond first and second internal clock signals (CDQ_F and CDQ_S), all data in the impact damper 1463 are outwards output all.Shown in the latter half of Figure 16, in test pattern, output buffer 1463 responds the first and second internal clock signal CDQ_F ' behind the frequency division and CDQ_S ' respectively and outwards exports sense data DO-D3, so the active data window is exaggerated.Like this, in these embodiments, output buffer can be operated with original half speed, and simultaneously memory cell array with normal mode similarly fully speed operate.
Figure 17 is the process flow diagram according to the operation that can be carried out by the integrated circuit memory devices with memory cell array of various embodiments of the invention, and wherein this memory cell array is configured to first data transfer rate and a plurality of data bit of line output.These operations can be undertaken by any embodiment among Fig. 2 recited above-16.As shown in figure 17, when when square 1710 is selected normal mode, then export a plurality of data bit successively to exterior terminal with first data transfer rate from memory cell array at square 1720.At square 1730, when selecting test pattern, then export a plurality of data bit to exterior terminal with second data transfer rate that is lower than first data transfer rate from memory cell array at square 1740.According to any embodiment of the invention described above, can use the embodiment of Fig. 2,3-6,7-10,11-13 and/or 14-16 to carry out these operations.
In drawing and description, a plurality of embodiment of the present invention is disclosed, though wherein adopted special term, they also only are used as general and descriptive explanation rather than the purpose in order to limit, scope of the present invention is illustrated by claims.

Claims (30)

1. integrated circuit (IC) apparatus comprises:
Memory cell array is configured to first data transfer rate and a plurality of data bit of line output; And
Output circuit is configured to export a plurality of data bit with first data transfer rate successively to exterior terminal, and in test mode of operation, export a plurality of data bit with second data transfer rate that is lower than first data transfer rate successively to exterior terminal in the normal mode operation,
Wherein, described output circuit be configured in first subpattern of test mode of operation with second data transfer rate that is lower than first data transfer rate to exterior terminal export successively from described memory cell array and a plurality of data bit of line output in first, and in second subpattern of test mode of operation with second data transfer rate that is lower than first data transfer rate to exterior terminal export successively from described memory cell array and a plurality of data bit of line output in second portion.
2. according to the integrated circuit (IC) apparatus of claim 1, wherein said memory cell array response has the clock signal of rising edge and negative edge, the rising edge and the negative edge of the wherein said first data transfer rate response clock signal generate, and in wherein said second data transfer rate rising edge that is only response clock signal or the negative edge one and generate.
3. according to the integrated circuit (IC) apparatus of claim 1, wherein said memory cell array is configured to by corresponding a plurality of first data lines with first data transfer rate and a plurality of data bit of line output, and wherein said output circuit is configured to use in normal manipulation mode corresponding a plurality of second data lines to export a plurality of data bit with first data transfer rate successively to exterior terminal, and uses corresponding a plurality of second data lines to export a plurality of data bit with second data transfer rate that is lower than first data transfer rate successively to exterior terminal in test mode of operation.
4. according to the integrated circuit (IC) apparatus of claim 1, wherein said memory cell array response has the clock signal of rising edge and negative edge, wherein said output circuit responds first internal clock signal and second internal clock signal in normal manipulation mode, only respond in first internal clock signal or second internal clock signal one in test mode of operation, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates.
5. according to the integrated circuit (IC) apparatus of claim 1, wherein said memory cell array response has the clock signal of rising edge and negative edge, wherein said output circuit responds first internal clock signal and second internal clock signal in normal manipulation mode, in test mode of operation, alternately respond first internal clock signal and second internal clock signal, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates.
6. according to the integrated circuit (IC) apparatus of claim 1, wherein said memory cell array response has the clock signal of rising edge and negative edge, wherein said output circuit responds first internal clock signal and second internal clock signal in normal manipulation mode, first internal clock signal in test mode of operation behind the response frequency division and second internal clock signal behind the frequency division, the rising edge of the wherein said first internal clock signal response clock signal generates, the negative edge of the described second internal clock signal response clock signal generates, first internal clock signal behind the described frequency division is generated by first internal clock signal, and second internal clock signal behind the described frequency division is generated by second internal clock signal.
7. according to the integrated circuit (IC) apparatus of claim 1:
Wherein said memory cell array is configured to by corresponding a plurality of first data lines with first data transfer rate and a plurality of data bit of line output; And
Wherein said output circuit comprises multiplexer and output buffer, described multiplexer is configured to give corresponding a plurality of second data lines with the sense data multiplex on first data line, and described output buffer is configured to the data on second data line are outputed to exterior terminal successively.
8. according to the integrated circuit (IC) apparatus of claim 7:
Wherein said multiplexer is configured in normal manipulation mode each first data line is coupled to each second data line, in first subpattern of test mode of operation, each even number first data line is coupled to each even number second data line, and in second subpattern of test mode of operation, each odd number first data line is coupled to each odd number second data line.
9. according to the integrated circuit (IC) apparatus of claim 1:
Wherein said memory cell array is configured to by corresponding a plurality of first data lines with first data transfer rate and a plurality of data bit of line output; And
Wherein said memory cell comprises the output buffer that is configured to exterior terminal output data successively.
10. according to the integrated circuit (IC) apparatus of claim 9, wherein said memory cell array response has the clock signal of rising edge and negative edge, wherein said output buffer responds first internal clock signal and second internal clock signal in normal manipulation mode, in first subpattern of test mode of operation, only respond in first internal clock signal or second internal clock signal, in second subpattern of test mode of operation, only respond in first internal clock signal or second internal clock signal another, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates.
11. according to the integrated circuit (IC) apparatus of claim 10, wherein said output buffer comprises:
Corresponding a plurality of register, wherein each register is configured to store the data of reading from each first data line;
Latch, its register pair adjacent with each links to each other, and each latch all is configured to respond first clock signal and latchs data from first adjunct register, and response second clock signal latch is from the data of second adjunct register; And
Parallel-to-serial converter, it responds the latch and first and second internal clock signals in normal manipulation mode, and in the first operation subpattern, only respond in first and second internal clock signals, in the second operation subpattern, only respond in first and second internal clock signals another.
12. the integrated circuit (IC) apparatus according to claim 10 also comprises:
Mode register set, it responds a plurality of command signals and is configured to generate first and second test mode signals, so that output buffer is worked under first and second subpatterns of test mode of operation respectively.
13. integrated circuit (IC) apparatus according to claim 9, wherein said memory cell array response has the clock signal of rising edge and negative edge, wherein said output buffer responds first internal clock signal and second internal clock signal in normal manipulation mode, first internal clock signal in test mode of operation behind the response frequency division and second internal clock signal behind the frequency division, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates.
14. according to the integrated circuit (IC) apparatus of claim 13, first internal clock signal behind the wherein said frequency division and the frequency of second internal clock signal behind the described frequency division are respectively half of frequency of first internal clock signal and second internal clock signal.
15. the integrated circuit (IC) apparatus according to claim 13 also comprises:
Mode register set, it responds a plurality of command signals and is configured to generate test mode signal, so that output buffer is worked under test mode of operation.
16. the integrated circuit (IC) apparatus according to claim 13 also comprises:
First frequency dividing circuit, it is configured to the rising edge of response clock signal and test mode select signal and first internal clock signal after generating frequency division; And
Second frequency dividing circuit, it is configured to the negative edge of response clock signal and test mode select signal and second internal clock signal after generating frequency division.
17. integrated circuit (IC) apparatus according to claim 16:
Wherein first frequency dividing circuit comprises the rising edge of response clock signal and first frequency divider of test mode signal; And
Wherein second frequency dividing circuit comprises the negative edge of response clock signal and second frequency divider of test mode signal, and the delay element that is used to increase the time interval between the rising edge of first and second internal clockings behind the frequency division.
18. integrated circuit (IC) apparatus according to Claim 8 also comprises:
Mode register set, it responds a plurality of command signals and is configured to generate first and second test mode signals, respectively multiplexer is placed first and second subpatterns of test mode of operation.
19. an integrated circuit (IC) apparatus comprises:
Memory cell array, it is configured to by corresponding a plurality of first data lines with first data transfer rate and a plurality of data bit of line output;
Output circuit, it is configured to export a plurality of data bit with first data transfer rate successively to exterior terminal in normal manipulation mode, and in test mode of operation, export a plurality of data bit successively to exterior terminal with second data transfer rate that is lower than first data transfer rate, described output circuit comprises multiplexer and output buffer, described multiplexer is configured to give corresponding a plurality of second data lines with the sense data multiplex on first data line, and described output buffer is configured to the data on second data line are outputed to exterior terminal successively;
Mode register set, it responds a plurality of command signals and is configured to generate first and second test mode signals, respectively multiplexer is placed first and second subpatterns of test mode of operation;
Wherein said multiplexer is configured in normal manipulation mode each first data line is coupled to each second data line, in first subpattern of test mode of operation, each even number first data line is coupled to each even number second data line, and in second subpattern of test mode of operation, each odd number first data line is coupled to each odd number second data line, and comprise;
First switch, it is configured in first subpattern each even number first data line is coupled to each even number second data line;
Second switch, it is configured in second subpattern each odd number first data line is coupled to each odd number second data line; And
Equalizing circuit, it is configured in first and second subpatterns each odd number second data line is coupled to each adjacent last even number second data line.
20. an integrated circuit (IC) apparatus comprises:
Memory cell array, it is configured to by corresponding a plurality of first data lines with the parallel a plurality of data bit of output of first data transfer rate;
Output circuit, it is configured to export a plurality of data bit with first data transfer rate successively to exterior terminal in normal manipulation mode, and in test mode of operation, export a plurality of data bit successively to exterior terminal with second data transfer rate that is lower than first data transfer rate, described output circuit comprises multiplexer and output buffer, described multiplexer is configured to give corresponding a plurality of second data lines with the sense data multiplex on first data line, and described output buffer is configured to the data on second data line are outputed to exterior terminal successively;
Mode register set, it responds a plurality of command signals and is configured to generate first and second test mode signals, respectively multiplexer is placed first and second subpatterns of test mode of operation;
Wherein said multiplexer is configured in normal manipulation mode each first data line is coupled to each second data line, in first subpattern of test mode of operation, each first data line is coupled to each second data line, and in second subpattern of test mode of operation, each odd and even number first data line cross-couplings is arrived each even number and odd number second data line.
21. integrated circuit (IC) apparatus according to claim 20, wherein said memory cell array response has the clock signal of rising edge and negative edge, wherein said output buffer responds first internal clock signal and second internal clock signal in normal manipulation mode, when first and second subpatterns of test mode of operation, only respond in first internal clock signal or second internal clock signal, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates.
22. according to the integrated circuit (IC) apparatus of claim 20, wherein said multiplexer comprises:
First switch, it is configured in first subpattern each first data line is coupled to each second data line; And
Second switch, it is configured in second subpattern each odd and even number first data line cross-couplings be arrived each even number and odd number second data line.
23. according to the integrated circuit (IC) apparatus of claim 21, wherein said output buffer comprises:
Corresponding a plurality of register, each register wherein are configured to store the data of reading from each first data line;
Latch, its register pair adjacent with each links to each other, and each latch is configured to respond first clock signal and latchs data from first adjunct register, and response second clock signal latch is from the data of second adjunct register; And
Parallel-to-serial converter, it responds the latch and first and second internal clock signals in normal manipulation mode, and only responds in first and second internal clock signals one during the subpatterns in first and second operations.
24. a method of operating integrated circuit (IC) apparatus, wherein said integrated circuit (IC) apparatus have the memory cell array that is configured to first data transfer rate and a plurality of data bit of line output, described method comprises:
In normal manipulation mode, export a plurality of data bit from memory cell array successively to exterior terminal with first data transfer rate; And
In test mode of operation, export a plurality of data bit from memory cell array successively to exterior terminal with second data transfer rate that is lower than first data transfer rate,
Wherein, successively exporting a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate in test mode of operation comprises:
In first subpattern of test mode of operation, export first a plurality of data bit from memory cell array successively to exterior terminal with second data transfer rate that is lower than first data transfer rate; And
In second subpattern of test mode of operation, export two parts a plurality of data bit from memory cell array successively to exterior terminal with second data transfer rate that is lower than first data transfer rate.
25. method according to claim 24:
Wherein successively exporting a plurality of data bit from memory cell array to exterior terminal with first data transfer rate in normal manipulation mode comprises the rising edge of response clock signal and negative edge and successively export a plurality of data bit from memory cell array to exterior terminal with first data transfer rate normal manipulation mode; And
Wherein exporting a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate in test mode of operation comprises the rising edge of response clock signal only or the negative edge and successively export a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate in test mode of operation.
26. according to the method for claim 24,
Wherein said memory cell array response has the clock signal of rising edge and negative edge;
Wherein in normal manipulation mode, export a plurality of data bit from memory cell array successively to exterior terminal and comprise that response first internal clock signal and second internal clock signal successively export a plurality of data bit from memory cell array to exterior terminal with first data transfer rate with first data transfer rate, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates;
Wherein in test mode of operation, export a plurality of data bit from memory cell array successively to exterior terminal and comprise that only respond first internal clock signal and second internal clock signal one successively exports a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate with second data transfer rate that is lower than first data transfer rate.
27. according to the method for claim 24,
Wherein said memory cell array response has the clock signal of rising edge and negative edge;
Wherein in normal manipulation mode, export a plurality of data bit from memory cell array successively to exterior terminal and comprise that response first internal clock signal and second internal clock signal successively export a plurality of data bit from memory cell array to exterior terminal with first data transfer rate with first data transfer rate, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates;
Wherein successively exporting a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate in test mode of operation comprises and alternately responds first internal clock signal and second internal clock signal is successively exported a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate.
28. according to the method for claim 24,
Wherein said memory cell array response has the clock signal of rising edge and negative edge;
Wherein in normal manipulation mode, export a plurality of data bit from memory cell array successively to exterior terminal and comprise that response first internal clock signal and second internal clock signal successively export a plurality of data bit from memory cell array to exterior terminal with first data transfer rate with first data transfer rate, the rising edge of the wherein said first internal clock signal response clock signal generates, and the negative edge of the described second internal clock signal response clock signal generates;
Wherein in test mode of operation, export a plurality of data bit from memory cell array successively to exterior terminal and comprise that first internal clock signal and second internal clock signal behind the frequency division behind the response frequency division successively export a plurality of data bit from memory cell array to exterior terminal with second data transfer rate that is lower than first data transfer rate with second data transfer rate that is lower than first data transfer rate, wherein first internal clock signal behind the frequency division is generated by first internal clock signal, and second internal clock signal behind the frequency division is generated by second internal clock signal.
29. according to the method for claim 24,
Wherein said memory cell array is configured to be configured to export a plurality of data bit to outlet terminal by corresponding a plurality of second data lines with first data transfer rate and a plurality of data bit of line output and described memory cell by corresponding a plurality of first data lines;
Wherein successively exporting a plurality of data bit from memory cell array to exterior terminal with first data transfer rate in normal manipulation mode is included in the normal manipulation mode each first data line is coupled to each second data line; And
Wherein in test mode of operation, export a plurality of data bit from memory cell array successively to exterior terminal and be included in first subpattern of test mode of operation each even number first data line is coupled to each even number second data line, and in second subpattern of test mode of operation, each odd number first data line is coupled to each odd number second data line with second data transfer rate that is lower than first data transfer rate.
30. according to the method for claim 24,
Wherein said memory cell array is configured to be configured to export a plurality of data bit to outlet terminal by corresponding a plurality of second data lines with first data transfer rate and a plurality of data bit of line output and described memory cell by corresponding a plurality of first data lines;
Wherein successively exporting a plurality of data bit from memory cell array to exterior terminal with first data transfer rate in normal manipulation mode is included in the normal manipulation mode each first data line is coupled to each second data line; And
Wherein in test mode of operation, export a plurality of data bit from memory cell array successively to exterior terminal and be included in first subpattern of test mode of operation each first data line is coupled to each second data line with second data transfer rate that is lower than first data transfer rate, and in second subpattern of test mode of operation with each odd and even number first data line cross-couplings to each even number and odd number second data line.
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