JP2004362762A - Ic memory device and operating method that are configured to output data bit at low transfer rate in test mode of operation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IC memory device and an operation method that are configured to output data bits at a lower transfer rate in a test mode. <P>SOLUTION: IC memory devices include a memory cell array that is configured to output data bits in parallel at a first data transfer rate and an output circuit. The output circuit is configured to serially output the data bits to an external terminal at the first data transfer rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data transfer rate that is lower than the first data transfer rate in a test mode of operation. Accordingly, the memory cell array can operate at the first data transfer rate while allowing the output circuit to output data to an external terminal at the second data transfer rate that is lower than the first data transfer rate, in a test mode of operation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an IC memory device, and more particularly, to a circuit and a method for testing an IC memory device.

  IC memory devices are used in various application fields, and the most widely used memory device is a DRAM. A synchronous DRAM (Synchronous DRAM: SDRAM) is designed so that data can be written / read in synchronization with a rising edge or a falling edge of a clock signal. In particular, a dual data rate (DDR) SDRAM performs a conventional SDRAM (Single Data Rate (SDR)) by writing / reading data in response to both rising and falling edges of a clock signal. ) Designed to operate at higher frequencies (called SDRAM). Here, the "data transfer rate" means the number of bits transmitted to the external input / output terminal by the memory device or transmitted from the external input / output terminal to the inside of the memory device within one clock cycle.

  FIG. 1 is a timing chart for comparing the operation of a conventional SDR SDRAM with the operation of a conventional DDRS DRAM. Each of these SDRAMs has a 4-burst length (BL) and a 2-column address strobe latency (CAS (Column Address Strobe) Latency: CL). Therefore, as shown in FIG. 1, 4-bit data Q1 to Q3 are read in response to a read command R from an SDRAM in which BL is 4 and CL is 2, and each of data Q1 to Q3 is read. Bits are output in response to the rising edge of clock CLK. Similarly, 4-bit data is sequentially input in response to the rising edge of clock CLK in response to write command W.

  In contrast, as shown in FIG. 1, for a DDR SDRAM, stored data Q0 to Q3 are stored in memory in response to rising and falling edges of a data strobe signal (DQS: Data Strobe Signal). Output from the device. DQS is generated from the clock signal CLK. Also, data D0-D3 are written into the memory device in response to the rising and falling edges of DQS in response to a write command, thereby providing a two data transfer rate. The design and operation of SDRAMs, including SDR SDRAMs and DDR SDRAMs, are well known to those skilled in the art and will not be described in detail here.

  Due to the high data transfer rates, it may be difficult to test high frequency memory devices such as DDR SDRAM. Also, it is particularly difficult to test high frequency memory devices such as DDR SDRAM using low frequency test equipment designed to test SDR SDRAM. For example, Patent Document 1 discloses a test method and a test circuit ("Method and Circuit for Testing a Semiconductor Device Memory Operating at High Frequency") of a semiconductor memory device operating at a high frequency. As disclosed in Patent Document 1, a circuit for testing a semiconductor memory device includes a latency controller that controls the latency of an external clock signal, an internal column address generator that generates a column address signal, and a mode signal. It has a mode register to generate. The circuit for testing the semiconductor memory device may include a column address decoder for decoding an output address signal of the internal column address generator, a memory cell for storing data, and a memory cell for storing data in response to an output signal of the latency controller. An input / output control unit for controlling data input / output of the device and a data input / output buffer. Further, there is further provided a frequency integrator for generating an internal clock signal having a frequency corresponding to n times the frequency of the external clock signal. With the improvements described above, conventional test equipment can be used for testing high frequency memory devices.

  Patent Document 2 discloses a synchronous semiconductor memory device (“Synchronous semiconductor memory device while can be inspected even with low speed tester”) that can be tested by a low-speed tester. As disclosed in Patent Document 2, a synchronous semiconductor memory device includes a prefetch selector for receiving first and second data read from first and second memory cells corresponding to even and odd addresses, respectively. The prefetch selector sequentially outputs the first and second data to the data input / output terminal within one clock cycle during a normal operation. The prefetch selector determines whether the first and second data match in a test mode, and outputs the determination result to the data input / output terminal within one clock cycle.

  Finally, Patent Document 3 discloses an input circuit ("Semiconductor memory device input circuit") of a semiconductor memory device. Patent Document 3 discloses a DDR memory device configured to be able to be tested by a general memory test device. The DDR memory device includes a DDR input circuit, an SDR input circuit, a word line control circuit, a bit line control circuit, and a memory cell array. The normal write operation is performed by selecting the DDR input circuit, and the test write operation is performed by selecting the SDR input circuit. Such a configuration allows the DDR memory device to be tested with a common SDR memory test device.

Also, since high frequency memory devices have relatively small effective data window margins caused by manufacturing process changes, it is difficult to test high frequency memory devices such as DDR and SDRAM. Therefore, even if a high-frequency memory device such as a DDR SDRAM is tested by using the DDR SDRAM high-frequency test equipment, it is difficult to test a large number of DDR SDRAM devices in parallel.
U.S. Pat. No. 5,933,379 U.S. Pat. No. 6,163,491 U.S. Pat.No. 6,212,113

  A technical problem to be solved by the present invention is to provide a semiconductor memory device and an operation method for outputting data bits at a lower transfer rate in a test mode in order to extend an effective output data window in a test mode. .

  According to another aspect of the present invention, there is provided an IC memory device including a memory cell array configured to output a plurality of data bits in parallel at a first data transfer rate, and an output circuit. The output circuit outputs the plurality of data bits serially to an external terminal at the first data transfer rate in a normal mode, and outputs the plurality of data bits at a second data transfer rate lower than the first data transfer rate in a test mode. Are output in series to the external terminal.

  The memory cell array is responsive to a clock signal having rising and falling edges, and the first data transfer rate is generated in response to both rising and falling edges of the clock signal; The speed is generated in response to only one of the rising and falling edges of the clock signal. Further, the memory cell array is configured to output the plurality of data bits in parallel at the first data transfer rate on a corresponding plurality of first data lines, and the output circuit is configured to output the corresponding plurality of data bits in the normal mode. Outputting the plurality of data bits serially to the external terminal at the first data rate using a second data line, and in the test mode using the plurality of second data lines; The plurality of data bits are configured to be serially output to the external terminal at a transfer rate.

  The output circuit duplicates a first portion of the plurality of data bits in the test mode, and outputs the duplicated first portion in series to the external terminal at the second data transfer rate. A second portion of the bits is configured to be duplicated and the duplicated second portion is serially output to the external terminal at the second data rate. In particular, the memory cell array is configured to output the plurality of data bits in parallel on the corresponding plurality of first data lines at the first data rate, and the output circuit includes a corresponding plurality of second data lines. A multiplexer for multiplexing and outputting data read on the first data line and an output buffer for serially outputting data on the second data line to the external terminal;

  The multiplexer may connect each first data line to each second data line in the normal mode, and may connect each even-numbered first data line to each even-numbered data line in the first test mode of the test mode. A second data line is connected, and in the second test mode of the test mode, each odd-numbered first data line is connected to each odd-numbered second data line. The multiplexer further includes a first switch for connecting each even-numbered first data line to each even-numbered second data line in the first test mode, and a respective odd-numbered first data line in the second test mode. A second switch for connecting one data line to each odd-numbered second data line; and connecting each odd-numbered second data line to each adjacent even-numbered second data in the first and second test modes. And an equivalent circuit connected to the line. Also provided is a mode register set for generating first and second test mode signals in response to a plurality of command signals to place the multiplexer in the first and second test modes of the test mode.

  The multiplexer may connect each first data line to each second data line in the normal mode, and may connect each first data line to each second data line in the first test mode of the test mode. And in the second test mode of the test mode, each odd-numbered and even-numbered first data line is cross-connected to each even-numbered and odd-numbered second data line. In the normal mode, the output buffer is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal; The first and second test modes of the test mode respond to only one of the first and second internal clock signals.

  The multiplexer may further include a first switch for connecting each first data line to each second data line in the first test mode, and an odd-numbered and even-numbered first data in the second test mode. A second switch for cross-connecting the line to each of the even-numbered and odd-numbered second data lines. The output buffer is associated with a plurality of registers for storing read data on each of the first data lines, and a pair of adjacent registers, respectively, and outputs from the first adjacent register in response to a first clock signal. And a plurality of latches for latching data output from a second adjacent register in response to a second clock signal, and the first and second latches in the normal mode in response to the latch. A parallel-to-serial converter responsive to an internal clock signal and responsive to only one of the first and second internal clock signals during the first and second test modes.

  In the normal mode, the output circuit is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal; The test mode alternately responds to the first and second internal clock signals. In particular, the memory cell array outputs the plurality of data bits in parallel on the corresponding plurality of first data lines at the first data rate, and the output circuit outputs data in series to the external terminal. Is provided.

  In the normal mode, the output buffer is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal; In a first test mode of the test mode, only one of the first and second internal clock signals is responsive, and in a second test mode of the test mode, another of the first and second internal clock signals is used. Responds to only one of The output buffer is associated with a plurality of registers for storing read data on each of the first data lines, and a pair of adjacent registers, respectively. A plurality of latches are provided for latching output data and for latching data output from a second adjacent register in response to a second clock signal. And responding to the latch, responding to the first and second internal clock signals in the normal mode, and responding to only one of the first and second internal clock signals during the first test mode. A parallel-to-serial converter responsive to the second test mode and responsive to only one of the first and second internal clock signals may be further provided.

  In the normal mode, the output circuit is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal; The test mode is responsive to a divided first divided clock signal generated from the first internal clock signal and a divided second internal clock signal generated from the second internal clock signal. The frequency of the divided first and second internal clock signals is half of the frequency of the first and second internal clock signals, respectively.

  A first division circuit that generates the divided first internal clock signal in response to a rising edge of the clock signal and a test mode selection signal; and a first division circuit that responds to a falling edge of the clock signal and the test mode selection signal. A second division circuit for generating the divided second internal clock signal may be further provided. Also, the first divider circuit includes a first divider responsive to a rising edge of the clock signal and the test mode signal, and the second divider circuit responds to a falling edge of the clock signal and the test mode signal. A second divider and a second delay element responsive to the second divider.

  According to another aspect of the present invention, there is provided an IC memory device operating method for operating a semiconductor device having a memory cell array that outputs a plurality of data bits in parallel at a first data transfer rate. The plurality of data bits are serially output from the memory cell array to an external terminal at the first data rate in a normal mode. In the test mode, the plurality of data bits are serially output from the memory cell array to the external terminal at a second data rate lower than the first data rate.

  According to the IC memory device and the method of operating the same according to the present invention, the effective output data window in the test mode can be expanded by outputting data bits at a lower transfer rate in the test mode than in the normal mode.

  For a full understanding of the present invention, its operational advantages, and the objects achieved by the practice of the present invention, reference should be had to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the invention. There must be.

  Hereinafter, the present invention will be described in detail by explaining preferred embodiments of the present invention with reference to the accompanying drawings. The same reference numbers present in each drawing represent the same elements.

  FIG. 2 is a block diagram schematically illustrating a memory device and an operation method according to an embodiment of the present invention.

  As shown in FIG. 2, the memory device 200 includes a memory cell array 211 configured to output a plurality of data bits in parallel at a first data rate DR1. Since the design of the memory cell array 211 is known to those skilled in the art, a detailed description thereof will be omitted.

  Referring to FIG. 2, the output circuit 213 outputs the plurality of data bits in series to the external terminal 217 at the first data rate in the normal mode, and outputs the plurality of data bits to the external terminal 217 in the test mode. The plurality of data bits are configured to be serially output to the external terminal 217 at two data rates DR2. Meanwhile, it will be apparent to those skilled in the art that the plurality of memory cell arrays 211, the plurality of output circuits 213, and / or the plurality of external terminals 217 are provided in one memory device 200.

  The memory cell array 211 is configured to output a plurality of data bits in parallel on the corresponding plurality of first data lines 212 at a first data rate DR1. Therefore, one first data line 212 is allocated to each bit output in parallel from the memory cell array 211. The output circuit 213 outputs the plurality of data bits to the external terminal 217 at the first data rate in the normal mode using the corresponding plurality of second data lines 214, and outputs the plurality of data bits to the external terminal 217 in the test mode. The plurality of data bits are configured to be serially output to the external terminal 217 at the second data rate lower than the first data rate. For example, four first data lines 212 and four second data lines 214 are used.

  FIG. 3 is a block diagram illustrating a memory device and an operation method according to a first embodiment of the present invention.

  Referring to FIG. 3, the output circuit 313 duplicates the first part of the plurality of data bits output from the memory cell array 211 in parallel, so that, in the test mode, the external terminal 217 is at the second data rate. And outputting the first portion of the plurality of data bits in series. Also, the output circuit 313 duplicates the second portion of the plurality of data bits output from the memory cell array 211 in parallel, so that in the test mode, the plurality of data bits are output to the external terminal 217 at a second data transfer rate. The second portion of bits is configured to be output in series.

  In particular, as shown in FIG. 3, the memory cell array 211 is configured to output a plurality of data bits in parallel at a first data transfer rate on a corresponding plurality of first data lines 212. In FIG. 3, the first data lines 212 are denoted as RDIO_0 to RDIO_3. However, fewer or more first data lines 212 may be used. Also, as shown in FIG. 3, the output circuit 313 is configured to multiplex and output data read out on the first data line 212 onto a corresponding plurality of second data lines DO_0 to DO_3. 313a. The output circuit 313 also includes an output buffer 313b configured to output the data on the second data lines DO_0 to DO_3 to the external terminal 217 in series. Although only four second data lines 214 are shown in FIG. 3, fewer or more second data lines may be used.

  The multiplexer 313a is configured to connect each of the first data lines RDIO_0 to RDIO_3 to each of the second data lines DO_0 to DO_3 in a normal mode (＠NORMAL). In the first test mode (@TEST MODE1), the multiplexer 313a connects each even-numbered first data line RDIO_0, RDIO_2 to each even-numbered second data line DO_0, DO_2 and each adjacent odd-numbered second data line DO_2. It is connected to the data lines DO_1 and DO_3. In the second test mode (@TEST MODE2), the multiplexer 313a connects each odd-numbered first data line RDIO_1, RDIO_3 to each odd-numbered second data line DO_1, DO_3 and each adjacent even-numbered second data line. It is connected to data lines DO_0 and DO_2. Although only two test modes have been described here, it is clear that more test modes can be configured to be supported.

  Accordingly, in the normal mode, the first data lines RDIO_0 to RDIO_3 are connected to the corresponding second data lines DO_0 to DO_3 to output data from the output buffer 313 at a first data transfer speed corresponding to the data transfer speed of the DDR SDRAM. Is done. During the first test mode, the data of the even-numbered first data lines RDIO_0 and RDIO_2 are duplicated on the even-numbered and odd-numbered second data lines DO_0 to DO_3. Accordingly, the data is provided to the output buffer 313b in a duplicated form, and the data is output to the external terminal 217 at a second data transfer rate corresponding to the SDR / SDRAM data transfer rate. The second data rate is lower than the first data rate. Lastly, in the second test mode, the data of the odd-numbered first data lines RDIO_1 and RDIO_3 is duplicated on the odd-numbered and even-numbered second data lines DO_0 to DO_3, thereby transferring the data at the first data transfer rate. It is provided to output buffer 313b at a lower second data rate. Therefore, in the test mode, the data window of the output data DOUT of the output buffer 313b is expanded as compared with the data window of the data read from the memory cell array 211. Therefore, the DDR SDRAM is tested by the DDR SDRAM test equipment and / or multiple SDR SDRAM test equipment because the data window is expanded.

  A mode register set (MRS) 315 generates first and second test mode signals TM1 and TM2 for setting the multiplexer 313a to the first and second test modes in response to a plurality of command signals. The plurality of instruction signals include a row address strobe signal (RASB: Row Address Strobe Signal), a column address strobe signal (CASB: Column Address Strobe Signal), a write enable signal (WEB: Write Enable Signal), and an address. Since the MRS 315 is included in the memory device 300 according to an embodiment of the present invention, it may be tested after packaging.

  FIG. 4 is a circuit diagram of a multiplexer used in the embodiment of FIG.

  As shown in FIG. 4, the multiplexer 313a is configured to connect each even-numbered first data line RDIO_0, RDIO_2 to each even-numbered second data line DO_0, DO_2 in the first test mode TM1. The first switch 420 is provided. The second switch 430 is configured to connect the odd-numbered first data lines RDIO_1 and RDIO_3 to the respective odd-numbered second data lines DO_1 and DO_3 in the second test mode TM2. The equivalent circuit 440 is configured to connect each odd-numbered second data line DO_1 and DO_3 to each adjacent even-numbered second data line DO_0 and DO_2 in the first and second test modes.

  Therefore, the first read data RDIO_0 and RDIO_2 read from the memory cell array 211 onto the first data line 212 are converted into the second read data DO_0 and DO_2 on the second data line 214 in response to the first test mode signal TM1. Each is conveyed.

  At the same time, the equivalent circuit 440 is activated so that each pair of even / odd second read data (DO_0, DO_1) and (DO_2, DO_3) is maintained at the same level, while the second test mode signal The second switch 430 that receives TM2 is deactivated. The odd-numbered read data RDIO_1 and RDIO_3 are also processed as described above, and therefore, the valid data window of the output data DOUT is doubled as compared with the normal mode. In the normal mode, the equivalent circuit 440 is inactivated.

  FIG. 5 is a timing diagram of a normal mode and a test mode for reading data from the memory device according to the embodiment of FIGS.

  As shown in FIG. 5, the read data D0 to D3 in the normal mode are transmitted to the external terminal DOUT in response to the rising and falling edges of the clock signal CLK with a valid data window W1. Further, the even-numbered and odd-numbered data DO_0, DO_2, DO_1, DO_3 have the data window W2 extended in the test mode, and are transmitted to the external terminal DOUT in response to the rising edge of the external clock signal CLK.

  FIG. 6 is a detailed timing chart showing the operation performed by the output circuit according to the embodiment of FIGS.

  As shown in FIG. 6, the first internal clock signal CDQ_F is generated in response to a rising edge of the clock signal CLK. The second internal clock signal CDQ_S is generated in response to a falling edge of the clock signal CLK. In the normal mode, the output data D0 to D3 are transmitted to the external terminal DOUT in response to the first and second internal clock signals CDQ_F and CDQ_S corresponding to the rising and falling edges of the clock signal CLK. In the first test mode, the even data and the odd data are maintained at the same level, so that the output data D0 and D2 are transmitted to the external terminal DOUT with an extended data window. In the second test mode, a similar operation is provided for the output data D1 and D3.

  7 to 10 illustrate a memory device and an operation method according to a second embodiment of the present invention.

  In these embodiments, the memory cell array 211 responds to a clock signal CLK having rising and falling edges. The output circuit 733 responds to the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and the second internal clock signal CDQ_S generated in response to the falling edge of the clock signal in the normal mode.

  However, in the test mode, the output circuit is responsive to only one of the first internal clock signal or the second internal clock signal. Therefore, the data bits are output at a second data rate lower than the first data rate in the test mode.

  In particular, in this embodiment, the output circuit 733 includes a multiplexer 733a configured to couple each first data line 212 to each second data line 214 in a normal mode (＠NORMAL). In the first test mode (@TEST MODE1), each first data line 212 is connected to each second data line 214. Finally, in the second test mode (@TEST MODE2), each odd-numbered and even-numbered first data line 212 is cross-connected to each even-numbered and odd-numbered second data line 214.

  The output circuit 733 includes an output buffer 733b. The output buffer 733b responds to the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and the second internal clock signal CDQ_S generated in response to the falling edge of the clock signal CLK in the normal mode.

  In the test mode, that is, in the first and second test modes, the output buffer 733b is responsive to only one of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. In some embodiments, as shown in FIG. 7, the output buffer 733b responds only to the first internal clock signal CDQ_F in the test mode, and the second internal clock signal CDQ_S is disabled.

  Therefore, FIG. 7 shows how the valid data window of the output data DOUT of the output buffer 733b is extended by a predetermined value. Here, the effective data window of the output data DOUT is twice as large as the effective data window of the read data RDIO_0 to RDIO_3 output from the memory cell array 211 by disabling the second internal clock signal CDQ_S in the test mode. Become. Therefore, the output buffer 733b is not operated by the second internal clock signal CDQ_S such that the read data DO_0 to DO_3 have an extended valid data window and are output to the external terminal 217.

  FIG. 8 is a circuit diagram of a multiplexer used in the embodiment of FIG.

  As shown in FIG. 8, the multiplexer 733a is configured to connect each of the first data lines RDIO_0 to RDIO_3 to each of the second data lines DO_0 to DO_3 in the normal mode and the first test mode TM1. One switch 820 is provided. The second switch 830 is configured to cross-connect each odd-numbered and even-numbered first data line to each even-numbered and odd-numbered second data line in the second test mode TM2.

  Accordingly, the first read data RDIO_0 to RDIO_3 on the first data line 212 read from the memory cell array 211 are transmitted to the second data lines 214, DO_0 to DO_3 in response to the first test mode signal TM1. In addition, each of the first read data RDIO_0 to RDIO_3 on the first data line 212 read from the memory cell array 211 is adjacent to the second data line 214, DO_1, DO_0, DO_3 in response to the second test mode signal TM2. , DO_2.

  FIG. 9 is a circuit diagram of an output buffer used in the embodiment of FIG.

  As shown in FIG. 9, output buffer 733b includes a plurality of corresponding registers 910a-910d, each of which is configured to store read data on a respective first data line 212. Latch 920a is associated with two adjacent registers 910a and 910b, and latch 920b is associated with two adjacent registers 910c and 910d.

  Respective latches 920a and 920b latch data output from the first adjacent registers 910a and 910c in response to the first internal clock signals 1st FCLK and 2nd FCLK, and latch the second internal clock signals 1st SCLK and 2nd. It is configured to latch data output from the second adjacent registers 910b and 910d in response to SCLK. The parallel-to-serial converter comprising the multiplexer 930 is responsive to the latches 920a and 920b, and in normal mode is responsive to the first and second internal clock signals. Multiplexer 930 is responsive to only one of the first and second internal clock signals during the first and second test modes.

  More specifically, in the normal mode, the second read data DO_0 to DO_3 on the second data line 214 are transmitted to the registers 910a to 910d in parallel in response to the internal clock signal INTCLK. The data DO_0 and DO_1 stored in the registers 910a and 910b are sequentially transmitted to the first latch 920a in response to the generation of the first rising and first falling clocks 1st FCLK and 1st SCLK. Meanwhile, the data DO_2 and DO_3 stored in the registers 910c and 910d are sequentially transmitted to the second latch 920b in response to the generation of the second rising and second falling clocks 2nd FCLK and 2nd SCLK.

  Accordingly, the data DO_0 to DO_3 are output to the external terminal 217 in response to the first and second internal clock signals CDQ_F and CDQ_S which are sequentially activated in the normal mode.

  However, in the test mode, the data DO_0 and DO_1 stored in the two registers 910a and 910b are sequentially transmitted to the first latch 920a in response to generation of the first rising and first falling clocks 1st FCLK and 1st SCLK. However, since only the first internal clock signal CDQ_F is activated, only the data DO_0 is transmitted to the external terminal 217 at a second data transfer rate lower than the first data transfer rate. Even if the data DO_2 and DO_3 stored in the two registers 910c and 910d are sequentially transmitted to the second latch 920b in response to the generation of the second rising and second falling clocks 2nd FCLK and 2nd SCLK, Only DO_2 is transmitted to the external terminal 217 at a second data rate lower than the first data rate. That is, data DO_0 is output until the next rising clock CDQ_F for data DO_2 is input. Therefore, the valid data window is extended.

  The first read data RDIO_1 and RDIO_3 are transmitted to the second read data DO_0 and DO_2 in the second test mode TM2. Thereby, the data DO_0 and DO_2 are transmitted to the external terminal 217 with an extended data window. Therefore, in the two test modes TM1 and TM2, the data RDIO_1 to RDIO_3 are all output to the outside. FIG. 9 also shows a logic circuit 940 used to disable the falling clock CDQ_S during the first and second test modes TM1, TM2.

  FIG. 10 is a timing chart showing the generation of output data during the normal mode and the test mode in the embodiments of FIGS.

  As shown in FIG. 10, during the normal mode, the output circuit 733 generates the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and generates the output circuit 733 in response to the falling edge of the clock signal CLK. In response to the second internal clock signal CDQ_S, a plurality of data bits D0 to D3 are serially output to the external terminal 217 at the first data transfer rate.

  During the test mode, as shown in FIG. 10, the output circuit 733 responds to only one of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. Here, the case of responding to the first internal clock signal CDQ_F is illustrated. During the first test mode, data on the even-numbered second data lines DO_0 and DO_2 is output at a second data transfer rate lower than the first data transfer rate. Although not shown in FIG. 10, the same operation is performed in the second test mode except that data on the odd-numbered second data lines DO_1 and DO_3 is transmitted to the even-numbered test lines. Therefore, except that data D1 and D3 are output, the operation in the second test mode is the same as the operation in the first test mode.

  11 to 13 show a memory device and an operation method according to a third embodiment of the present invention.

  In this embodiment, the output circuit includes the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and the second internal clock signal generated in response to the falling edge of the clock signal CLK in the normal operation mode. Responds to CDQ_S. The output circuit alternately responds to the first internal clock signal and the second internal clock signal in the test mode.

  In particular, referring to FIG. 11, the memory cell array 211 is configured to output a plurality of data bits in parallel on a corresponding plurality of first data lines 212 at a first data transfer rate. The output circuit includes an output buffer 1143 configured to output data to the external terminal 217 in series.

  In particular, referring to FIG. 11, the memory cell array 211 responds to a clock signal having rising and falling edges. The output buffer 1143 receives the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and the second internal clock signal CDQ_S generated in response to the falling edge of the clock signal CLK during the normal mode. respond.

  In the first test mode TM1, the output buffer 1143 responds to only one of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. Here, a case where the response is to the first internal clock signal CDQ_F is shown. In the second test mode TM2, the output buffer 1143 responds only to another one of the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. Here, a case where the response is to the second internal clock signal CDQ_S is shown.

  Therefore, in FIG. 11, the valid data window of the output data DOUT of the output buffer 1143 is extended in the test mode by alternately disabling the first internal clock signal CDQ_F and the second internal clock signal CDQ_S. In this embodiment, the first internal clock signal CDQ_F is disabled in the second test mode, and the second internal clock signal CDQ_S is disabled in the first test mode. Therefore, the read data is output with the expanded window.

  FIG. 12 is a circuit diagram of the output buffer of FIG.

  As shown in FIG. 12, the output buffer 1143 includes a plurality of registers 1210a to 1210d configured to store read data on the first data line. Latch 1220a is associated with two adjacent registers 1210a and 1210b, and latch 1220b is associated with two adjacent registers 1210c and 1210d. The latch 1220a is configured to latch data output from the first adjacent registers 1210a and 1210b in response to the first rising and first falling clock signals 1st FCLK and 1st SCLK. The latch 1220b is configured to latch data output from the second adjacent registers 1210c and 1210d in response to the second rising and second falling clock signals 2nd FCLK and 2nd SCLK.

  In the normal mode, the parallel-to-serial converter 1230 responds to the latches 1220a and 1220b and responds to the first and second internal clock signals CDQ_F and CDQ_S. The parallel-to-serial converter 1230 responds to only one of the first and second internal clock signals during the first test mode TM1, and outputs the first and second internal clock signals during the second test mode TM2. Respond only to the other one. FIG. 12 shows logic circuits 1230 and 1250 configured to disable the first internal clock signal CDQ_F in the second test mode and to disable the second internal clock signal CDQ_S in the first test mode. I have.

  FIG. 13 is a timing chart performed in the embodiment of FIGS.

  As shown in FIG. 13, in the normal mode, the output circuit responds to the first and second internal clock signals CDQ_F 'and CDQ_S'. The first internal clock signal CDQ_F or CDQ_F 'responds to a rising edge of the clock signal CLK, and the second internal clock signal CDQ_S or CDQ_S' responds to a falling edge of the clock signal CLK.

  In the first test mode, the second internal clock signal CDQ_S 'is disabled, and the output circuit responds only to the first internal clock signal CDQ_F'. In the second test mode, the output circuit responds only to the second internal clock signal CDQ_S '. Therefore, as shown in FIG. 12, the data DQ_0 and DQ_2 stored in the registers 1210a and 1210b are transmitted to the latches 1220a and 1220b in response to the first and second rising clock signals 1st FCLK and 2nd FCLK. Next, the data DQ_0 is output until the next rising of the first internal clock signal CDQ_F 'at the time when the data DO_2 is output.

  In the second test mode, the odd data DO_1 and DO_3 stored in the registers 1210b and 1210d are transmitted to the latches 1220a and 1220b in response to the first and second falling clock signals 1st SCLK and 2nd SCLK. As a result, the data DO_1 is output until the next rising of the second internal clock signal CDQ_S 'at the time when the data DO_3 is output. Therefore, the valid data window for odd data and even data is extended.

  14 to 16 are block diagrams illustrating a memory device and an operation method according to a fourth embodiment of the present invention.

  In this embodiment, in the normal mode, the output circuit includes the first internal clock signal CDQ_F generated in response to the rising edge of the clock signal CLK and the second internal clock signal generated in response to the falling edge of the clock signal CLK. Responds to CDQ_S.

  The output circuit is responsive to the divided first internal clock signal CDQ_F ′ generated from the first internal clock signal CDQ_F and the divided second internal clock signal CDQ_S ′ generated from the second internal clock signal CDQ_S in the test mode. I do. In this embodiment, the frequency of the divided first and second internal clock signals is half the frequency of the first and second internal clock signals.

  In particular, as shown in FIG. 14, in this embodiment, a FIFO (First In First Out) register 1460 is used to store data on the first data line 212. The output buffer 1463 is responsive to the first and second internal clock signals CDQ_F and CDQ_S during the normal mode. However, during the test mode TM, the output buffer 1463 is responsive to the divided first internal clock signal CDQ_F 'and the divided second internal clock signal CDQ_S'. Therefore, the frequency of the clock is divided, for example, in half in the test mode.

  Therefore, the valid data window of the output data DOUT of the output buffer 1463 is extended by dividing the frequency of the internal clock signals CDQ_F and CDQ_S in the test mode. That is, the frequencies of the internal clock signals CDQ_F and CDQ_S are divided into lower frequencies in response to the test mode signal TM. The test mode signal TM may be generated from an MRS that receives a plurality of command signals RASB, CASB, WEB and an address signal. Therefore, the data window of the output data is expanded during the test mode.

  FIGS. 15A and 15B are block diagrams of a division circuit used to generate an internal clock signal divided from the internal clock signal during the test mode.

  In particular, as shown in FIG. 15A, the first division circuit 1500a is configured to generate the divided first internal clock signal CDQ_F ′ in response to the first internal clock signal CDQ_F and the test mode selection signal TM. Is done. As shown in FIG. 15B, the second division circuit 1500b is configured to generate the divided second internal clock signal CDQ_S ′ in response to the second internal clock signal CDQ_S and the test mode selection signal TM. .

  In particular, as shown in FIG. 15A, in this embodiment, the first divider 1500a includes a first divider 1510 responsive to a rising edge of a clock signal and a test mode signal. In this embodiment, the second divider 1500b includes a second divider 1520 responsive to the falling edge of the clock signal and the test mode signal, and a delay 1530 responsive to the second divider 1520.

  The delay unit 1530 is connected between the divided first internal clock signal CDQ_F ′ and the divided second internal clock signal CDQ_S ′ so that the output data is output from the external terminal 217 with an extended valid data window. Used to extend the time interval of the rising edge of.

  FIG. 16 is a timing diagram of the operation according to the embodiment of FIGS. 14, 15A and 15B.

  Referring to FIGS. 14, 15A, and 15B, data RDIO_0 to RDIO_3 are stored in a FIFO register 1460 and transmitted to an output buffer 1463 in response to an internal clock signal. Next, all data in the output buffer 1463 is output to the outside in the normal mode in response to the first and second internal clock signals CDQ_F and CDQ_S. In the test mode, the output buffer 1463 outputs the read data D0 to D3 to the outside in response to the divided first and second internal clock signals CDQ_F 'and CDQ_S'. As a result, the valid data window is extended. Thus, in the test mode, the memory cell array operates at full speed as in the normal mode, while the output buffer can operate at half the operating speed of the memory cell array.

  FIG. 17 is a flowchart of operations performed by various embodiments of the present invention.

  This operation can be performed using any of the above-described embodiments of FIGS. As shown in FIG. 17, when the normal mode is selected in block 1710, a plurality of data bits are serially output from the memory cell array to the external terminal at a first data transfer rate in block 1720. If the test mode is selected in block 1730, a plurality of data bits are output from the memory cell array to an external terminal at a second data rate lower than the first data rate at block 1740.

  This operation may be performed by the embodiments of FIGS. 2, 3 to 6, 7 to 10, 11 to 13, and / or 14 to 16 according to the above-described various embodiments of the present invention. It can be performed using.

  As described above, the best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used merely for the purpose of describing the present invention, and are not intended to limit the scope of the present invention as described in the appended claims. It was not used for Accordingly, those skilled in the art will recognize that various modifications and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the appended claims.

  INDUSTRIAL APPLICABILITY The present invention is used for testing an IC memory device, and enables an accurate test when testing an IC memory device.

FIG. 4 is a timing chart of operations performed by a conventional DDR and SDR memory device. FIG. 2 is a block diagram illustrating an outline of a memory device and an operation method according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating a memory device and an operation method according to a first embodiment of the present invention. FIG. 4 is a circuit diagram of a multiplexer used in the embodiment of FIG. FIG. 5 is a timing chart of the operation performed in the embodiment of FIGS. 3 and 4. FIG. 5 is a timing chart of the operation performed in the embodiment of FIGS. 3 and 4. FIG. 5 is a block diagram illustrating a memory device and an operation method according to a second embodiment of the present invention; FIG. 8 is a circuit diagram of a multiplexer used in the embodiment of FIG. 7. FIG. 8 is a circuit diagram of an output buffer used in the embodiment of FIG. FIG. 10 is a timing chart of an operation performed by the embodiment of FIGS. 7 to 9. FIG. 9 is a block diagram illustrating a memory device and an operation method according to a third embodiment of the present invention. FIG. 12 is a circuit diagram of an output buffer used in the embodiment of FIG. FIG. 13 is a timing chart performed by the embodiment of FIGS. 11 and 12; FIG. 11 is a block diagram illustrating a memory device and an operation method according to a fourth embodiment of the present invention. 15 is a block diagram of a divider circuit used in the embodiment of FIG. 15 is a block diagram of a divider circuit used in the embodiment of FIG. FIG. 15 is a timing diagram of the operations performed by the embodiments of FIGS. 14, 15A and 15B. 4 is a flowchart of operations performed by various embodiments of the present invention.

Explanation of reference numerals

200 Memory device 211 Memory cell array 212 First data line 213 Output circuit 214 Second data line 217 External terminal DR1 First data transfer rate DR2 Second data transfer rate

Claims (32)

A memory cell array for outputting a plurality of data bits in parallel at a first data transfer rate;
In the normal mode, the plurality of data bits are serially output to the external terminal at the first data transfer rate, and in the test mode, the plurality of data bits are output to the external terminal at a second data transfer rate lower than the first data transfer rate. And an output circuit for outputting the data in series to the IC memory device. The memory cell array is responsive to a clock signal having rising and falling edges,
The first data rate is generated in response to both rising and falling edges of the clock signal, and the second data rate is responsive to only one of the rising and falling edges of the clock signal. The IC memory device according to claim 1, wherein the IC memory device is generated as a result. The memory cell array outputs the plurality of data bits in parallel on the corresponding plurality of first data lines at the first data transfer rate;
In the normal mode, the output circuit outputs the plurality of data bits to the external terminal in series at the first data transfer rate using the corresponding plurality of second data lines, and in the test mode, The IC memory device according to claim 1, wherein the plurality of data bits are serially output to the external terminal at the second data rate using a plurality of second data lines.   The output circuit, in the test mode, duplicates a first portion of the plurality of data bits, outputs the duplicated first portion in series to the external terminal at the second data rate, and outputs the plurality of data bits. 2. The method of claim 1, wherein a second portion of the bit is duplicated and the duplicated second portion is serially output to the external terminal at the second data rate lower than the first data rate. IC memory device. The memory cell array is responsive to a clock signal having rising and falling edges,
In the normal mode, the output circuit is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal, 2. The IC memory device according to claim 1, wherein the test mode responds to only one of the first and second internal clock signals. The memory cell array is responsive to a clock signal having rising and falling edges,
In the normal mode, the output circuit is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal, 2. The IC memory device according to claim 1, wherein the test mode alternately responds to the first and second internal clock signals. The memory cell array is responsive to a clock signal having rising and falling edges,
In the normal mode, the output circuit is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal, The test mode is responsive to a divided first internal clock signal generated from the first internal clock signal and a divided second internal clock signal generated from the second internal clock signal. 3. The IC memory device according to claim 1. The memory cell array outputs the plurality of data bits in parallel on the corresponding plurality of first data lines at the first data transfer rate;
The output circuit includes a multiplexer that multiplexes and outputs data read out on the first data line onto a corresponding plurality of second data lines, and an output that serially outputs data on the second data line to the external terminal. The IC memory device according to claim 1, further comprising a buffer.   The multiplexer connects each first data line to each second data line in the normal mode, and connects each even-numbered first data line to each even-numbered data line in the first test mode of the test mode. 9. The second test mode of claim 2, wherein each odd first data line is connected to each odd second data line in a second test mode of the test mode. An IC memory device according to claim 1. A memory cell array that outputs a plurality of data bits in parallel at a first data transfer rate on a corresponding plurality of first data lines;
In the normal mode, the plurality of data bits are serially output to the external terminal at the first data transfer rate. In the test mode, the plurality of data bits are output to the external terminal at a second data transfer rate lower than the first data transfer rate. A multiplexer that serially outputs data bits, multiplexes and outputs data read on the first data line onto a corresponding plurality of second data lines, and serially outputs data on the second data line to the external terminal An output circuit including an output buffer for outputting;
A mode register set for generating first and second test mode signals in response to a plurality of command signals to place the multiplexer in the first and second test modes of the test mode;
The multiplexer connects each first data line to each second data line in the normal mode, and connects each even-numbered first data line to each even number in the first test mode of the test mode. A second data line, and in the second test mode of the test mode, connecting each odd first data line to each odd second data line;
The multiplexer includes a first switch for connecting each even-numbered first data line to each even-numbered second data line in the first test mode, and a respective odd-numbered first data line in the second test mode. A second switch for connecting the data line to each odd-numbered second data line, and connecting each odd-numbered second data line to each adjacent even-numbered second data line in the first and second test modes. And an equivalent circuit connected to the IC memory device.   A mode register set for generating first and second test mode signals in response to a plurality of command signals to place the multiplexer in the first and second test modes of the test mode. The IC memory device according to claim 9. A memory cell array that outputs a plurality of data bits in parallel at a first data transfer rate on a corresponding plurality of first data lines;
In the normal mode, the plurality of data bits are serially output to the external terminal at the first data transfer rate. In the test mode, the plurality of data bits are output to the external terminal at a second data transfer rate lower than the first data transfer rate. A multiplexer that serially outputs data bits, multiplexes and outputs data read on the first data line onto a corresponding plurality of second data lines, and serially outputs data on the second data line to the external terminal An output circuit including an output buffer for outputting;
A mode register set for generating first and second test mode signals in response to a plurality of command signals to place the multiplexer in the first and second test modes of the test mode;
The multiplexer connects each first data line to each second data line in the normal mode, and connects each first data line to each second data line in the first test mode of the test mode. Wherein the odd and even first data lines are cross-connected to the even and odd second data lines, respectively, in the second test mode of the test mode. Memory device. The memory cell array is responsive to a clock signal having rising and falling edges,
The output buffer is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode, 13. The IC memory device according to claim 12, wherein the first and second test modes in the test mode respond to only one of the first and second internal clock signals. The multiplexer,
A first switch for connecting each first data line to each second data line in the first test mode;
And a second switch for cross-connecting each odd-numbered and even-numbered first data line to each even-numbered and odd-numbered second data line in the second test mode. 13. The IC memory device according to claim 12. The output buffer comprises:
A plurality of registers for storing data read on each of the first data lines;
Latching data output from a first adjacent register in response to a first clock signal, and outputting data from a second adjacent register in response to a second clock signal A plurality of latches for latching data to be
Responding to the latch, responding to the first and second internal clock signals in the normal mode, and responding to one of the first and second internal clock signals during the first and second test modes. 14. The IC memory device according to claim 13, further comprising: a parallel-to-serial converter that responds only. The memory cell array outputs the plurality of data bits in parallel on the corresponding plurality of first data lines at the first data transfer rate;
The IC memory device according to claim 1, wherein the output circuit includes an output buffer that outputs data to the external terminal in series. The memory cell array is responsive to a clock signal having rising and falling edges,
In the normal mode, the output circuit is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal, In a first test mode of the test mode, only one of the first and second internal clock signals is responsive, and in a second test mode of the test mode, the first and second internal clock signals of the first and second internal clock signals are responded to. 17. The IC memory device according to claim 16, wherein the IC memory device responds only to the other one. The output buffer comprises:
A plurality of registers for storing data read on each of the first data lines;
Latching data output from a first adjacent register in response to a first clock signal, and outputting data from a second adjacent register in response to a second clock signal A plurality of latches for latching data to be
Responding to the latch, responding to the first and second internal clock signals in the normal mode, and responding to only one of the first and second internal clock signals during the first test mode. 18. The parallel-to-serial converter responsive to the second test mode and responsive to only one of the first and second internal clock signals. IC memory device.   A mode register set for generating first and second test mode signals for placing the output buffer in the first and second test modes of the test mode in response to a plurality of command signals. The IC memory device according to claim 17, wherein: The memory cell array is responsive to a clock signal having rising and falling edges,
The output buffer is responsive to a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal in the normal mode, 17. The IC memory device according to claim 16, wherein the test mode responds to the divided first and second internal clock signals.   21. The IC memory device of claim 20, wherein the frequency of the divided first and second internal clock signals is half of the frequency of the first and second internal clock signals, respectively.   21. The IC memory device of claim 20, further comprising a mode register set responsive to a plurality of command signals to generate a test mode signal for placing the output buffer in the test mode. A first division circuit for generating the divided first internal clock signal in response to a rising edge of the clock signal and a test mode selection signal;
21. The IC according to claim 20, further comprising: a second divider that generates the divided second internal clock signal in response to a falling edge of the clock signal and the test mode selection signal. Memory device. The first divider circuit includes a first divider responsive to a rising edge of the clock signal and the test mode signal,
24. The method of claim 23, wherein the second divider includes a second divider responsive to a falling edge of the clock signal and the test mode signal, and a second delay element responsive to the second divider. An IC memory device according to claim 1. A method of operating an IC memory device having a memory cell array that outputs a plurality of data bits in parallel at a first data transfer rate, comprising:
In the normal mode, the plurality of data bits are serially output from the memory cell array to an external terminal at the first data transfer rate,
In the test mode, the plurality of data bits are serially output from the memory cell array to the external terminal at a second data rate lower than the first data rate. In a case where the plurality of data bits are serially output in the normal mode, in response to a rising edge and a falling edge of a clock signal, the normal mode transmits the data bits from the memory cell array to the external terminal at the first data transfer rate. Output multiple data bits in series,
In the case where the plurality of data bits are serially output in the test mode, only the rising edge and the falling edge of the clock signal are responsive to the first data rate in the test mode. 26. The method of claim 25, wherein the plurality of data bits are serially output from the memory cell array to the external terminal at two data rates. When outputting the plurality of data bits in series in the test mode,
Duplicating a first portion of the plurality of data bits output from the memory cell array in parallel, outputting the duplicated first portion in series to the external terminal at the second data rate;
26. The method of claim 25, wherein a second portion of the plurality of data bits is duplicated and the duplicated second portion is serially output to the external terminal at the second data rate. The memory cell array is responsive to a clock signal having rising and falling edges,
When outputting the plurality of data bits in series in the normal mode, a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal. Responsive to an internal clock signal, serially outputting the plurality of data bits from the memory cell array to the external terminal at the first data rate;
When outputting the plurality of data bits in series in the test mode, the second data transfer is slower than the first data transfer rate in response to only one of the first and second internal clock signals. 26. The method of claim 25, wherein the plurality of data bits are serially output from the memory cell array to the external terminal at a rate. The memory cell array is responsive to a clock signal having rising and falling edges,
When outputting the plurality of data bits in series in the normal mode, a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal. Responsive to an internal clock signal, serially outputting the plurality of data bits from the memory cell array to the external terminal at the first data rate;
When outputting the plurality of data bits in series in the test mode, the memory cell array responds to the first and second internal clock signals alternately and at the second data transfer rate lower than the first data transfer rate. 26. The method according to claim 25, wherein the plurality of data bits are output in series to the external terminal. The memory cell array is responsive to a clock signal having rising and falling edges,
When outputting the plurality of data bits in series in the normal mode, a first internal clock signal generated in response to a rising edge of the clock signal and a second internal clock signal generated in response to a falling edge of the clock signal. Responsive to an internal clock signal, serially outputting the plurality of data bits from the memory cell array to the external terminal at the first data rate;
Responding to the divided second internal clock signal generated from the divided first and second internal clock signals generated from the first internal clock signal when outputting the plurality of data bits in series in the test mode; 26. The method of claim 25, wherein the plurality of data bits are serially output from the memory cell array to the external terminal at the second data rate lower than the first data rate. The memory cell array outputs the plurality of data bits in parallel on the corresponding plurality of first data lines at the first data transfer rate, and the data on the plurality of first data lines is corresponding to the corresponding plurality of second data lines. Conveyed on the data line,
When outputting the plurality of data bits in series in the normal mode, connecting each first data line to each second data line in the normal mode;
When outputting the plurality of data bits in series in the test mode, connecting each even-numbered first data line to each even-numbered second data line in a first test mode of the test mode; 27. The method of claim 25, wherein each odd first data line is connected to each odd second data line in a second test mode of the test mode. The memory cell array outputs the plurality of data bits in parallel on the corresponding plurality of first data lines at the first data transfer rate, and the data on the plurality of first data lines is corresponding to the corresponding plurality of second data lines. Conveyed on the data line,
When outputting the plurality of data bits in series in the normal mode, connecting each first data line to each second data line in the normal mode;
When outputting the plurality of data bits in series in the test mode, each first data line is connected to each second data line in a first test mode of the test mode, and a second test of the test mode is performed. 26. The method of claim 25, wherein each of the odd and even first data lines is cross-connected to a respective even and odd second data line in a mode.

Images