200400530 (1) 玖、發明說明 【發明所屬之技術領域】 本發明是關於一種具有對向配置的基板，及配設於其 中一方的基板內面的複數電子源的畫像顯示裝置及其製造 方法。 【先Η丨i技術】 近年來，盼望高品位廣播用或是配合廣播用的高淸晰 度的晝像顯示裝置。針對於該螢幕顯示性能期望更嚴格的 性能。爲了達成此些期望，必須爲螢幕面的平坦化，高淸 晰度化，同時也須謀求輕量，薄型化。 作爲滿足如上述的盼望的晝像顯示裝置，例如著重場 發射顯示裝置（以下稱爲FED)等的平面顯示裝置。該fed是 具有特定間隙而對向配置的第1基板及第2基板，此些基板 是其周緣部彼此間經由直接或矩形框狀的側壁互相地被接 合而構成真空外圍器。在第1基板的內面形成有營光體層 ，而在第2基板的內面，作爲激勵螢光體層所發出的電子 源而設有複數電子放出元件。 又，爲了支持施加於第1基板及第2基板的大氣壓負荷 ，在此些基板之間作爲支持構件配設有複數間隙壁。在該 FED中，顯示畫像時陽極電壓被施加於螢光體層，俾藉由 陽極電壓來加速從電子放出元件所放出的電子束而相撞於 螢光體層，發光螢光體而顯示畫像。 在種FED中，電子放出元件的大小爲微米階，而可將 -6 - (2) (2)200400530 第1基板與第2基板之間隔設定在毫米階。所以，與使用作 爲現在的電視機或電腦的顯示裝置的陰極射線管（以下稱 爲CRT)相比較，成爲可達成晝像顯示裝置的高淸晰度化， 輕量化及薄型化。 在如上述的畫像顯示裝置中，爲了得到實用性顯示特 性，使用與通常CRT同樣的螢光體，盼望將陽極電壓設定 在數kV以上。但是，第1基板與第2基板之間的間隙，是由 淸晰度或支持構件的特性，製造性等觀點上無法增大，而 須設定在1至2mm左右。所以，從電子放出元件所放出的 電子與形成在第1基板的螢光面相撞時所發生的二次電子 及反射電子相撞於配設於基板間的間隙壁，結果，使得間 隙壁帶電。在FED的加速電壓中，一般間隙壁是帶正電， 而從電子放出元件所放出的電子束是被拉至間隙壁，因而 會從原來的軌道偏離。因此對於螢光體層發生電子束的偏 差著落，使得顯示畫像的色純度有劣化的缺點問題。 爲了減低依此種間隙壁所產生的電子束的吸引，考慮 在間隙壁表面的全部或一部分施以導電處理而能避免帶電 。然而，在間隙壁本體施加導電處理時，經由間隙壁增加 從第1基板流在第2基板的無效電流，而會引起溫度上昇或 增加耗電。 【發明內容】 本發明是鑑於以上事項而創作者，其目的是在於提供 一種不會引起溫度上昇或增加耗電，防止電子束的偏軌， (3) (3)200400530 提商畫像品位的畫像顯示裝置/及其製造方法。 爲了達成上述目的，本發明的形態的晝像顯示裝置， 其特徵爲具備：具有晝像顯示面的第1基板，及 隔著間隙對向配置於上述第1基板，同時設有放出電 子並激勵上述畫像顯示面的複數電子源的第2基板，及 配設於上述第1基板及第2基板間，並支持作用於第1 及第2基板的大氣壓負荷的複數間隙壁，及 分別配置於上述間隙壁的上述第2基板側的前端與上 述第2基板之間，並反斥從上述電子源所放出的電子束的 導電體。 又，本發明的其他形態的畫像顯示裝置的製造方法， 屬於具有畫像顯示面的第1基板，及隔著間隙對向配置於 上述基板，同時設有放出電子並激勵上述晝像顯示面的複 數電子源的第2基板，及配設於上述第1基板及第2基板間 ，並支持作用於第1及第2基板的大氣壓負荷的複數間隙壁 的畫像顯示裝置的製造方法，其特徵爲： 在上述第2基板的特定位置與上述間隙壁的第2基板側 的前端之間配置導電體。 在配置上述間隙成爲使其第2基板側的前端夾住上述 導電體並抵接於上述第2基板的狀態下，互相地接合上述 第1及第2基板。 依照如上述地所構成的晝像顯示裝置，從位於間隙壁 近旁的電子源所放出的電子，是藉由導電體所形成的電場 一旦被反斥，採取朝從間隙壁遠離之方向的軌道之後’最 -8- (4) (4)200400530 後被間隙壁吸引而採取朝接近於間隙壁的方向的軌道。藉 由該反斥與吸引來抵銷電子的偏軌，而從電子源所放出的 電子是最終地達到晝像顯示面的目標位置。由此，可得至5! 減低起因於電子的偏差著落的色純度的劣化，又提高品位 的畫像顯示裝置。 【實施方式】 以下一面參照圖式，一面詳述將本發明作爲平面型晝 像顯示裝置適用FED的一種表面傳導型電子放出裝置（以下 稱爲SED)的實施形態。 如第1圖至第3圖所示地，該SED是作爲透明絕緣基板 分別具備矩形狀玻璃板所組成的第1基板1 0及第2基板1 2， 此些基板是隔著大約1.0至2.0mm的間隙對向配置。第2基 板12是形成稍大於第1基板10的大小尺寸。如此，第1基板 10及第2基板12是經由玻璃所組成的矩形框狀的側壁14接 合有周緣部彼此間，構成扁平矩形狀的真空外圍器1 5。 在第1基板1 0的內面形成有作爲晝像顯示面的螢光體 的螢幕。該螢光體螢幕1 6是排列藉由電子的相撞發光成紅 、藍、綠的螢光體層R，G，B及紫色遮光層11所構成。此 些螢光體層R，G，B是形成條紋狀或點狀。在螢光體螢幕 16上，形成有鋁等所組成的金屬襯墊17及未圖示的吸氣膜 。又，在第1基板10與螢光體螢幕之間，設置如ITO等所組 成的透明導電膜或濾色片膜也可以。 在第2基板12的內面，作爲激勵螢光體螢幕16的螢光 -9- (5) (5)200400530 體層的電子源，設有分別放出電子束的多數表面傳導型電 子放出元件1 8。此些電子放出元件18是對應每一像素排列 成複數列及複數行。各電子放出元件18是由未予圖示的電 子放出部，在該電子放出部施加電壓的一對元件電極等所 構成。第2基板1 2的內面上，矩陣狀地設有將電位供給於 電子放出元件1 8的多數條配線2 1，其端部是被拉出至真空 外圍器1 5的外部。 功能作爲接合構件的側壁1 4是藉由低融點玻璃，低融 點金屬等的密封材20，被密封於第1基板1 〇的周緣部及第2 基板12的周緣部，接合第1基板及第2基板彼此間。 又，如第2圖及第3圖所示地，SED是具備配於第1基 板10及第2基板12間的間隙壁裝配22。間隙壁裝配22是具 備板狀柵極24，及一體地豎設於柵極的兩面的複數柱狀間 隙壁所構成。 再予以詳述，柵極24是具有與第1基板10的內面對向 的第1表面24a及與第2基板12的內面對向的第2表面24b， 而與此些基板平行地配置。在柵極24藉由蝕刻等形成有多 數電子束通過孔26及複數間隙壁開孔28。功能作爲本發明 的開孔的電子束通過26，是與電子放出元件1 8分別對向地 排列，透過從電子放出元件所放出的電子束。又，間隙壁 開孔28是位於各該電子束通過孔26間而以特定節距加以配 置。 柵24是如藉由鐵-鎳系的金屬板形成厚度〇.1至〇.25mm ，同時在其表形成有構成金屬板的元素所組成的氧化膜， - 10- (6) (6)200400530 例如形成有Fe3〇4、NiFe3〇4所組成的氧化膜。在柵極24的 表面，形成有塗布，燒成玻璃，陶瓷所組成的高電阻物質 的高電阻膜，高電阻膜的電阻是被設定成E +8 Ω /□以上。 電子束通過孔26是形成如0.15 + 0.25mmx 0.15至 0.2 5 mm的矩形狀，間隙壁開孔28是形成如直徑大約0.2至 0.5 m m的圓形。 又，上述的高電阻膜是也形成在設於柵極24的電子束 通過孔2 6的壁面。 在栅極24的第1表面22a上面，重疊於各間隙壁開孔28 一體地豎設有第1間隙壁3〇a。在各第1間隙壁30a的延出端 塗布有銦層，構成緩和間隙壁高度的參差不齊的緩和層3 1 。如此，各第1間隙壁3 0a的延出端，是經由緩和層3 1，吸 氣膜，金屬襯墊17及螢光體螢幕16的遮光層11抵接於第1 基板1 〇的內面。緩和層3 1是針對於電子束的軌道並沒有任 何影響者，若間隙壁的高度參差不齊的緩和效果具有某一 適當硬度，並不被限定於金屬者。又，金屬襯墊17及螢光 體螢幕1 6的黑色遮光層1 1也具有緩和間隙壁的高度參差不 齊的效果，若這樣子就可得到充分高的參差不齊緩和效果 時，則並不一定設置緩和層3 1。 在柵極24的第2表面24b上面，重疊於各間隙壁開孔28 一體地豎設有第2間隙壁30b，其延出端是抵接於第2基板 1 2的內面。各第2間隙壁3 0 b的延出端是位於設在第2基板 1 2的內面上的配線2 1上面，同時在該配線與第2間隙壁的 延出端之間設有導電體3 3。導電體3 3是形成與第2間隙壁 -11 - (7) (7)200400530 3 0 b的延出端大約相似形狀，該厚度，亦即沿著與第2其板 12成爲正交方向的高度是例如設定在12〇// m。 如下述’導電體33是從第2間隙壁30b朝分離方向反斥 地作用從電子放出元件1 8所放出的電子束。導電體3 3是由 如白金、鎢、銦、鍊、餓、釕等高融點金屬，此些合金， 或含有此些的金屬的導電性玻璃等所形成。作爲導電體3 3 也可使用銦、鋁、銀、銅等金屬，惟在產生放電時，若溶 融溫度較低則被熔融而有無法發揮原來的功能之虞，而使 用高融點金屬者較理想。 導電體3 3的形狀是並未被加以特別限定，惟考慮放電 而較圓地形成隅部較理想。導電體3 3的高度是考慮給予電 子束的反斥力，亦即考慮電子束的軌道修正量而任意地設 定。 第1及第2間隙壁30a，30b是分別形成從柵極24側朝延 出端直徑變小的尖細推拔狀。例如，各第1間隙壁3 〇 a是位 於柵24側的基端的直徑形成大約0.4mm，延出端的直徑形 成大約〇 . 3 m m ’而尚度形成大約0.6 m m。又，各第2間隙壁 3 0 b是位於柵2 4側的基端的直徑形成大約〇 . 4 m m，延出端 的直徑形成大約〇. 25 ，而高度形成大約〇. 8 mm。如此地 ，第1間隙壁3〇a的高度是形成低於第2間隙壁30b的高度， 第2間隙壁的高度，是對於第1間隙壁的高度被設定成大約 4/3倍以上。 第1間隙壁3〇a及第2間隙壁30b的表面電阻是成爲5x 1〇13 Ω。各間隙壁開孔28，第1及第2間隙壁30a ’ 3〇b是位於 (8) (8)200400530 互相整齊地排列；第1及第2間隙壁是經由間隙壁開孔2 8互 相一體地被連結。由此，第1及第2間隙壁30a，3Ob是在從 兩面夾住柵極24的狀態而與柵極24—體地形成。 如上述所構成的間隙壁裝配22是被配設在第1基板10 及第2基板12間。如此，第1及第2間隙壁30a，30b，是藉由 抵接於第1基板1 0及第2基板1 2的內面，支持作用於此些基 板的大氣壓負荷，並將基板間隔維持在特定値。 如第2圖所示地，SED是具備將電壓施加於柵極24及第 1基板10的金屬襯墊17的電壓供給部50。該電壓供給部50， 是分別被連接於柵極24及金屬襯墊17，例如將12kV電壓施 加於柵極24，而將10kV電壓施加於金屬襯墊17。亦即，施 加於柵極24的電壓是設成高於施加於第1基板1 0的電壓， 例如設定在1.2 5倍以內。 在上述SED中，顯示晝像時陰極電壓在施加於螢光體 螢幕16及金屬襯墊17，而藉由陽極電壓來加速從電子放出 元件1 8所放出的電子束B俾相撞於螢光體螢幕1 6。由此， 螢光體螢幕1 6的螢光體層被激勵而發光，並顯示晝像。 以下，針對於如上述地所構成的SED的製造方法加以 說明。製造間隙壁裝配22時，首先，準備特定尺寸的柵極 2 4，具有與栅極大約相同尺寸及未圖示的矩形板狀第1及 第2模具。這時候，進行脫脂，洗淨，乾燥Fe-50 %Ni所組 成的板厚0.1 2mm的薄板之後，藉由蝕刻形成電子束通過孔 26，及間隙壁開孔28而作爲柵極24。然後，藉由氧化處理 來氧化整體柵極24，包含電子束通過孔26及間隙壁開孔28 (9) (9)200400530 的內面，將絕緣膜形成在柵極表面。又，在絕緣膜上面’ 噴霧覆蓋分散氧化錫及氧化銻的微粒子的液體，經乾燥燒 成而形成尚電阻膜。 第1及第2模具是具有分別對應於柵極24的間隙壁開孔 28的複數透孔。又，在第1模具及第2模具中，至少在對應 於間隙壁開孔28的複數透孔的內面，塗佈有藉由熱處理而 熱分解的樹脂。 又，將第1模具在各透孔定位成與柵極24的間隙壁開 孔28整齊排列的狀態密著於柵極的第1表面24a。同樣地， 將第2模具在各透孔定位成與柵極24的間隙壁開孔28整齊 排列的狀態密著於柵極的第2表面24b。如此，使用未圖示 的定位器等互相地固定此些第1模具，柵極24及第2模具。 然後’例如從第1模具的外面側供給糊狀的間隙壁形 成材料，俾將間隙壁形成材料塡充於第1模具的透孔，柵 極24的間隙壁開孔28，及第2模具的透孔。作爲間隙壁形成 材料，至少使用紫外線硬化型黏合劑（有機成分）及含有玻 ΐ离塡料物的玻璃糊。 然後’對於塡充的間隙壁形成材料，作爲放射線從第 1及第2模具的外面側照射紫外線（υν)，俾υV硬化間隙壁形 成材料。之後，視需要進行熱硬化也可以。然後，藉熱處 理來熱分解塗佈於第1模具及第2模具的各透過孔的樹脂， 在間隙壁形成材料與模具之間製作間隙，而從柵極24剝離 第1及第2模具。 然後’在加熱爐內熱處理塡充有間隙壁形成材料的柵 -14 - (10) (10)200400530 極2 4 ’從間隙壁形成材料內飛掉黏合劑之後，在大約5 〇 〇 至5 5 0 °C進行3 0分鐘至一小時正式燒成間隙壁形成材料。 由此，在柵極24上得到製作有第i及第2間隙壁30a，30b的 間隙壁裝配22。 另一方面’事先準備設有螢光體螢幕16及金屬襯墊17 的第1基板10，以及設有電子放出元件18及配線21之同時接 合有側壁14的第2基板12。 然後，在第2基板1 2的配線2 1上印刷導電性糊成爲與 第2間隙壁30b的前端大約相似形狀而厚度成爲12〇 /z m之後 ，藉由乾燥及燒成，而在配線2 1上的特定位置形成導電體 3 3。又，將形成高緩和層3 1所形成所需的銦粉末塗佈於各 第1間隙壁30a的延出端。 之後，將如上述地所構成的間隙壁裝配22定位配置於 第2基板12上面。這時候，使得第2間隙壁30b的延出端能分 別接觸於導電體3 3地定位間隙壁裝配22。在該狀態，將第1 基板10，第2基板12及間隙壁裝配22配置在真空室內，真空 排氣真空室內之後，將第1基板經由側壁14接合於第2基板 。同時地，熔融被配置於第1間隙壁30a的延出端的銦粉末 ’以第1基板1 0被壓潰來修正高度。由此，可製造具備間 隙壁裝配22的SED。 如第3圖所示地，依照如上述地所構成SED，從位於第 2間隙壁30b近旁的電子放出元件18所放出的電子束B，是藉 由形成有設置在第2間隙壁30b的延出端與第2基板12之間的 導體層的電場被反斥。一面採用從第2間隙壁遠離的方向的 -15- (11) (11)200400530 軌道一面朝電子束通過孔26。然後，電子束B這一次是被帶 電的第2間隙壁30b及第1間隙壁30a吸引，而將取接近於此些 間隙壁的方向的軌道。如此，藉由該反斥與吸引被抵銷電子 束B的軌道偏離，而從電子放出元件1 8所放出的電子束B， 是最終地達到作爲螢光體螢幕1 6的目標的螢光體層。 具體地，從電子放出元件至間隙壁側面的距離愈小，則 電子束移動至間隙壁側的量愈大，相反地對於間隙壁側面的 距離充分大時，則電子束移動至間隙壁側的量是成爲可忽略 的量。電子束的移動現象是在螢光面所發生的二次電子及反 射電子相撞於間隙壁使得間隙壁帶電而發生。這時候，從 SED所使用的加速電壓至間隙壁表面的二次電子放出常數成 爲1以上，間隙壁側壁是帶正電’成爲可將電子束拉至間隙 壁側。 在本實施形態中，在電子速度較小的間隙壁的第2基板 側的端部與第2基板之間設置導電體33 ’藉由該導電體33， 形成電子束與間隙壁反斥的方向的電場。控制導電體3 3的高 度來變更電場的強度’而可控制反斥量。如此’在本實施形 態中，並不迴避間隙壁的帶電’而藉由依間隙壁的吸引與依 電子束3 3的反斥來抵銷電子束的軌道偏離。所以’依照上述 SED，不必設置如CRT的電子槍地收歛電子束所需的複雜機 構。 如此地，依照上述的SED ’使得第1及第2間隙壁30a ’ 3Ob帶電，而藉由此些間隙壁使得電子束以立近時’也可防 止電子束的軌道偏離。由此，防止電子束B的偏差著落，結 (12) (12)200400530 果，減低色純度的劣化而可謀求提高畫像品位。 又，在間隙壁的表面的全部或一部分直接施以導電處理 時，則從第1基板經由間隙壁流至第2基板的無效電流會增加 ，而產生溫度上昇或增加耗電。又，該導電處理部在SED的 動作中成爲氣體的發生源，也有產生位於間隙壁近旁的電子 源的離子相撞的情形。對於此，依照本實施形態，不會產生 增加無效電流，溫度上昇或增加耗電，或離子相撞，藉由導 電體33來變更間隙壁週邊的電場而可容易地控制電子束的軌 道。 準備本實施形態的SED，及未設有上述的導電體33的 SED，來比較電子束的移動量。結果，在未設有導電體的 SED，電子束在間隙壁側移動的120 // m，而在本實施形態的 SED中，電子束的移動量幾乎成爲零，也改善了顯示晝像的 色純度。 又，依照上述SED，柵極24配置於第1基板10與第2基板 12之間，同時第1圖間隙壁30a的高度是形成低於第2間隙壁 30b的高度。由此，柵極24是位於比第2基板12更接近第1基 板10側的位置。所以，即使從第1基板10側產生放電時，藉 由柵極24，成爲也可抑制設於第2基板12上的電子放出元件 1 8的放電破損。因此，可得到對於放電的耐壓性上優異而提 商畫像品位的SED。 又’依照上述構成的SED，藉由將第1間隙壁30a的高度 形成比第2間隙壁30b更低，將施加於柵極24的電壓比施加於 第1基板1 0的電壓較大時，也可將從電子放出元件1 8所發生 (13) (13)200400530 的電子確實地達到至螢光體螢幕側。 又，在複數第1間隙壁30a有高度參差不齊的情形，藉由 高度緩和層3 1也可吸收參差不齊，可確實地接觸複數第1間 隙壁與第1基板10。因此，藉由第i及第2間隙壁30a，30b， 成爲幾乎在所有領域可均勻地保持第1基板10及第2基板1 2間 的間隔。 以下，針對於本發明的第二實施形態的SED加以說明。 如第4圖所示地，依照第2實施形態，導電體33是藉由金屬或 合金形成與第2間隙壁30b的延出端相似形狀。例如導電體33 是由Fe-50%Ni的厚度200 /zm的金屬板所形成，而藉由導電 性玻璃料，導電性黏接劑等所組成的固定層被固定在第2基 板12的配線21上。如此，間隙壁裝配22是在各第2間隙壁30b 的延出端抵接於導電體3 3的狀態下，被配設在第1及第2基 板1 0，1 2之間。 又，其他構成是與上述的第一實施形態相同，在相同 部分賦予相同的參照記號而省略其詳述。 欲製造如上述地所構成的第二實施形態的SED時，藉 由與第一實施形態同樣的工序，形成第1及第2基板1 〇，1 2 及間隙壁裝配22。這時候，第1間隙壁30a的高度是作爲 0.2mm，而第2間隙壁30b的高度是作成1.0mm。 然後，在第2基板1 2的配線2 1上的所定位置，塗佈與 第2間隙壁30b的前端大約相似形狀而厚度5 // m的導電性黏 接劑而形成固定層40。如此，在固定層40上裝載Fe-50 %Ni 所組成的厚度200 /z m的導電體33之後，乾燥固定層，俾將 (14) (14)200400530 導電體33固裝在配線上面。 之後，與第一實施形態同樣地，將間隙壁裝配2 2定位 配置在第2基板12上面。這時候，使得第2間隙壁3〇b的延出 端與導電體3 3分別接觸地定位間隙壁裝置22。在該狀態， 將第1基板10，第2基板12，及間隙壁裝配22配置在真空室 內，而真空排氣真空室內之後，將第1基板經由側壁1 4接 合於第2基板。由此，來製造SED。 依照以上構造的SED，可得到與第一實施形態同樣的作 用。又，在第二實施形態中，可將導電體3 3固定於配線2 1的 固定層40。使用作爲修正間隙壁的高度參差不齊的修正層。 所以，不需要間隙壁的高加工精度，成爲可謀求減低間隙壁 的製造成本。200400530 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to an image display device having a substrate disposed oppositely and a plurality of electron sources arranged on the inner surface of one of the substrates, and a method for manufacturing the same. [Preliminary technology] In recent years, high-definition daylight display devices for broadcasting or high-definition broadcasting are expected. More stringent performance is expected for this screen display performance. In order to meet these expectations, it is necessary to flatten the screen surface and increase the resolution, and at the same time, it must be lightweight and thin. As a day image display device satisfying the above-mentioned expectations, a flat display device such as a focused field emission display device (hereinafter referred to as FED) is used. This fed is a first substrate and a second substrate which are arranged to face each other with a specific gap. These substrates are connected to each other via a direct or rectangular frame-shaped side wall to form a vacuum peripheral. A phosphor layer is formed on the inner surface of the first substrate, and a plurality of electron emission elements are provided on the inner surface of the second substrate as an electron source for exciting the phosphor layer. In addition, in order to support the atmospheric pressure load applied to the first substrate and the second substrate, a plurality of partition walls are provided as supporting members between the substrates. In this FED, an anode voltage is applied to the phosphor layer when an image is displayed, and the anode voltage is used to accelerate an electron beam emitted from an electron emission element to collide with the phosphor layer to emit a phosphor to display an image. In this type of FED, the size of the electron emission element is in the order of micrometers, and the interval between the first substrate and the second substrate can be set to the order of millimeters. Therefore, compared with a cathode ray tube (hereinafter referred to as a CRT) used as a display device of a current television or a computer, it is possible to achieve high definition, weight reduction, and thinness of a day image display device. In the image display device as described above, in order to obtain practical display characteristics, a phosphor similar to that of a normal CRT is used, and it is desirable to set the anode voltage to several kV or more. However, the gap between the first substrate and the second substrate cannot be increased from the standpoint of sharpness or characteristics of the supporting member, manufacturability, etc., but must be set to about 1 to 2 mm. Therefore, when the electrons emitted from the electron emitting element collide with the fluorescent surface formed on the first substrate, the secondary electrons and the reflected electrons collide with the gap wall disposed between the substrates. As a result, the gap wall is charged. . In the acceleration voltage of the FED, the gap wall is generally positively charged, and the electron beam emitted from the electron emitting element is pulled to the gap wall, so it will deviate from the original orbit. Therefore, uneven landing of the electron beam occurs in the phosphor layer, which causes a problem that the color purity of a displayed image is deteriorated. In order to reduce the attraction of the electron beam generated by such a gap wall, it is considered that all or a part of the surface of the gap wall can be electrically conductive to avoid electrification. However, when a conductive treatment is applied to the partition wall body, an ineffective current flowing from the first substrate to the second substrate via the partition wall increases the temperature and increases the power consumption. [Summary of the Invention] The present invention was created in view of the above matters, and its purpose is to provide an image that does not cause temperature rise or increase power consumption and prevent the deflection of the electron beam. (3) (3) 200400530 Display device / manufacturing method thereof. In order to achieve the above object, a day image display device according to an aspect of the present invention includes a first substrate having a day image display surface, and a first substrate disposed opposite to the first substrate with a gap therebetween. The second substrate of the plurality of electron sources on the image display surface, a plurality of spacers disposed between the first substrate and the second substrate, and supporting an atmospheric pressure load acting on the first and second substrates, and are respectively disposed on the above. A conductive body between the front end of the partition wall on the second substrate side and the second substrate and repels an electron beam emitted from the electron source. In addition, a method for manufacturing an image display device according to another aspect of the present invention belongs to a first substrate having an image display surface, and is disposed opposite to the substrate with a gap therebetween, and a plurality of emitting electrons are provided to excite the day image display surface. The manufacturing method of a second substrate of an electron source and a plurality of gap display devices arranged between the first substrate and the second substrate and supporting the atmospheric pressure load acting on the first and second substrates is characterized in that: A conductive body is disposed between a specific position of the second substrate and a distal end on the second substrate side of the partition wall. The first and second substrates are bonded to each other in a state where the gap is disposed such that the tip of the second substrate side sandwiches the conductive body and abuts the second substrate. According to the daylight image display device constructed as described above, the electrons emitted from the electron source located near the gap wall are once repelled by the electric field formed by the conductor, and then take the orbit toward the direction away from the gap wall. 'Most-8- (4) (4) 200400530 was later attracted by the gap wall and adopted a track approaching the gap wall. By this repulsion and attraction, the derailment of the electrons is offset, and the electrons emitted from the electron source finally reach the target position of the day image display surface. Thereby, it is possible to obtain 5! An image display device which reduces deterioration in color purity due to the deviation of electrons and improves quality. [Embodiment] An embodiment of a surface-conduction type electron emission device (hereinafter referred to as SED) to which the present invention is applied as a flat day image display device to FED will be described in detail with reference to the drawings. As shown in FIG. 1 to FIG. 3, the SED is a first substrate 10 and a second substrate 12 each having a rectangular glass plate as a transparent insulating substrate, and these substrates are separated by approximately 1.0 to 2.0. Clearance of mm. The second substrate 12 has a size slightly larger than that of the first substrate 10. As described above, the first substrate 10 and the second substrate 12 are connected to each other via the rectangular frame-shaped sidewall 14 made of glass, and constitute a flat rectangular vacuum peripheral 15. A phosphor screen is formed on the inner surface of the first substrate 10 as a day image display surface. The phosphor screen 16 is composed of phosphor layers R, G, and B, and a purple light-shielding layer 11 arranged to emit red, blue, and green by collision of electrons. These phosphor layers R, G, and B are striped or dotted. On the phosphor screen 16, a metal pad 17 composed of aluminum and the like, and a getter film (not shown) are formed. A transparent conductive film or a color filter film made of ITO or the like may be provided between the first substrate 10 and the phosphor screen. On the inner surface of the second substrate 12, as the electron source for exciting the fluorescent light of the phosphor screen 16-(5) (5) 200400530, there are provided a plurality of surface-conduction electron emission elements that emit electron beams, respectively. 8 . These electron emission elements 18 are arranged in a plurality of columns and a plurality of rows corresponding to each pixel. Each electron emission element 18 is composed of an electron emission portion (not shown), and a pair of element electrodes or the like that applies a voltage to the electron emission portion. The inner surface of the second substrate 12 is provided with a plurality of wirings 21 for supplying potentials to the electron emission elements 18 in a matrix form, and the ends thereof are pulled out to the outside of the vacuum peripheral 15. The side wall 14 functioning as a bonding member is sealed to a peripheral portion of the first substrate 10 and a peripheral portion of the second substrate 12 by a sealing material 20 such as low-melting glass, low-melting metal, and the like, and the first substrate is bonded. And the second substrate. As shown in Figs. 2 and 3, the SED is provided with a spacer assembly 22 arranged between the first substrate 10 and the second substrate 12. The partition wall assembly 22 is provided with a plate-shaped grid 24 and a plurality of columnar partition walls integrally erected on both sides of the grid. To further elaborate, the gate 24 has a first surface 24a facing the inner surface of the first substrate 10 and a second surface 24b facing the inner surface of the second substrate 12, and is disposed in parallel with these substrates. . A plurality of electron beam passage holes 26 and a plurality of spacer openings 28 are formed in the gate electrode 24 by etching or the like. The electron beams functioning as the openings of the present invention pass through 26, are arranged opposite to the electron emission elements 18, respectively, and pass through the electron beams emitted from the electron emission elements. The gap openings 28 are arranged between the electron beam passing holes 26 at a predetermined pitch. The grid 24 is formed of an iron-nickel-based metal plate with a thickness of 0.1 to 0.25 mm, and an oxide film composed of elements constituting the metal plate is formed on its surface.-10- (6) (6) 200400530 For example, an oxide film composed of Fe304 and NiFe304 is formed. A high-resistance film of a high-resistance substance composed of coated, fired glass, or ceramic is formed on the surface of the gate electrode 24, and the resistance of the high-resistance film is set to E +8 Ω / □ or more. The electron beam passing hole 26 is formed in a rectangular shape such as 0.15 + 0.25 mmx 0.15 to 0.2 5 mm, and the gap wall opening 28 is formed in a circular shape having a diameter of about 0.2 to 0.5 mm. The above-mentioned high-resistance film is also formed on the wall surface of the electron beam passage hole 26 provided in the gate electrode 24. On the first surface 22a of the grid 24, a first partition wall 30a is vertically formed integrally with each of the partition wall openings 28. An indium layer is coated on the extended end of each first barrier rib 30a to constitute an uneven tempering layer 3 1 that reduces the height of the barrier ribs. In this way, the extending end of each first partition wall 30a is in contact with the inner surface of the first substrate 10 through the relief layer 31, the getter film, the metal pad 17, and the light shielding layer 11 of the phosphor screen 16. . The relaxation layer 31 is for those who do not have any influence on the orbit of the electron beam. If the unevenness of the height of the gap wall has a certain hardness, the relaxation layer is not limited to metal. In addition, the metal pad 17 and the black light-shielding layer 11 of the phosphor screen 16 also have the effect of reducing the unevenness of the height of the gap wall. It is not necessary to set the relief layer 31. On the second surface 24b of the grid 24, a second gap wall 30b is integrally erected in an overlapping manner with each of the gap wall openings 28, and an extension end thereof is in contact with the inner surface of the second substrate 12. The extension end of each second gap wall 3 0 b is located on the wiring 21 provided on the inner surface of the second substrate 12, and a conductor is provided between the wiring and the extension end of the second gap wall. 3 3. The conductor 33 is formed to have a shape similar to that of the extending end of the second partition wall -11-(7) (7) 200400530 3 0 b, and the thickness is in a direction orthogonal to the second plate 12 The height is set at 12 // m, for example. As described below, the 'conductor 33' repels the electron beam emitted from the electron emission element 18 from the second partition wall 30b in the separation direction. The conductor 33 is formed of a high melting point metal such as platinum, tungsten, indium, chain, star, ruthenium, etc., these alloys, or conductive glass containing these metals. As the conductor 3 3, metals such as indium, aluminum, silver, and copper can also be used. However, when a discharge occurs, if the melting temperature is low, it will be melted and may not perform its original function. ideal. The shape of the conductive body 3 3 is not particularly limited, but it is preferable to form the crotch portion in a round shape in consideration of discharge. The height of the conductor 33 is arbitrarily set in consideration of the repulsive force given to the electron beam, that is, the orbit correction amount of the electron beam. The first and second spacers 30a, 30b are formed in a sharp push-out shape, each of which has a reduced diameter from the gate 24 side toward the extension end. For example, each of the first spacers 30a has a diameter of about 0.4 mm at the base end located on the gate 24 side, and a diameter of about 0.3 mm m at the extension end, and a thickness of about 0.6 mm. In addition, each of the second spacers 30b has a diameter of the base end on the gate 24 side of about 0.4 mm, a diameter of the extension end about 0.25, and a height of about 0.8 mm. In this way, the height of the first partition wall 30a is lower than the height of the second partition wall 30b, and the height of the second partition wall is set to about 4/3 times or more the height of the first partition wall. The surface resistances of the first barrier ribs 30a and the second barrier ribs 30b are 5 x 1013 Ω. Each gap wall opening 28, the first and second gap walls 30a '30b are aligned with each other at (8) (8) 200400530; the first and second gap walls are integrated with each other through the gap wall openings 28 The ground is connected. Accordingly, the first and second partition walls 30a, 3Ob are formed integrally with the gate 24 in a state where the gate 24 is sandwiched from both sides. The partition wall assembly 22 configured as described above is disposed between the first substrate 10 and the second substrate 12. In this way, the first and second partition walls 30a and 30b support the atmospheric pressure load acting on these substrates by abutting the inner surfaces of the first substrate 10 and the second substrate 12 and maintaining the substrate interval at Specific 値. As shown in FIG. 2, the SED is a voltage supply unit 50 including a voltage applied to the gate 24 and the metal pad 17 of the first substrate 10. The voltage supply unit 50 is connected to the gate 24 and the metal pad 17, respectively. For example, a voltage of 12 kV is applied to the gate 24, and a voltage of 10 kV is applied to the metal pad 17. That is, the voltage applied to the gate 24 is set to be higher than the voltage applied to the first substrate 10, and is set to, for example, 1.2 to 5 times. In the above-mentioned SED, the cathode voltage is applied to the phosphor screen 16 and the metal pad 17 when a daylight image is displayed, and the anode beam B 俾 emitted from the electron emitting element 18 is accelerated by the anode voltage to collide with the fluorescent light. Body screen 1 6. As a result, the phosphor layer of the phosphor screen 16 is excited to emit light, and a day image is displayed. A method for manufacturing the SED constructed as described above will be described below. When manufacturing the spacer assembly 22, first, a grid 24 of a specific size is prepared, and it has rectangular plate-like first and second dies approximately the same size as the grid and not shown. At this time, after degreasing, washing, and drying a thin plate having a thickness of 0.1 to 2 mm composed of Fe-50% Ni, an electron beam passage hole 26 and a gap wall opening 28 are formed by etching to serve as the grid 24. Then, the entire gate electrode 24 is oxidized by an oxidation treatment, and the insulating film is formed on the gate surface including the inner surface of the electron beam passage hole 26 and the spacer opening 28 (9) (9) 200400530. Furthermore, a liquid on which fine particles of tin oxide and antimony oxide are dispersed is sprayed on the upper surface of the insulating film, and dried and fired to form a resistive film. The first and second molds have a plurality of through-holes having a partition wall opening 28 corresponding to the grid 24, respectively. In the first mold and the second mold, at least the inner surface of the plurality of through holes corresponding to the partition wall openings 28 is coated with a resin that is thermally decomposed by heat treatment. In addition, the first mold is closely adhered to the first surface 24a of the grid in a state where each through hole is aligned with the gap wall openings 28 of the grid 24. Similarly, the second mold is closely adhered to the second surface 24b of the gate electrode in a state where each through hole is aligned with the gap wall openings 28 of the gate electrode 24. In this manner, the first mold, the grid 24, and the second mold are fixed to each other using a positioner or the like (not shown). Then, for example, a paste-like gap wall forming material is supplied from the outer side of the first mold, and the gap wall forming material is filled in the through holes of the first mold, the gap wall openings 28 of the grid 24, and the second mold. Through hole. As the material for forming the partition wall, at least a UV-curable adhesive (organic component) and a glass paste containing glass frit materials are used. Then, for the filled gap forming material, ultraviolet rays (υν) are irradiated from the outer surfaces of the first and second molds as radiation, and 俾 υV hardens the gap forming material. After that, heat curing may be performed as necessary. Then, the resin applied to each of the through holes of the first mold and the second mold is thermally decomposed by heat treatment, a gap is formed between the spacer forming material and the mold, and the first and second molds are peeled from the grid 24. Then, 'the grid filled with the spacer-forming material -14-(10) (10) 200400530 pole 2 4' heated in a heating furnace after the adhesive is flew out of the spacer-forming material, and the temperature is about 500 to 5 5 Forming the gap-forming material is carried out at 0 ° C for 30 minutes to one hour. As a result, a spacer assembly 22 having the i-th and second spacers 30a, 30b formed on the grid 24 is obtained. On the other hand, a first substrate 10 provided with a phosphor screen 16 and a metal pad 17 and a second substrate 12 provided with an electron emission element 18 and a wiring 21 and bonded to a side wall 14 are prepared in advance. Then, a conductive paste is printed on the wiring 21 of the second substrate 12 to have a shape similar to that of the front end of the second partition wall 30b, and the thickness becomes 120 / zm. Then, the wiring 21 is dried and fired. A specific position on the conductive body 3 3 is formed. The indium powder required for the formation of the high relaxation layer 31 is applied to the extended ends of the first spacers 30a. Thereafter, the partition wall assembly 22 configured as described above is positioned on the second substrate 12. At this time, the extended end of the second gap wall 30b can be positioned to contact the conductive body 33 to position the gap wall assembly 22 respectively. In this state, the first substrate 10, the second substrate 12 and the spacer assembly 22 are placed in a vacuum chamber, and the vacuum chamber is evacuated, and then the first substrate is bonded to the second substrate via the side wall 14. Simultaneously, the indium powder 'melted on the extended end of the first partition wall 30a is melted to crush the first substrate 10 to correct the height. Thereby, the SED including the gap wall mounting 22 can be manufactured. As shown in FIG. 3, according to the SED structured as described above, the electron beam B emitted from the electron emitting element 18 located near the second gap wall 30b is formed by forming a delay provided on the second gap wall 30b. The electric field in the conductor layer between the output end and the second substrate 12 is repelled. One side adopts the -15- (11) (11) 200400530 orbiting direction away from the second gap wall, and one side faces the electron beam passage hole 26. Then, the electron beam B is attracted by the charged second gap wall 30b and the first gap wall 30a this time, and will take an orbit close to the direction of these gap walls. In this way, by the repulsion and the deviation of the orbit of attracting the canceled electron beam B, the electron beam B emitted from the electron emitting element 18 finally reaches the phosphor layer which is the target of the phosphor screen 16 . Specifically, the smaller the distance from the electron emitting element to the side of the gap wall, the larger the amount of the electron beam moved to the side of the gap wall. On the contrary, when the distance from the side of the gap wall is sufficiently large, the electron beam moves to the Amount is a negligible amount. The movement of the electron beam occurs when the secondary electrons and reflected electrons on the fluorescent surface collide with the gap wall and the gap wall is charged. At this time, the secondary electron emission constant from the accelerating voltage used by the SED to the surface of the gap wall is 1 or more, and the side wall of the gap wall is positively charged 'so that the electron beam can be drawn to the side of the gap wall. In this embodiment, a conductive body 33 is provided between the second substrate-side end of the gap wall having a small electron velocity and the second substrate. The conductive body 33 forms a direction in which the electron beam and the gap wall repel. Electric field. By controlling the height of the conductor 33 to change the strength of the electric field ', the amount of repulsion can be controlled. In this way, "in this embodiment, the charging of the gap wall is not avoided", and the orbital deviation of the electron beam is offset by the attraction of the gap wall and the repulsion by the electron beam 33. Therefore, according to the above-mentioned SED, it is not necessary to provide a complicated mechanism for converging an electron beam such as an electron gun of a CRT. In this way, the first and second gap walls 30a 'and 3Ob are charged in accordance with the above-mentioned SED', and when these electron beams are brought closer by these gap walls', the orbit of the electron beam can be prevented from deviating. This prevents the deviation of the electron beam B from landing, and as a result (12) (12) 200400530, the deterioration of color purity is reduced, and the image quality can be improved. When all or a part of the surface of the gap wall is directly subjected to a conductive treatment, the reactive current flowing from the first substrate through the gap wall to the second substrate increases, resulting in temperature rise or increased power consumption. In addition, the conductive processing unit becomes a gas generation source during the operation of the SED, and ions of an electron source near the gap wall may collide. In this regard, according to this embodiment, no increase in ineffective current, increase in temperature, increase in power consumption, or collision of ions occurs, and the orbit of the electron beam can be easily controlled by changing the electric field around the gap with the conductor 33. The SED of this embodiment and the SED without the above-mentioned conductor 33 are prepared to compare the amount of movement of the electron beam. As a result, in the SED without the conductor, the electron beam moves 120 // m on the side of the gap wall. In the SED of this embodiment, the amount of movement of the electron beam becomes almost zero, and the color of the daytime image is improved. purity. According to the SED, the grid 24 is disposed between the first substrate 10 and the second substrate 12, and the height of the spacer 30a in the first figure is lower than the height of the second spacer 30b. Accordingly, the grid 24 is located closer to the first substrate 10 than the second substrate 12. Therefore, even when a discharge occurs from the first substrate 10 side, the gate 24 makes it possible to suppress the discharge damage of the electron emission element 18 provided on the second substrate 12. Therefore, it is possible to obtain an SED which is excellent in the withstand voltage of the discharge and has a good image quality. Furthermore, according to the SED having the above configuration, by forming the height of the first spacer 30a lower than that of the second spacer 30b, when the voltage applied to the gate 24 is larger than the voltage applied to the first substrate 10, The electrons generated from the electron emission element 18 (13) (13) 200400530 can be reliably reached to the screen side of the phosphor. In addition, in the case where the plurality of first spacers 30a have uneven heights, the unevenness can be absorbed by the height relaxation layer 31, and the plurality of first spacers 30 and the first substrate 10 can be reliably contacted. Therefore, the distance between the first substrate 10 and the second substrate 12 can be maintained uniformly in almost all areas by the i and second partition walls 30a and 30b. The SED of the second embodiment of the present invention will be described below. As shown in Fig. 4, according to the second embodiment, the conductor 33 is formed into a shape similar to the extending end of the second partition wall 30b by a metal or an alloy. For example, the conductor 33 is formed of a metal plate with a thickness of 200 / zm from Fe-50% Ni, and a fixed layer composed of a conductive glass frit, a conductive adhesive, and the like is fixed to the wiring of the second substrate 12 21 on. In this manner, the spacer assembly 22 is disposed between the first and second substrates 10, 12 in a state where the extended ends of the respective second spacers 30b are in contact with the conductors 33. The other configurations are the same as those of the first embodiment described above, and the same reference numerals are given to the same portions, and detailed descriptions thereof are omitted. When the SED of the second embodiment configured as described above is to be manufactured, the first and second substrates 10, 12 and the spacer assembly 22 are formed by the same process as the first embodiment. At this time, the height of the first partition wall 30a is 0.2 mm, and the height of the second partition wall 30b is made 1.0 mm. Then, at a predetermined position on the wiring 21 of the second substrate 12, a conductive adhesive having a thickness similar to that of the front end of the second partition wall 30b and a thickness of 5 // m is applied to form the fixing layer 40. In this way, after the conductive layer 33 having a thickness of 200 / z m composed of Fe-50% Ni is loaded on the fixed layer 40, the fixed layer is dried, and (14) (14) 200400530 conductive body 33 is fixed on the wiring. Thereafter, as in the first embodiment, the spacer assembly 22 is positioned and disposed on the second substrate 12. At this time, the partition wall device 22 is positioned so that the extended end of the second partition wall 30b is in contact with the conductor 33. In this state, the first substrate 10, the second substrate 12, and the spacer assembly 22 are arranged in a vacuum chamber, and after the vacuum chamber is evacuated, the first substrate is bonded to the second substrate via the side wall 14. Thereby, SED is manufactured. According to the SED structured above, the same effect as that of the first embodiment can be obtained. In the second embodiment, the conductor 3 3 can be fixed to the fixing layer 40 of the wiring 21. Use as a correction layer to correct uneven height of the gap wall. Therefore, high machining accuracy of the spacer is not required, and it is possible to reduce the manufacturing cost of the spacer.
又’準備第二實施形態SED，及未設有導電體33的SED ’來比較電子束的移動量。結果，在未設有導電體的SED， 電子束在間隙壁側移動的1 50 /z m，而在本實施形態的SED中 ’電子束的移動量幾乎成爲零，也改善了顯示晝像的色純度 〇 以下，針對於本發明的第三實施形態的SED加以說明。 如第4圖所示地，依照第2實施形態，導電體33是藉由金屬或 合金形成與第2間隙壁30b的延出端相似形狀。例如導電體33 是由Fe-50%Ni的厚度200 /zm的金屬板所形成，藉由絕緣性 黏接劑，例如藉由玻璃料玻璃所組成的固定層42被固定在第 2間隙壁30b的延出端。如此間隙壁裝配22是在導電體33所固 裝的各第2間隙壁30b的延出端抵接於第2基板12上的配線21 (15) (15)200400530 的狀態下，被配設在第丨及第2基板丨〇，丨2之間。 又’其他構成是與上述的第一實施形態相同，在相同 部分賦予相同的參照記號而省略其詳述。 欲製造如上述地所構成的第二實施形態的SED時，藉 由與第一實施形態同樣的工序，形成第1及第2基板10，12 及間隙壁裝配22。這時候，第1間隙壁30a的高度是作爲 0.2mm’而第2間隙壁30b的高度是作成1.0mm。 然後，在間隙壁裝配22的各第2間隙壁30b的前端，塗 佈玻璃料玻璃作爲固定層42。在固定層42上裝載Fe-5ONi 所組成的厚度200 // m的導電體33之後，乾燥固定層，藉由 燒成，俾將導電體3 3固裝在第2間隙壁30b前端。] 然後，將間隙壁裝配22定位配置在第2基板12上面。這 時候’使得導電體33所固裝的第2間隙壁30b的延出端分別 位於第2基板1 2的配線2 1上面地定位間隙壁裝配2 2。在該 狀態，將第1基板1 0，第2基板1 2及間隙壁裝配2 2配置在真 空室內，而真空排氣真空室內之後，將第1基板經由側壁 14接合於第2基板。由此，來製造SED。 又，依照如上所構成的SED，可得到與第一實施形態 同樣的作用效果。在第三實施形態中，可將導電體3 3固定 於第2間隙壁前端的固定層42，使用作爲修正間隙壁的高 度參差不齊的修正層。所以，不需要間隙壁的高加工精度 ，成爲可謀求減低間隙壁的製造成本。 又，準備第二實施形態SED，及未設有導電體33的SED ，來比較電子束的移動量。結果，在未設有導電體的SED， (16) (16)200400530 電子束在間隙壁側移動的1 50 // m，而在本實施形態的SED中 ’電子束的移動量幾乎成爲零，也改善了顯示畫像的色純度 〇 本發明是並不被限定於上述的實施形態，在本發明的範 圍內可進行各種變形。例如，本發明是並不被限定於具備柵 極的晝像顯示裝置，也可適用於未具有柵極的畫像顯示裝置 。這時候，分別使用一體地所形成的柱狀或板狀的間隙壁， 藉由在各間隙壁的第2基板側的前端與第2基板之間設置導電 體，可得到與上述同樣的作用效果。 又，在該發明中，間隙壁的直徑或高度，其他的構成要 素的尺寸，材質等是視需要可適當地選擇。又，在上述的實 施形態中，導電體是作成設於第2基板上的配線與間隙壁前 端之間的構成，惟並不被限定於配線上，而在迴避電子放出 元件的位置設在第2基板與間隙壁前端之間就可以。 電子源是並不被限定於表面傳導型電子放出元件，也可 適用電場放出型，使用電子放出於碳奈米管等的真空中的電 子源的FED等型式。 (產業上的利用可能性） 如上所詳述地，依照本發明，提供一種不會引起溫度上 昇或增加耗電，防止電子束的偏軌，提高畫像品位的畫像顯 示裝置及 【圖式簡單說明】 -21 - (17) (17)200400530 第1圖是表示本發明的實施形態的SED的立體圖。 第2圖是表示沿著第1圖的線II-II加以切剖的上述 SED的立體圖。 第3圖是表示放大上述SED的剖視圖。 第4圖是表示放大本發明的第二實施形態的SED的主 要部分的剖視圖。 第5圖是表示放大本發明的第三實施形態的SED的主 要部分的剖視圖。 [符號說明] 1 0 :第1基板 1 1 :黑色遮光層 1 2 :第2基板 14 :側壁 1 5 :真空外圍器 16 :螢光體 1 7 :金屬襯墊 1 8 :電子放出元件 2 0 :密封材 2 2 :間隙壁裝配 24 :柵極 2 6 :電子束通過孔 2 8 :間隙壁開孔 3 0 a :第1間隙壁 -22- (18) (18)200400530 3 0 b :第2間隙壁 3 1 :緩和層 3 3 :導電體 40，42 :固定層 5 〇 :電壓供給部 B :電子束Also, the SED of the second embodiment and the SED without the conductor 33 are prepared to compare the amount of movement of the electron beam. As a result, in the SED without a conductive body, the electron beam moves by 150 / zm on the side of the gap wall. In the SED of this embodiment, the amount of movement of the electron beam is almost zero, and the color of the daytime image is improved. Purity 0 or less will be described for the SED according to the third embodiment of the present invention. As shown in Fig. 4, according to the second embodiment, the conductor 33 is formed into a shape similar to the extending end of the second partition wall 30b by a metal or an alloy. For example, the conductor 33 is formed of a metal plate having a thickness of 200 / zm from Fe-50% Ni, and is fixed to the second partition wall 30b by an insulating adhesive such as a fixing layer 42 composed of frit glass. Extended end. In this manner, the spacer assembly 22 is disposed in a state where the extended ends of the second spacers 30b fixed by the conductor 33 are in contact with the wiring 21 (15) (15) 200400530 on the second substrate 12. Between the second and second substrates 丨 0, 丨 2. The other configuration is the same as that of the first embodiment described above, and the same reference numerals are given to the same portions and detailed descriptions thereof are omitted. When the SED of the second embodiment configured as described above is to be manufactured, the first and second substrates 10, 12 and the spacer assembly 22 are formed by the same process as the first embodiment. At this time, the height of the first partition wall 30a is 0.2 mm 'and the height of the second partition wall 30b is made 1.0 mm. Then, a frit glass is applied as a fixed layer 42 to the front end of each of the second partition walls 30b of the partition wall assembly 22. After the conductive layer 33 having a thickness of 200 // m made of Fe-5ONi is loaded on the fixed layer 42, the fixed layer is dried, and the conductive body 33 is fixed to the front end of the second gap wall 30b by firing. Then, the spacer assembly 22 is positioned and disposed on the second substrate 12. At this time ', the extending ends of the second spacers 30b fixed by the conductors 33 are positioned on the wirings 21 of the second substrate 12 to position the spacers 22, respectively. In this state, the first substrate 10, the second substrate 12 and the spacer assembly 22 are placed in a vacuum chamber, and after the vacuum chamber is evacuated, the first substrate is bonded to the second substrate via the side wall 14. Thereby, SED is manufactured. According to the SED structured as described above, the same effects as those of the first embodiment can be obtained. In the third embodiment, the conductor 33 can be fixed to the fixing layer 42 at the front end of the second gap wall, and a correction layer for correcting the uneven height of the gap wall can be used. Therefore, the high machining accuracy of the gap wall is not required, and it is possible to reduce the manufacturing cost of the gap wall. In addition, the SED of the second embodiment and the SED without the conductor 33 were prepared to compare the amount of movement of the electron beam. As a result, in a SED without a conductive body, the (16) (16) 200400530 electron beam moves 1 50 // m on the side of the gap wall, and in the SED of this embodiment, the amount of movement of the electron beam becomes almost zero. The color purity of the displayed image is also improved. The present invention is not limited to the embodiment described above, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to a daylight image display device provided with a grid electrode, and is also applicable to an image display device without a grid electrode. In this case, a columnar or plate-shaped spacer formed integrally is used, and a conductive body is provided between the front end of the second substrate side of each spacer and the second substrate, so that the same effect as the above can be obtained. . In this invention, the diameter or height of the partition wall, the dimensions and materials of other constituent elements can be appropriately selected as necessary. In addition, in the above-mentioned embodiment, the conductor is configured to be provided between the wiring provided on the second substrate and the front end of the gap wall. However, the conductor is not limited to the wiring. 2 between the substrate and the front end of the spacer. The electron source is not limited to a surface-conduction type electron emission element, and an electric field emission type may also be applied. A type such as FED is used in which electrons are emitted from a vacuum source such as a carbon nanotube. (Industrial Applicability) As described in detail above, according to the present invention, there is provided an image display device which does not cause temperature rise or increase power consumption, prevents deflection of an electron beam, and improves image quality. -21-(17) (17) 200400530 Fig. 1 is a perspective view showing a SED according to an embodiment of the present invention. Fig. 2 is a perspective view showing the SED taken along a line II-II in Fig. 1. FIG. 3 is a cross-sectional view showing the SED in an enlarged manner. Fig. 4 is a cross-sectional view showing a main part of an SED according to a second embodiment of the present invention enlarged. Fig. 5 is a cross-sectional view showing a main part of an SED according to a third embodiment of the present invention in an enlarged manner. [Description of Symbols] 1: 1st substrate 1 1: Black light-shielding layer 1 2: 2nd substrate 14: Side wall 1 5: Vacuum peripheral 16: Phosphor 1 7: Metal pad 1 8: Electron emitting element 2 0 : Sealing material 2 2: Spacer wall assembly 24: Grid 2 6: Electron beam passing hole 2 8: Spacer wall opening 3 0 a: 1st spacer -22- (18) (18) 200400530 3 0 b: No. 2 Spacer wall 3 1: Relief layer 3 3: Conductor 40, 42: Fixed layer 5 〇: Voltage supply unit B: Electron beam
-23--twenty three-