SU720766A1

SU720766A1 - Device for timing measuring trains

Info

Publication number: SU720766A1
Application number: SU782625394A
Authority: SU
Inventors: Евгений Вячеславович Титов
Original assignee: Предприятие П/Я Р-6609
Priority date: 1978-06-05
Filing date: 1978-06-05
Publication date: 1980-03-05

Description

Изобретение относится к системам ; связи с импульсно-кодовой модуляцией и может использоваться при контроле ' линейных трактов цифровых систем передачи.The invention relates to systems; communication with pulse-code modulation and can be used to control the 'linear paths of digital transmission systems.

Известно устройство синхронизации измерительных последовательностей, содержащее последовательно соединенные регистр сдвига, дешифратор и последовательно соединенные блок выделения сигнала, делитель частоты и блок совпадения, а также триггер, блок запрета и генератор эталонной последовательности [1].A known device for synchronizing measuring sequences, containing a series-connected shift register, a decoder and series-connected signal extraction unit, a frequency divider and a coincidence unit, as well as a trigger, a prohibition unit and a reference sequence generator [1].

Однако известное устройство имеет 15 значительное время вхождения в синхронизм.However, the known device has 15 significant time entry into synchronism.

Цель изобретения - сокращение в_ремени вхождения в синхронизм.The purpose of the invention is to reduce the time of entry into synchronism.

Для этого в устройство синхрониза-20 ции измерительных последовательностей, содержащее последовательно соединенные регистр сдвига, дешифратор и rtoследователь но соединенные блок выделения сигнала, делитель частоты и 25 блок совпадения, а также триггер, блок запрета и генератор эталонной последовательности, введен сумматор, объединенный по входу с блоксм выделения сигнала, выход которого подклю-30 чен. к входам блока запрета и регистра сдвига, другой вход которого соединен с'вых од см сумматора, другой вход которого через генератор эталонной последовательности соединен с выходом блока запрета, другой вход которого соединен с выходом блока совпадения, другой вход которого через триггер соединен с выходом дешифратора.For this, a synchronization device-20 measuring sequences, containing sequentially connected shift register, decoder and rto subsequently connected signal extraction unit, frequency divider and 25 coincidence unit, as well as a trigger, inhibit unit and a reference sequence generator, an adder combined at the input with a block of signal isolation, the output of which is connected to 30 chen. to the inputs of the prohibition block and the shift register, the other input of which is connected to the last one adder, the other input of which is connected through the generator of the reference sequence to the output of the prohibition block, the other input of which is connected to the output of the coincidence block, the other input of which is connected via the trigger to the decoder output .

На чертеже представлена структурная электрическая схема предложенного устройства. /The drawing shows a structural electrical diagram of the proposed device. /

Схема устройства синхронизации измерительных последовательностей содержит последовательно соединенные регистр 1 сдвига, дешифратор 2 и триггер 3, последовательно соединенные блок 4 выделения сигнала, делитель 5 частоты и блок б совпадения, блок 7 запрета, генератор 8 эталонной последовательности и сумматор 9.The circuit of the measuring sequence synchronization device comprises a shift register 1, a decoder 2 and a trigger 3 connected in series, a signal extraction unit 4, a frequency divider 5 and a matching block b, a block 7, a reference sequence generator 8 and an adder 9, connected in series.

Устройство работает следующим образом.The device operates as follows.

В сумматоре 9 (по модулю два) осуществляется поразрядное сравнение .In adder 9 (modulo two), bitwise comparison is performed.

контрольного сигнала, приходящего из линии, и эталонного сигнала, формируемого генератором 8 эталонной последовательности. Прй поступлении на вход синхронизации триггера 3 импуль•V са ''синхронизация'' на выходе триггера 3 появляется единичный потенциал, разрешающий прохождение через блок 6 Совпадения сигнала с делителя 5 частоты. Сигнал с делителя 5 частоты поступает на вход блока 7 запрета, на другой вход которого поступают тактовые импульсы с блока 4 выделения· сигнала, и на выходе блока 7 запрета ........появляется пОёлёдоватёльность такто•-’-в'Ёбс' ййпульсов с запрещенным тактом, за счет чего и осуществляется временной сдвиг эталонного сигнала, формируемого генератором 8 эталонной последовательности относительно сигнала, приходящего из линии. При наличии достаточного для данной структуры сигналов числа совпадений, фиксируемых регистром .1 сдвига, на выходе дешифратора 2 формируется сигнал, , который возвращает триггер 3 в нулевое состояние, что означает Окончание процесса синхронизации .the control signal coming from the line, and the reference signal generated by the generator 8 of the reference sequence. When a trigger 3 pulse is input to the trigger synchronization input • V CA “synchronization”, a single potential appears at the output of trigger 3, allowing passage through block 6 of the signal coincidence with the frequency divider 5. The signal from the frequency divider 5 is fed to the input of the prohibition unit 7, to the other input of which clock pulses are received from the signal extraction unit 4, and at the output of the prohibition unit 7 ........ The clock cycle appears • -'- v'Ebs 'yypulsov with a prohibited cycle, due to which the time shift of the reference signal generated by the generator 8 of the reference sequence relative to the signal coming from the line. If there is a sufficient number of matches for the signal structure recorded by the shift register .1, a signal is generated at the output of the decoder 2, which returns trigger 3 to the zero state, which means the end of the synchronization process.

Введение сумматора, объединенного по входу с блоком выделения сигнала, и новые связи между другими блоками устройства позволяют основывать процесс синхронизации на выявлении достаточного для данной структуры сигналов числа совпадений, что сокращает время вхождения в синхронизм.The introduction of an adder, combined at the input with the signal extraction unit, and new connections between other units of the device allow us to base the synchronization process on identifying a sufficient number of matches for this signal structure, which reduces the time it takes to synchronize.

Claims

The invention relates to communication systems with pulse-code modulation and can be used to monitor the linear paths of digital transmission systems. A device for synchronization of measuring sequences is known, comprising a serially connected shift register, a decoder and a serially connected signal extraction unit, a frequency divider and a matching unit, as well as a trigger, a block for a gret and a generator of the reference sequence 1. However, the known device has a significant timing. The purpose of the invention is to reduce the time to synchronize. To do this, an adder integrated in the input with the signal extraction unit is inserted into the synchronization device of the measuring sequence containing the sequentially connected shift register, the decoder and the subsequently connected signal extraction unit, the frequency divider and the matching unit the output of which is connected to the inputs of the prohibition block and the shift register, another input is connected to the output of the adder, the other input of which is through the reference generator after This is connected to the output of the prohibition block, the other input of which is connected to the output of the coincidence unit, the other input of which through a trigger is connected to the output of the decoder. The drawing shows the structural electrical circuit of the proposed device. The device diagram of the synchronization measurement sequence 1 contains serially connected shift register 1, decoder 2 and trigger 3, the signal extraction unit 4, the divider 5 and the match unit 6, the inhibitor block 7, the generator 8 of the reference sequence and the adder 9. The device operates as follows zetl In adder 9 (modulo two) a bitwise comparison is made. the control signal coming from the line, and the reference signal generated by the generator 8 of the reference sequence. When a synchronization pulse arrives at the sync trigger input 3, a single potential appears at the output of trigger 3, allowing the passage through the block 6 of the signal falling from the frequency divider 5. The signal from the 5 part divider is fed to the input of block 7 of the prohibition to another input of which clock pulses are received from the signal extraction block 4, and the output of block 7 is stopped by a block of 11 belective tact clock; yypulbsov With aapregtsenny taksm, due to which a temporary shift of the reference signal generated by the generator 8 of the reference signal generated by the satellite by the signal coming from the line. If there is a sufficient number of coincidences for this signal structure fixed by the register .1 food yoke, a signal is generated at the output of the decoder 2, which returns trigger 3 to the zero state, which means the termination of the signaling system; SyyHronizgaKyi. : .The introduction of an adder, combined with a p6 input with a signal extraction block, and new connections between other units of the device do not have to base the synchronization process on finding the number of coincidences sufficient for a given signal structure, which shortens the timing. Claims The device of synchronization of measuring sequences, containing sequentially connected shift register, decoder and serially connected signal extraction unit, frequency divider and coincidence unit, as well as trigger, prohibition unit and reference generator, characterized in that in order to synchronize time , entered adder, combined on the input with the block selection signal, the output of which is connected to the inputs of the prohibition block and the shift register, the other input It is connected to the output of an adder, another input of which is connected to the output of a prohibition block through a generator 15th terminal, another input of which is connected to the output of a coincidence unit, another input which is connected via a trigger to the output of a decoder. .. Sources of information taken into account in the examination of 1, Levin, LS, Plotkin, MA, Basics of building digital transmission systems. M., Holy Hail 1975, p. 119 (prototype).