SU1160551A2 - Device for synchronizing pulse sequences - Google Patents

Abstract

DEVICE FOR SYNCHRONIZATION OF PULSE SEQUENCES on aut. St. No. 748838, characterized in that, in order to increase the operation stability of the device, a delay element is additionally inserted in it, which is connected between the clock input and the additional input of the fourth And element, in addition, the sync bus is connected to the input of the synchro generator.

Description

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The invention relates to the field of pulsed technology and can be used in the construction of equipment for testing and tuning the equipment of digital communication systems and computing equipment.

According to the main author. St. No. 748838, a device for synchronizing pulse sequences, containing a clock frequency extractor, the output of which is connected to the information input of the inhibit element, the output of which is connected to the first input of the mismatch element, four AND elements, two RS triggers, clock generator, shift register , the clock input of which is connected to the output of the clock frequency selector, and the direct output of the first bit and the inverse output of the second bit through the first And element are connected to the another entry of the element for; preta and S-input of the first RS-flip-flop. The output of the clock selector is connected to the input bus and the second input of the mismatch element. The inputs of the second element And are connected respectively to the outputs of the second RS trigger, the mismatch element and the synchronous generator, whose output through the inverter is connected to the first inputs of the third and fourth elements And, the second inputs of which are connected respectively to the direct and inverse outputs of the first trigger R-input of which with the output of the second element I. The output of the third element And is connected to the information input of the shift register, the output of the fourth element And - with 8-input of the second trigger, the R-input of which is connected to the bus is synchronized 1. However, in the known device possible false synchronization. The start of synchronization signal 6 can arrive at any moment of time, including at the end of the pulse at the output of the synchronous generator, during which it is determined whether the input and reference sequences coincide or not in phase. In this case, even if the phase of these sequences does not match, a false end of synchronization is possible due to the partial coincidence of the compared fragments. In addition, premature termination of synchronization is possible with a long duration of the pause at the output of the synchro-generator. The aim of the invention is to increase the stability of the device. FIG. 1 is a block diagram of the device; in fig. 2 - plots showing his work.

The device contains 1 clock frequency selector, prohibition element 2, gene-. Ratio 3 reference, Element 4 mismatch, Elements 5-8, two RS flip-flops 9 and 10, clock generator 11 shift register 12, input bus 13, inverter 14, clock 15, delay element 16 and output bus 17. Exhaust input 1 clock frequency is connected to the input bus 13 and the first input of the mismatch element 4. The output of the selector 1 is connected to the synchronization input of the shift register 12 and to the information input of the prohibition element 2, the output of which is through the reference generator 3

the sequence is connected to the second input of mismatch element 4, the output of which is connected to the input of element 6, the other inputs of which are connected respectively to the output of trigger 10 and to the output of synchronous generator 11. The output of synchronous generator 11 is also connected via inverter 14 to the first inputs of elements 7 and 8, the second inputs of which are connected to the direct and inverse outputs of the RS flip-flop 9, respectively, and the third additional input of the And 8 element is connected to the synchronous generator 11 through the delay element 16. The output of the And 8 element is connected to the S-input of the trigger 10, the R-input of which is connected to the synchronization thickness 15 and to the input of the clock generator installation I. The output of the And 7 element is connected to the information input of the shift register 12, the direct output of which is the first bit and the inverse output the second bit is connected to the inputs of the element And 5, the output of which is connected to the prohibitory input of the element 2

prohibition and S-input trigger 9, the R-input of which is connected to the output element And 6. The device operates as follows. The measuring sequence (Fig. 2a) is fed to the bus 13. At the output of the selector 1, clock pulses are formed (Fig. 26) corresponding to this measuring sequence. Through the prohibition element, controlled by the signal from the output of the element And 5, the clock pulses (Fig. 2c) trigger the generator 3 of the reference sequence. On the discrepancy element 4, the measuring (Fig. 2a) and reference (Fig. 2d) sequences are compared. The signals from the output of the mismatch element 4 (Fig. 2e) are fed to the input of the element And 6, to the other inputs of which the signals from the outputs of the clock generator 11 (Fig. 2e) and the trigger 10 (Fig. 2g) are received, on. the inputs of which are given signals from the bus 15 (Fig. 2h) about the start of the synchronization process and the output of the And 8 element (Fig. 2i) about the completion of the synchronization process. Signal generated by i

Claims (1)

DEVICE FOR SYNCHRONIZING PULSE SEQUENCES according to ed. St. No. 748838, characterized in that, in order to increase the stability of the device, a delay element is additionally inserted into it, which is connected between the output of the sync generator and the additional input of the fourth element And, in addition, the synchronization bus is connected to the input of the sync generator. Figure 1 I