SU1140250A1 - Synchronizing signal generator of synchronous network - Google Patents

Abstract

1. SYNCHROGENERATOR SYNCHRONOUS NETWORK containing serially connected master oscillator, frequency divider and service signal conditioner unit, as well as sync driver and initial state conditioner, the output of which is connected to the second frequency dividers input, and the output of the sync signal generator and outputs of the service signalizer unit are, respectively, the sync output and the sync generator service signal outputs, which are used to increase the synchronization network synchronization helixes, the inhibited pulse generator and the clock signal analyzer, as well as the clock unit are inputted, while the output of the clock unit is connected to the combined inputs of the initial state unit and the clock signal analyzer, the second input of which is connected to the output of the clock generator, and the first and the second outputs of the clock analyzer are connected respectively to the control inputs of the initial state setup unit and driver clock signals whose clock inputs are connected to the corresponding frequency decoder code, the second clock driver output is connected to the inhibitor pulse driver input, and the clock signal input and clock input unit are connected to the clock generator output and the second clock generator output, respectively. 2. The clock generator according to claim 1, characterized in that the clock signal analyzer contains serially connected unit for (L support, the first I-NB element and D trigger, as well as the second AND-NOT element, the first input and output of which are connected respectively to the forward In the code and R input of the ID of the trigger, -NHH-. The full output of the D of the trigger is connected to the second input of the first element AND-NO, and the input of the delay unit is connected to the second input of the second element AND-NOT, and the input of the input unit, C-input The D-trigger and the third input of the second NAND element are respectively The first, second, and third inputs of the sync signal analyzer, and the inverse and direct outputs; D-trigger, respectively, the first and second outputs of the sync signal analyzer. 3, The sync generator according to claim 1, characterized in that the inhibitor pulse driver is pulse expander.

Description

11 The invention relates to telecommunication technology and can be used as part of installations in order to ensure their synchronous interaction, in particular, as part of application television installations operating in a common synchronous network. A synchronous network synchronous generator is known, containing a series-connected frequency divider, a clock generator, and an initial state setting unit, the output of which is connected to the setup input of the frequency divider ij. A disadvantage of the known synchronous generator synchronous network is the low reliability of synchronization of the synchronous network. The closest to the invention is a synchronous network synchronization generator, containing serially connected master oscillator, frequency divider and auxiliary signals shaper unit, as well as a sync shaper unit and a source state laziness setting unit, the output of which is connected to the second input of the frequency divider, and the sync shaper output and the outputs of the signal driver unit are respectively the output of the clock signals and the outputs of the service signals of the clock generator, and the first and volts are swarm inputs of establishing the initial state are respectively connected to the second output of the oscillator and the output clock signal to shape bodies 2j. The purpose of the Invention is to improve the synchronization network synchronization reliability. This goal is achieved by a network containing serially connected master oscillator, frequency divider and block of service signal drivers, as well as a clock generator and an initial state establishment unit, during which the frequency divider is connected to the second input of the clock generator and the output of the driver unit service signals are, respectively, the output of the sync signals and the outputs of the service signals of the sync generator; banning pulses and a sync signal analyzer, as well. the clock unit, while the output of the clock unit is connected to the combined inputs of the initial state unit and the clock analyzer, the second input of which is connected to the code of the clock generator, and the first and second outputs of the clock analyzer are connected respectively to the control inputs of the initial state unit and the driver clock signals, the clock inputs of which are connected to the corresponding outputs of the frequency divider, the second output of the clock signal generator is connected to the input of the inhibitor pulse generator, and the clock signal input and the clock input of the clock unit are connected respectively to the output of the clock signal generator and the second code of the master oscillator. The sync signal analyzer contains a delayed unit connected in series, the first NAND element and D are the trigger, as well as the second NAND element, the first input and output of which are connected respectively to the direct output and the R input of the C flip-flop. connected to the second input of the first NAND element, and the input of the delay unit is connected to the second input of the second NAND element, the input of the delay unit, the C input of the O-trigger and the third input of the second AND element are respectively the first, second and the third input of the synchro analyzer latter is present, and the forward and inverse outputs of the flip-flop 35 are respectively first and second clock outputs analyzer. The inhibitor pulse shaper is designed as a pulse expander. FIG. Figure 1 shows the structural electrical circuit of the synchronous network synchronous generator; in fig. 2 timing diagrams explaining the operation of the synchronous network synchronous generator. The synchronous generator synchronous network contains a block of 1 clock, a block 2 of establishing the initial state, a master oscillator 3, an analyzer 4 clock signals, a divider 5 frequencies. shaper 6 prohibition pulses. driver 7 clock signals and a block of 8 drivers service signals. The sync signal analyzer 4 contains a delay block 9, the first element 10 is NAND, the second element 11 NAND and D is a trigger 12. The synchronous network sigenerator operates as follows. The master oscillator 3 generates a sequence of clock pulses (Fig. 2a). A frequency divider 5 generates a series of sequences of clock pulses having a multiple value of the following frequency. The block 8 and the driver 7, on the basis of the sequences of the clock pulses, generate, respectively, service pulses and synchronization pulses (sync signals). The signals from the outputs of the block 8 and the form of the rotor 7 are transmitted via the trunk (multi-wire) bus to the installation device serviced by the synchronous network synchronous generator. To ensure synchronous operation of all network settings, the inputs of the synchronous network synchronous generators included in their structure are connected to a common distribution bus (1PC). The sync signals acting in the UJPC arrive at analyzer 4 through a block of 1 clock, thereby eliminating the incorrect operation of analyzer 4 due to the random phase shift of external clock signals. When analyzer 4 is running, the following alternative 1 CRS states are possible: lack of sync signals (Q); the presence of its own clock signals (S); the presence of the sync signals of another synchronous network synchronous generator (6); the presence of interference of several sync signals in the case of q IlPC analysis of the sync signal torus generates a command that, under the action of which shaper 7, begins to force its own sync signals to IlPC. After this, analyzer 4 ascertains the condition corresponding to the operation of the synchronous generator of the synchronous network in the master (autonomous) mode. When a synchronous network synchronous network generates other signals in analyzer 4, analyzer 4 should record the state 1 of the interference of the clock signals and the corresponding command to the driver 7 to stop outputting its own clock signals to the SRS. The moments of the decision to stop issuing the clock signals to the network for different synchronous generators of the synchronous network will not be the same. If the synchronous generators are switched off sequentially, the last of them will no longer register interference at the moment of making a decision. Therefore, analyzer 4 of the last synchronous generator of the synchronous network will not fix state 1, but state 8 and this synchronous generator of the synchronous network will become the leader in the network. Analyzers 4 other synchronous network synchronous generators, after termination of their own sync signals, will register the state S corresponding to the slave mode of operation. In this mode, the analyzer 4 issues a command to the initial state setting unit 2, which allows the formation of a signal to bring the frequency divider 5 to the initial state, which causes a forced phasing of all generated service signals. Thus, the described interaction of the analyzer 4 and the former 7 provides a decentralized automatic implementation of the main control function of the synchronous network — a gap. Because of the unlimited speed of real radio elements, the temporal resolution of analyzer 4 is not infinite, therefore, there is a nonzero probability of simultaneously registering a state in the synchronous network interfering generators if they are sufficiently close. In this case, all of them will stop introducing their own sync signals into the network, and therefore the next cycle will state a (no sync signals), with the result that all synchronous generators of the synchronous network will almost simultaneously decide on their own sync signals, and the entire network will return to interference state. In order to avoid cyclic repetition of such processes, it is necessary to ensure

the difference in the conditions for registering other people's sync signals when their phase difference between x and their own sync signals is concerned.

The reason for this difference is the natural phase incursion in the master oscillators 3 that are not related to each other. As long as the phase difference does not exceed the period of the clock frequency, the network state is indistinguishable from the synchronous one. But when the phase incursion exceeds the duration of the clock frequency period, it is impossible to allow simultaneous recording of state 1 in all interacting synchronous generators of the synchronous network, otherwise the process of state search will not stop.

To do this, it is necessary to block the action of the analyzer 4 for several cycles or before the transfer begins.

own sync signal, or immediately after it ends.

To block the interference analysis, a synchronization network shaper 6 is inserted into the inhibitor pulse generator 6, the output of which is connected to the third input of the analyzer 4. Since the analysis blocking interval is set after the termination of the sync pulse, an extension of the sync signals is used for generating the inhibit pulses, for which the input of the imaging unit 6 is connected to the frequency divider 5 through the imaging unit 7 ,.

To ensure that all synchronous network synchronous generators can be identically connected to L4PC, the drivers 7 (the outputs of which are combined) must be implemented according to the open output scheme, which is connected via a resistor to the power supply.

Analyzer 4 contains a D.-trigger 12, the state of which is determined by the master (log.1) or slave (.0) operation mode of the synchronous network synchronous generator. On the C-input B-trigger 12 receives the sync signal. shaper 7. FIG. 26 shows the starting and ending portions 50 of this sync signal. The clock fronts should correspond to the middle of the interval between the timing points in the timing unit 1, since this achieves the necessary left-hand timing of the timing error. The output of block 1 clocking synchronization signal

turns out to be tied to the timing points and takes the form, for example, shown in FIG. 2d,

In the master mode (state ShRS 5)

element 10 is NOT closed by applying a logic level zero to the second input, so that at the time of acting on the C input 3) -thrigger 12 rewrites the level of the logical unit from the II input. Change in state of the D trigger 12

can only occur at the R input when element 11 NAND is triggered, the third input of which is supplied with an enable signal from the direct output of the B trigger of trigger 12. The second input of element 11 NI implies a inhibit impulse from form 6, shown in FIG. 2g. Its overlap in time with its own sync signal (Fig.26)

Termination of the interaction of own private signals with external ones. It is not possible to determine the presence of the latter while maintaining the level of the logical Zero driver 7.

Thus, the change in the state of the -D-trigger 12 is possible only when the logical unit enters the first input of the AND-NE element 11 outside the interval of the action of the inhibit pulses (Fig. 2g), i.e. when the interfering clock signal of the other synchronous generator of the synchronous network appears in lUPC (state ShRS 2). In this case, the B-trigger 11 will be set to the logical zero state, in which the analyzer 4 executes the command to disable its own synchronization signals to the driver 7 and the block enable command 2 establish the initial state, opening the sequence of the pulses to establish the initial state (Fig. 2e) on the frequency divider 5.

After using the commands, the synchronous network synchronous generator will go into slave mode. The D-trigger 12 at the moment of termination of its own clock signal (Fig. 26) will fix the logic zero level at the D-input, indicating the presence of the clock signals of the other synchronous generator of the synchronous network (state b). To ensure stable maintenance of the slave mode with random frequency deviations of clock pulses and in the presence of distortions of the form propagated through the network, it is synodic, since the nonlinear signal nature of the signal at T) -input D of trigger 12 (Fig. 2e) is inverted (element 10 AND-NOT ) and delayed (delay block 9) with respect to the signal at the input of the analyzer 4 (Fig. 2d). In the case of the disappearance of external clock pulses, the level of logic unit 1 will be recorded through the D input to the D trigger 12; s (UIPC state q), which commands are issued to enable the issuance of its own clock signals by the driver 7 and to block the operation of the block 2, After the commands are executed, the clock generator will go to the master (SHRS U state).

The proposed synchronous network synchronous generator as compared to the known synchronous network synchronous generator provides a higher reliability of network settings by implementing the functions of decentralized control of network operation modes (synchronization).

Claims (3)

1. SYNCHRONOUS SYNCHRONOUS NETWORK comprising serially connected a master oscillator, a frequency divider and an auxiliary signal conditioner unit, as well as a clock conditioner and an initial state setting unit, the output of which is connected to the second input of the frequency divider, and the output of the synchronizer and the outputs of the auxiliary signal former respectively, the output of the clock signals and the outputs of the service signals of the clock generator, characterized in that ·, in order to increase the reliability of synchronization of the synchronous network, a sequentially interlocked pulse shaper and a clock analyzer, as well as a clock block are introduced, while the output of the clock block is connected to the combined inputs of the initial state block and the clock analyzer, the second input of which is connected to the output of the clock shaper, and the first and second outputs all sub- timing analyzer ¹ are united respectively to the control inputs of the block and establish the initial state of the clock shaper, t whose actuation inputs are connected to the corresponding outputs of the frequency divider, the second output of the clock generator is connected to the input of the inhibit pulse generator, and the clock input and clock input of the clock block are connected respectively to the output of the clock generator and the second output of the master oscillator. 2. The clock generator according to claim 1, characterized in that the clock analyzer contains a series-connected delay unit, the first AND-NOT and B trigger element, as well as the second AND-NOT element, the first input and output of which are connected respectively to the direct output and R -input Ό -trigger. the versioned output of the D-trigger is connected to the second input of the first AND-NOT element, and the input of the delay unit is connected to the second input of the second AND-NOT element, and the input of the delay block, the C input of the G-trigger and the third input of the second AND-NOT element are respectively the first, second and third inputs of the clock analyzer, and the inverse and direct outputs of the D-trigger are respectively the first and ΒΤορέΐΜ outputs of the clock analyzer. 3. The sync generator according to claim 1, characterized in that the prohibition pulse shaper is made in the form of a pulse expander.