SU511715A1 - Signal synchronization device - Google Patents

Description

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The invention relates to a telegraph link, namely to devices intended to synchronize signals. A device for synchronizing signals in multicast communication systems with channel timing is known, comprising a series-connected unit for synchronizing signals, a phase discriminator, a reversible counter, a controller with a generator, and a controlled divider whose outputs are connected to the second input of the phase discriminator.

However, the known device is characterized by considerable time spent on phasing.

The aim of the invention is to accelerate the phasing of signals from different channels. For this purpose, a ring register, a block for rewriting the code, a rewriting and advancing pulse shaper and a divider are entered into the device, the outputs and the setup inputs of each bit of the controlled divider are connected to the setup inputs via the block for rewriting the code

and the outputs of the corresponding gaps of the ring register, and the control inputs of the block for rewriting the code and the bus for pushing the pulses of the ring register are connected to the corresponding outputs of the shaper of the rewriting and advancing pulses connected to the output of the generator through a divider.

The drawing shows a structural electrical circuit of the device.

A device for synchronizing signals, contains a block 1 for extracting synchronization signals, a phase discriminator 2, a reversible counter 3, a generator 4, a controller 5, a controlled divider 6, a ring register 7, a block 8 for rewriting a code, a driver 9 for rewriting and advancing, and a divider ten.

Components 1, 2, 3, 4, 5, 6 devices form a known clock synchronizer. The outputs and setup inputs of each bit of the controlled divider 6 are connected via block 8 to the setup inputs and outputs of the corresponding bits of the ring register 7. Inputs designed to control the overwriting mode code

and the bus of the pushing pulses of the ring register 7 is connected to the corresponding outputs of the imaging unit 9, one of the inputs is connected through a divider to the output of evi: p, - ropa -4;:, 7ori ;: - to oli:; for the channel Sikhrokizadnp (not shown ).

The device works as follows

The device memorizes the file of the reference signal of the equalizer 6 at the end of each time channel and restores it at the beginning of the same channel through the operation cycle.

Let during the time of receiving information from one and subscribers in the corresponding time channel, the mismatch between the reference and input signals was eliminated. At the same time, the interleaved reference signal at the output of the divider 10 and the reference signal at the output of the controlled divider 6 establishes a certain phase shift. This phase shift corresponds to a certain code of the controlled divider 6 at the moments of the appearance of pulses at the output of the divider 10. This code at the end of the channel interval is entered into the ring register 7 by a code write pulse produced by the driver 9 and linked to the reference signal received from the transducer but phase divider Y.

The phase of the reference signal is set at the beginning of the time channel in the reverse order of the pulses, which sets the code in the control divider 6. This pulse also coincides with the reference signal.

The code slip in ring register 7 is performed by a burst of pulses next in the time interval between the recording pulse and the pulse setting the code.

The number of pulses in a pack is equal to the number of code elements. The selection of the length of the ring register 7 is made taking into account the number of channels and the required accuracy of the memory phase.

invention formula

A device for synchronizing signals in time-divided multicast communication systems, comprising a series-connected unit for generating synchronization signals, a phase discriminator, a reversible counter, a controller with a generator, and a controlled divider whose outputs are connected to a second input of the phase discriminator, characterized in that In order to accelerate the phasing of the signals of various channels, a ring register, a block for rewriting the code, a driver for rewriting and advancing are entered into it. A divider, the outputs and installation inputs of each bit of the controlled divider are connected to the installation inputs and outputs of the corresponding bits of the ring register through a block for code rewriting, and the control inputs of the block for code rewriting and the forward pulse of the ring register are connected to the corresponding outputs a driver for rewriting and advancing pulses connected to the generator output via a divider.

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