SU628628A1

SU628628A1 - Cycle synchronization arrangement

Info

Publication number: SU628628A1
Application number: SU772475702A
Authority: SU
Inventors: Станислав Никитович Осипов; Геннадий Григорьевич Морозов; Лендруш Нерсесович Оганян; Борис Николаевич Тихонов
Original assignee: Военная Ордена Ленина Краснознаменная Академия Связи Им.С.М.Буденного; Предприятие П/Я А-3592
Priority date: 1977-04-18
Filing date: 1977-04-18
Publication date: 1978-10-15

Description

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Изобретение относитс к радиотехнике и может использоватьс дл синхронизации приемных распределителей в- системах передачи дискретной информации.The invention relates to radio engineering and can be used to synchronize receiving distributors in discrete information transmission systems.

Известно устройство синхронизации по циклам, содержащее объединенные по информационному входу блок опознавани синхросигнала, распределитель и блок -выделени тактовой частоты, выход которого подключен к счетным входам первого и второго делителей частоты, к управл ющим входам делителей подключены соответственно выходы первого и второго блоков управлени , а выход блока опознавани синхросигнала подключен к первым входам первого и второго блоков управлени и анализатора, выход которого подключен к входу накопиуел , к второму входу второго блока упралле-. ни подключен выход первого делител частоты , а к управл ющим входам распределител подключены соответствующие выходы второго делител частоты 1.A cycle synchronization device is known, containing a sync signal identification block, a distributor and a clock frequency selection unit, the output of which is connected to the counting inputs of the first and second frequency dividers, connected to the control inputs of the dividers are connected to the control inputs of the divider respectively, and the output of the sync signal recognition unit is connected to the first inputs of the first and second control units and the analyzer, the output of which is connected to the accumulator input, to the second input The second unit is controlled. The output of the first frequency divider is not connected, and the corresponding outputs of the second frequency divider 1 are connected to the control inputs of the distributor.

Однако известное устройство обладает недостаточным .быстродействием.However, the known device has insufficient. Speed.

Цель изобретени - повышение быстродействи работы устройства.The purpose of the invention is to increase the speed of the device.

Дл этого в предлагаемом устройстве синхронизации,по циклам выход первого де .лител частоты подключен к второму-входу первого блока управлени и к-входу сброса накопител , выход которЬго подключен к третьему входу второго блока управлени .To do this, in the proposed synchronization device, the cycles of the output of the first frequency divider are connected to the second input of the first control unit and to the reset input of the accumulator, the output of which is connected to the third input of the second control unit.

На чертеже изображена структурна электрическа схема предлагаемого устройства .The drawing shows a structural electrical circuit of the proposed device.

Устройство содержит блок 1 опознабаии синхросигнала, распределитель 2, блок 3 выделени тактовой частоты, первый и второй делители частоты-4, 5, первый и второй блоки 6, 7 управлени ;анализатор 8, накопитель 9.The device contains a sync signal identification unit 1, a distributor 2, a clock frequency allocation unit 3, first and second frequency dividers-4, 5, first and second control blocks 6, 7; analyzer 8, accumulator 9.

Устройство работает следующим образом .The device works as follows.

Claims

The synchronization state is characterized by the coincidence in time of the pulses at the outputs of the first frequency divider 4 and the sync signal recognition unit 1. The analyzer 8 for each such coincidence generates a pulse at its first output, I enter. The accumulator 9 is sent to the counting input, while its output signal using the second unit 7 with the second frequency divider 5 ensures that the second frequency divider 5 is fully equipped with the first frequency divider 4. The distributor 2, controlled by the second frequency divider 5. ensures the correct selection of the group signal . Both in the case of clock signal distortion, and in the case of true synchronization, i.e., if a time shift error occurs during the transmission process, the next pulse coming from the output of the nepBOfx) frequency divider 4 does not come from the output of the clock identification unit 1. In this case, the analyzer 8 at its second run, generates a pulse, dumping drive 9, the output of which, after being reset by the second block 7 by the second frequency divider 5, provides the second frequency divider 5 with the opportunity to continue operation while maintaining the previous phase regardless of the first divider frequency 4. In addition, the pulse of the second output of the analyzer 8 is fed to the second input of the first block 6 by the first frequency divider 4, which ensures the start of the search for the synchronism state using the first frequency divider 4. Thus, for the proposed device, it is characteristic to search for the state of synchronism while maintaining the unchanged operation of the distributor 2. When filling the accumulator 9, i.e., the search process is over, the output signal of the full driver 9 using the second unit 7 sets the second phase with the second frequency divider 5 frequency divider b in accordance with the phase of the first frequency divider 4 found in the synchronization process; as a result, the corresponding phase / distributor operation is also established

2. The claims of the Synchronization device on cycles, containing a sync signal identification block, a distributor and a clock frequency selection unit, the output of which is connected to the counting inputs of the first and second frequency dividers, connected to the control inputs of the dividers, respectively, are connected to the control inputs of the first and second control units. and the output of the sync signal identification unit (chen to the first inputs of the first and second control units and the analyzer, the output of which is connected to the drive input, to the second At the input of the second control unit, the output of the first frequency divider is connected, and the corresponding outputs of the second frequency divider are connected to the control inputs of the distributor, characterized in that, in order to increase the speed of the device, the output of the first frequency divider is connected to the second analyzer input, the other output of which connected to the second input of the first control unit and to the reset input of the storage device, the output of the latter connected to the third input of the second control unit. Sources of information taken into account in the examination:. Levin .7. C. and ar. Basics of building digital transmission systems. M., “Holy, 1975, p. 116-117.

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