KR940008244Y1 - B6zs coding error detecting circuit - Google Patents

Abstract

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Description

BIXZS Coding Error Detection Circuit

1 is a conventional block diagram.

2 is a block diagram according to the present invention.

3 is a detailed circuit diagram of a coding state detection and coding error detection unit according to the present invention.

4 is a view showing a waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

41: shift register 42: first end gate

43: Inverter 44: Buffer

45: second and gate

The present invention relates to a circuit for decoding a signal coded and transmitted in a wired digital communication device, and more particularly to a circuit for detecting an error in B6ZS coding in a circuit for decoding a signal coded by a B6ZS (Biploar 6 Zero Substitution) method. will be.

In general, a B6ZS coded signal is decoded separately into positive data (PD) and negative data (ND), and FIG. 1 is a circuit for decoding the B6ZS coded signal.

In FIG. 1, when a B6ZS coded signal is divided into PD 'and ND' and input together with a clock CLK, the data retiming unit 10 returns a return to zero (RZ) signal to a non-retum to zero (NRZ) signal. Convert to a signal and do waveform shaping. The PD 'and ND' signals that are shaped by the data retiming unit 10 are again synthesized and output as one data by the data synthesizing unit 20, which is input to the data storage unit 50.

On the other hand, the PD 'and ND' signals which are waveform-formed and output from the data retiming unit 10 are simultaneously applied to the BPV (Bipolar Vialation) detector 30. Therefore, the bipolar via detection (BPV) detection unit 30 outputs the bipolar violation detection signal BPV to the coding state detection unit 40 as the bipolar violation is detected by the PD ′ and ND ′ signals. When the bipolar violation detection signal BPV is input to the coding state detection unit 40 to determine whether the input data is coded data, the bipolar violation detection signal BPV is reset to the data storage unit 50 to store the reset signal. Removes data

However, the decoding circuit of FIG. 1 simply decodes an input signal that is B6ZS coded but does not check a coding error. Thus, when a code error occurs, it is impossible to know whether it is an error of a local station or an opposite station. This is a significant obstacle to communication and must be improved.

Therefore, an object of the present invention is to determine whether a code error occurs when decoding the B6ZS coded input signal, and if a code error occurs, detect a code error and determine whether it is a counter station error or a local error. In providing.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram according to the present invention, and the coding state detection unit 40 of FIG. 1, which is the conventional circuit, is improved to simultaneously detect not only a coding state but also an error state of coding when coded. The state detection and coding error detection unit 60 was further added in the configuration of FIG.

FIG. 3 is a detailed circuit diagram of the coding state detection and coding error detection unit 60 of FIG. 2, and the bipolar violation detection signal BPV output from the BPV detection unit 30 is input once in response to the clock CLK. A shift register 41 for outputting a shifted (a) signal and a shifted signal (b) four times, and a shifted signal (b) output four times from the shift register 41 and four shifts (b) An inverter for inverting the first and gate 42 outputting the signal to the reset terminal RS of the data storage unit 50 of FIG. 2 and the one-shifted signal (a) of the shift register 41. (43), the buffer 44 which buffers the signal (a) shifted four times of the shift register 41 and delays the predetermined time, and the output of the inverter 43 and the buffer 44 The second error gate 45 outputs the coding error signal CER to the decoding circuit.

FIG. 4 is an input / output waveform diagram of each part of FIG. 3, and FIG. 4 (a) shows when the decoding circuit operates normally, that is, when the BPV detector 30 detects the bipolar violation detection signal BPV every third clock. Fig. 4 (b) shows the input / output operation waveform of Fig. 4 (b) shows the input / output operation waveform when the bipolar violation detection signal BPV is detected every four clocks, for example, when the BPV detector 30 detects an abnormality in the decoding circuit. It is also.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

As the conventional coding state detection operation is mentioned with Fig. 1, the B6ZS coded signal is divided into PD and ND signals as shown in Fig. 4, and these signals are returned in the data retiming section 10 by RZ (Return). to Zero) signal becomes PD 'and ND' signals converted to NRZ (None Return to Zero) signal. As the PD 'and ND' signals are applied to the bipolar vialation (BPV) detector 30, the bipolar vialation (BPV) detector 30 detects a bipolar violation detection signal (BPV) for detecting a bipolar violation. It outputs to the detection part 60. Here, when the decoding circuit is in the normal operating state, the pulse of the bipolar violation detection signal BPV applied to the coding state detection and coding error detection unit 60 continues to be generated every third clock after the preceding pulse. This is the B6ZS coding rule. Accordingly, the coding state detection and error detection unit 60 determines whether a pulse of the bipolar violation detection signal BPV occurs every three clocks according to the B6ZS coding rule, and if this pulse is generated after every three clicks, In response thereto, the data reset signal DRS is applied to the reset terminal RS of the data storage unit 50 and the same error presence signal as the reset signal is applied to the control terminal S1 of the shift register 41.

The operation of the coding state detection and coding error detection unit 60 according to the application of the bipolar violation detection signal BPV will be described in more detail with reference to FIGS. 3 and 4.

First, when the decoding circuit operates normally, the operation of the coding state detection and coding error detection unit 60 will be described with reference to FIG. 4 (a).

Now, when the bipolar violation detection signal BPV shown in FIG. 4 (a) is applied to the write shift input terminal R of the shift register 41, the shift register 41 responds to the clock signal CLK in response to the bipolar violation signal. The detection signal BPV is shifted by a predetermined number of times and output. The output terminal QA of the shift register 41 outputs the signal (a) obtained by shifting the bipolar violation detection signal BPV once, as shown in FIG. As shown in), the signal (b) is shifted four times the bipolar violation detection signal BPV. The first and gate 42 outputs a signal by ANDing the signal (a) and the signal (b), wherein the second pulse of the signal (a) is the bipolar violation detection signal (BPV) and the first pulse of the signal (b). It should be noted that the bipolar violation detection signal of BPV is ANDed by the first AND gate 42.

As shown in FIG. 4 (a) in the signal (c) output from the first and second gates 42, the preceding pulses multiplied by the first and gates 42 are reset stages of the data storage unit 50. The data reset signal DRS is applied to the RS, and at the same time, it is applied to the control terminal S1 of the shift register 41 as an error presence signal.

Looking at the configuration of the shift register 41 in detail, the input terminals (A, B, C, D) and the left shift input terminal (L) is grounded, the control terminal (S0) is a power supply (Vcc) with a clear terminal (CLR) ) Is to be applied. In addition, the control terminal S1 is connected to the output line of the first and gate 42.

In this connection, when the signal (c) output from the first AND gate 42 is applied to the control terminal S1 of the shift register 41 in binary logic " 1 " state, the shift register 41 is grounded. The signals of the input terminals A, B, C, and D, that is, the signals of the '0' state are outputted. At this point, the signal (a) of the output terminal QA of the shift register 41 is already in the second pulse. Although the bipolar violation detection signal BPV has been light-shifted once, the signal (d) of the output terminal QD has not yet light-shifted the bipolar violation detection signal BPV of the second pulse four times. Accordingly, the signal (a) of the output terminal QA outputs the bipolar violation detection signal BPV (the third pulse of the (a) signal) shifted once, but the output terminal QD of the output terminal QD of the shift register 41 is output. b) The signal is outputted to the control terminal S1 by applying a signal of "1" state (no error), i.e., it appears after 4 light shifts. The second pulse of gedoel (b) the signal is lost. FIG. 4 (b) the waveform of a dotted line to a signal (a) is showing a missing pulse signal.

Therefore, the (a) signal output from the output terminal QA of the shift register 41 generates a subsequent pulse at the third clock after the preceding pulse, but the (b) signal output from the output terminal QD is a preceding pulse. Subsequent pulses are generated at the sixth clock after.

The data reset signal DRS, which is the signal (c) output from the first AND gate 42, is applied to the data storage unit 50 to reset the data stored in the data storage unit 50. Here, the reset of the data in the data storage unit 50 means the data coding state detection confirmation.

Meanwhile, the signal (a) output from the output terminal QA of the shift register 41 is inverted by the inverter 43 and applied to one input terminal to the second end gate 45 and output from the output terminal QD. Is applied to the other input terminal of the second and gate 45. Accordingly, the second AND gate 45 outputs a coding error signal CER indicating a coding error state by logically multiplying two input signals. Since the coding error signal CER indicates that there is no coding error in the "0" state, it can be seen from FIG. 4A that there is no coding error. This operation shows an example of normal operation in B6ZS coding error detection.

Next, when the decoding circuit operates abnormally, the operation of the coding state detection and coding error detection unit 60 will be described with reference to FIG. 4 (b).

If the bipolar violation signal (BPV) is generated at a position other than every third clock, this is a coding error. At that time, the coding state detection and coding error detection unit 60 operates on the waveform of an embodiment as shown in FIG. do.

When the bipolar violation signal BPV 'occurs at a position other than every third clock, that is, every fourth clock, the output signals a' and b 'are output at the output terminals QA and QD of the shift register 41. As shown in (B) of FIG. 4, it can be seen that both signals generate a pulse following the fourth clock after the preceding pulse. Therefore, the coincidence of the pulses of the output signals a 'and b' does not occur at any clock time, so that the output signal c 'of the first AND gate 42 does not show any signal. The output signal c 'of the first and gate 42 is applied to the control terminal S1 of the shift register 41 as a signal having an "0" state (error) and at the same time the data storage unit 50 is " It is applied to the reset signal DRS of 0 " state. As a result, the data storage unit 50 cannot be reset, so that data transmission is continued.

Meanwhile, the signals (a ') and (b') output from the output terminals QA and QD of the shift raster 41 are logically multiplied by the second end gay 45 through the inverter 43 and the buffer 44. Since the error signal CER 'output from the second and gate 45 generates a pulse corresponding to an error every three clocks as shown in FIG. 4B, currently transmitted data is incorrectly coded. Able to know.

As described above, the present invention not only decodes B6ZS coded data, but also has an advantage of detecting a coding error in a data coding process.

Claims (3)

In a circuit for detecting a coding error when decoding a coded and transmitted signal, the first shift signal and the second shift are shifted a predetermined number of times in response to a clock by a bipolar violation detection signal having one pulse every predetermined clock period. Shift means for outputting a signal, first logical operation means for applying an error presence signal to a control terminal of the shift means by performing a logical operation on the first shift signal and the second shift signal, and a shift according to the application of the error presence signal And a second logical operation means for outputting a coding error signal because a predetermined logical operation is performed on the first shift control signal and the second shift control signal in the means. 2. The shift means of claim 1, wherein a light shift input terminal receives the bipolar violation detection signal, a plurality of input terminals and a left shift input terminal are grounded, and the control terminal is connected to an output terminal of the first logical operation means. B6ZS coding error detection circuit, characterized in that. 3. The second logical operation means according to claim 1 or 2, wherein the second logical operation means comprises: a buffer for delaying the first shift control signal, an inverter for inverting the second shift control signal, and a first shift buffered in the buffer. And an AND gate that logically multiplies a control signal by a second shift control signal inverted by the inverter.