SU1406809A2 - Receiver of bi-pulse signals - Google Patents

Abstract

The invention relates to communication technology, can be used in data transmission systems using self-synchronizing codes. The purpose of the invention is to increase the reliability of reception by reducing the likelihood of group error. The device performs correction of group errors caused by the transition of the receiver under the influence of errors to the reverse operation mode. To solve this goal, three elements AND 7, 9, 8, three shift registers 11, 12, 10, two inverters 13, 14, two triggers 15, 16 and element OR 17 were entered into the device. 3 Il.

Description

FIG. one

1H

The invention relates to a communication technique, can be used in data transmission systems using self-synchronizing codes, and is an improvement of the invention according to the author. No. 1019656.

The purpose of the invention is to increase the reliability of reception by reducing the likelihood of group error.

FIG. 1 shows a structural electrical circuit of the device in FIG. 2 is a block diagram of a clock pulse generator; in fig. 3 is a block diagram of a decision block.

 The device contains the first re-: gist 1 shift, decoder 2, driver 3 pulses, generator 4 clock pulses, frequency divider 5, decider 6, first 7, third, 8 and second 9 elements And, fourth 10, second 11 and third 12 shift registers, the second 13 and first 14 inverters; tori, first 15 and second 16 triggers 1 and the element OR 1 7.

 The generator 4 consists of the first 18 and second 19 delay blocks, the second 20 and first 21 differentiating blocks, the first 22 and second 23 OR elements, the inverter 24 and the AND 25 element.

Solving unit 6 form differentiating unit 26, elements And 27 and 28 and trigger 29i

The device works as follows.

Messages presented by bipulary code are received at the receiver input (it is assumed that the shape and duration of received pulses are restored). In the 4 clock pulse generator, using the delay unit 18, the received sequence is delayed by half the symbol follow-up period. After differentiation by differentiating blocks 20 and 21 of the fronts of these sequences, the output of the element OR 22 forms a sequence of synchronizing pulses (SI) with a following period I) two times higher than the received symbols. These pulses through the element ISH1 23 are fed to the generator output with 4 clocks of pulses. The occurrence of an error in the received

five

0 5

ABOUT

Q with

five

0

message leads to unselected SI. In order to detect the omission of the SR, a delay block 19, an inverter 24, and an And 25 element are used. If there is no SI, then it is inserted using a delay block 19 (the delay time of which is equal to the SR follow-up period). The absence of the SI at the first input of the element OR 23 at the set time is recorded with the help of the element AND 25, the output of which in this case generates an error signal in the received symbol.

Conversion of received messages from bi-pulse code to binary is performed in decision block 6. In this case, the bi-pulse code property is used, such as the presence in the middle of the bit interval of a negative impulse of differentiation when receiving a single symbol and a positive one when receiving a zero symbol. Based on the fact that logic elements, mainly use unipolar pulses, differentiating blocks in the proposed device have two outputs. On the first step, positive impulses are formed, corresponding to negative differentiation impulses, and on the second, positive impulses of differentiation are formed. Accordingly, in the decision block 6, the first output of the differentiating block 26 is connected via element 27 to the installation input of the trigger 29 to the unit state, and the second output through the element 28 to the installation input of the trigger to the zero state. The second inputs of the elements 27 and 28 receive the SRs corresponding to the moment of change in the values of the pulses in the middle of the bi-pulse signal. In this case, the output of the trigger 29 is formed receiving information in binary form. The selection of the SI sequence generated at the generator output 4 clock pulses only those SRs that correspond to the middle of the bit interval are performed using the shift register 1, the decoder 2, the frequency generator 3 pulses, and the frequency divider 5 by two. In this case, such a property of a bi-pulse signal is used as the obligatory presence of a combination of pulses 00 or 11 when changing the values of the transmitted symbols. At the moments of changing the values

There are no differentiation pulses generated at the beginning of the bit interval, and only a differentiation pulse generated in the middle of a bi-pulse signal is extracted. The received data is recorded in shift register 1 ha. Using the decoder 2, a combination of the 11 or 00 type is selected. According to the signal from its output, the driver of the 3 pulses generates a pulse that arrives at the input of the divider 5. If the incoming signal coincides with the pulse at the output of the divide, the bodies 5 necessary SI), i.e. there is a synchronous operation, then the change in the work of the divider 5 does not occur. Otherwise, the incoming pulse is inserted into the initial SI sequence at the input of divider 5. This results in a shift of the resulting sequence by half the period (the phase changes).

The occurrence of an error in the received message due to the false occurrence of a pair of pulses 11 or 00, as well as due to the omission of the SI, can lead to a violation of the synphasic arrival of the SI to the decisive block 6 (this is the case at the initial moment of the receiver operation). Violation of the input phase CI leads to a violation of the correct operation of the decision block 6. In this case, the device has a reverse operation, in which the received single character is fixed as zero and vice versa. This occurs due to a shift in the analysis time taken by the feed by half the period. Restoration of the correct operation of the receiver occurs only after the selection in the received sequence of the moment when the symbol values change. Therefore, a group error may appear at the output of the receiver under the influence of an error, the duration of which depends on the moment of the selection of the change of symbol values in the received data. Detection and correction of errors to a small multiplicity (one-time, two-time) are carried out using known interference-resistant codes (cyclic, Hamming, etc.), which ensure the achievement of the required probability characteristics

ten

fs

20

25

thirty

35

40

45

50

55

The device bots, however, the appearance of a group error greatly increases the likelihood of an undetected error, and also reduces the efficiency of error correcting codes. This leads to a decrease in the fidelity of the transmitted information.

To eliminate the error propagation effect, the device uses shift registers 10-12, two triggers 15 and 16, elements AND 7-9, inverters 13 and 14, and element OR 17. The group error correction is performed as follows. The binary information from the output of the decision block 6 is fed to the input of the shift register 10, where it is memorized. The error signal from the generator output 4 clock pulses is fed to the input of the register 12 shift. The instant of the occurrence of the error (possible beginning of a group error) is memorized. In the case when, after the moment of changing the values in the received sequence of characters, the signal at the output of the imaging unit 3 pulses does not coincide with the signal at the output of divider 3 (i.e., as a result of the error, a violation of the SR input signal occurs at the input of decision unit 6 ( group error), at the output of the element And 7, a signal is generated, which is recorded in the shift register 11 (the moment of recovery of the common-mode operation of the device or the moment of termination of the group error is remembered), and an error occurs In the unit state of the trigger 15, a single signal from the direct output of which allows the unit to be set in the unit state of the trigger 16, in this case, the error signal (the beginning of the group error), coming from the output of the shift register 12, is set to unit state. As a result, the consumer’s information is inverted (using inverter 13, element 9 and element OR 17). At the common-mode operation recovery signal, the output from the output of shift register 11 is set to zero The state of the trigger 15 and 16, as a result of which from this point on the information consumers: comes in unchanged.

In the case when the signals at the outputs of the divider 5 and driver 3

the pulses coincide (i.e., the error did not lead to the appearance of a group error); the indicated group of elements does not affect the receiver's operability.

Claims (3)

1. A device for receiving bi-pulse signals according to aut. St. By 1019656, characterized in that, in order to increase the reliability of reception by reducing the likelihood of a group error, it introduced three shift registers, two inverters, two triggers, three elements And, and the element SH, and the output of the driver of pulses is connected to the first the input of the first element And, the output of which is connected to the first inputs of the second shift register and the first trigger, the output of which is connected to the first input of the second trigger, the second, and the third inputs of which are connected respectively to the outputs of the second and third register The second output of the clock generator is connected to the first input of the third shift register, the output of the decision block is connected to the first input of the fourth shift register, the output of the frequency divider is connected to the second inputs of the second, third and fourth shift registers and through the first inverter to the second input The first element And, the output of the second shift register is connected to the second input of the first trigger, the direct and inverse output of the second trigger are connected to the first inputs of the second and third elements And, the output of the fourth regis pa sdvig.a coupled to a second input of the third ™ 14068096 element And through the second inverter with the second input of the second element And, the outputs of the second and third elements And connected to the inputs of the element OR. 2. The device according to claim 1, about t l and Since the clock pulse generator consists of two delay blocks, two differentiating blocks: their blocks, two gates, an inverter and an And element, the inputs of the first delay block and the differentiating block are the input of the clock generator, the output of the first differential block - j is not connected with the first input of the first element, OR, the output of the first delay unit through the second differentiating unit is connected to the second input of the first OR element, the output of which is connected to the first input of the second OR element and through the second a delay unit with a second input of the OR element, whose output is the first output of the clock generator and connected to the first input of the AND element, the output of which is the second output of the clock generator, the output of the first OR element is connected via an inverter to the second input of the I. 3. The device according to claim 1, namely, that the decision block consists of a differentiating unit, two elements AND and a trigger, the outputs of the differentiating unit connected to the first inputs of the elements AND, the second inputs of which are the first input of the decision unit, the second input and output of which, respectively, are the input of the differentiating unit and the output of the trigger, the inputs of which are connected to the outputs of elements I. FIG. 3 FIG. 2