KR930005844B1 - Switching device for cascade of multilevel interconnection - Google Patents

Abstract

The device for transmitting the control signal and the data simultaneously through the set pass comprises: a tag interpretation circuit (1) outputting the signal for a pass setting; an overlap demanding inhibit circuit (2) sending the line connecting signal and the blocking signal; a pass status storing circuit (3) storing the present set pass status by inputting the reset signal and the clock signal; an auxiliary control signal circuit (4) transfering the answer signal, the blocking signal and the control signal to the input/output port; a pass control circuit (5) controlling the connecting status of the input/output port by outputting the control signal.

Description

Switching element for circuit type multi-stage interconnection network

1 is a schematic diagram showing various connection states of a switch element of the present invention.

2 is a block diagram of a circuit switching device of the present invention.

3 is a schematic diagram showing an operating state of the switching device of the present invention.

4 is a timing diagram of respective signals used in the switching device of the present invention.

5 is a flowchart showing an operating state of the stitching element of the present invention.

* Explanation of symbols for main parts of the drawings

1: Tag Analysis Circuit 2: Overlap Request Circuit

3: Path state storage circuit 4: Auxiliary control signal circuit

5: path control circuit 11, 12: multiplexer

The present invention relates to a switching element used for a circuit-based multistage interconnection network for connecting a parallel processing computer to a processor.

In general, a parallel processing computer is a system that uses a plurality of processors to quickly solve a given problem, and it is well known that a connection system for providing a communication path between these processors is required. In addition, there are various types of connection systems used by the parallel-based computers, which are currently developed, such as crossbar switches, time-shared cmmonbuses, and multi-stage interconnection networks. It is widely used because of its better connection capability and lower cost than crossbar switches. Parallel processing computers using this multi-stage interconnection network can be divided into PE-to-PE (Processing Element-to-Processing Elment) and PE-to-M (Processing Element-to-Memory). Since the processor has its own local memory, it can refer to it quickly. It has the advantage that the data path is unidirectional compared to the bi-directional (PE-to-M) method.

However, both the PE-to-PE method and the PE-to-M method consist of software for controlling communication with a complicated circuit configuration, and thus there is a problem of low compatibility that must be installed and operated differently according to a parallel processing computer. Accordingly, an object of the present invention is to provide a switching device for a circuit-type multi-stage interconnection network that transmits data along with a control signal through a set path after setting a path for data transmission. To this end, the present invention comprises a control unit for generating a path control signal and a path unit for forming an appropriate path connection according to the path control signal generated by the control unit, while having a connection system by a generalized cube interconnection network. It is controlled by the control method by distributed control, and the destination tag method adopts the routing method and has priority to give priority to the upper port when requesting 16-bit transmission data from two input ports at the same time. It is.

The present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a connection state in the case of a 2x2 line. The upper input port (i) and the lower input port (j) of the 2x2 line switching element are connected to the upper output port (k) and the lower output port (l). Nine cases are shown by connection, straight connection, exchange connection, and broadcast connection when not connected.In this case, one input / output port is not used when it is in use. The route is available at any time.

2 shows the configuration of the line switching device, which generates the control signals required to connect the input ports (i), (j) and the output ports (k), (l), stores the path state, The control unit 10 and the control unit 20 for forming a connection state according to the path control signal generated by the control unit 10 to process the control signals required for transmission. And the control unit 10 is a path setting request signal Alternatively, in the tag analysis circuit 1 in which the tag signal TAG or the distribution tag signal BTAG is input to one input terminal while the release signal REL is alternately input to one input terminal, the path setting request signal is input. Only when is input, it decodes the routing signal by combining with the routing status signal (where the dag signal (TAG) is "0" to the upper output port (K) and if "1" is the lower output port (l)). If the distribution tag signal (BTAG) is "1", both upper and lower output ports (K) and (l) are connected.)

The route setting request signal is inputted from the tag analysis circuit 1 as described above. Alternatively, in the redundant request suppression circuit 2 in which the release signal REL and the tag signal TAG or the distributed tag signal BTAG are input to the two input terminals, the stop signal is applied to the requesting port when the port already configured is requested. When the same output port is requested, a stop signal is generated to the lower input port while sending a line connection signal to connect the upper incoming port first, and the reset signal RESET and the clock signal CLOCK are received. In the path register (3) which receives the stop signal (BLK) or the line connection signal from the redundant request stop circuit (2), the state of the currently set path is stored until the release signal (REL) is input. Provides data to the redundant request stop circuit 2 and the auxiliary control circuit 4, or outputs the routing status signal to the tag analysis circuit 1, and outputs the routing status signal from the path status storage circuit 3. The input path control circuit 5 outputs a control signal to the path unit 20 according to the state of the path establishment state signal, and between the input ports i, j, and output ports 12, l. Control connected bidirectionally to the The signal circuit 4 receives a stop signal BLK line connection signal, a route setting state signal, and the like from the redundant request blocking circuit 2 and the path state storage circuit 3, and receives a response signal. , Stop signal Or control signal ( ; Data Valid), ( ; Acknowledge), ( ; Ready for Data).

Meanwhile, the path section 20 has two multiplexers connected to the upper and lower input ports (i) and (j) with the input side in common and the output side connected to the upper output port k and the lower output port l, respectively. Two input ports (i), (j) and two output ports (k) and (l) by control signals from the path control circuit 5 of the control unit 10, consisting of (11) and (12). To make a connection. 3 schematically shows an operating state of the switching element, an idle state 21 in which a path is not set, a set-up state 22 which operates to set a path, It is divided into a data transmission state 23 for transmitting data through the established path and a release state 24 for releasing the established path. In the setup state 22 and the data transmission state 23, the release state ( Only after 24) can it return to the standby state 21. 4 is a view illustrating states of signals used in a switching device. The release signal REL is released in a state of "0" when setting a path, and is maintained until the transmission of data is completed. Return to "1". Route request signal Is used to request routing for the switching device. When routing information is loaded on the data bus, it is in the state of "0". When the connection is made according to the routing information, it returns to "1" and transfers data to the data bus. Allow it to be loaded.

Response signal Is a routing request signal that contains the response of the destination processor from one or more destinations. When the correct routing is done, the status is "0" and the routing request signal is Returns to "1 " and then becomes " 1 " to indicate the availability of the route. Stop signal ; Blocking) returns from the output ports (k) and (l) to the input ports (i) and (j). When the route cannot be connected to the destination and is blocked and has a partial route, it changes to "0". If set, the state of "1" is maintained. Control signal ( ) Tells the destination processors that there is useful data in the data at the starting point, and changes for a while to "0". Control signal Indicates that the processor is ready to receive data from all the destination processors, and cuts to "0" from the output ports (k) and (l) to the input ports (i) and (j). Control signal ( ) Indicates to the starting point processor that all destination processors have successfully received data, and is transmitted in the state of "0" from output ports (k) and (l) to input ports (i) and (j).

As shown in FIG. 5, the switching device of the present invention configured as described above initially selects the upper output port K when the tag signal TAG is "0", and selects the lower output port l when the "1". If the distribution tag signal (BTAG) is 1, the inactive signal REL is set to "0" while the routing tag for selecting both the upper and lower output ports K and (l) is loaded on the data bus. And routing request signal Is set to "0" and routing request signal to the output port according to routing cag information. And a release signal REL are transmitted (step 30).

Next, response signal to allow routing from the destination processor Check that the return is made (step 31). Response signal If is not returned, the interception signal is blocked from the access network during the routing period. Is activated in the state of " 0 " (step 32), and when the response signal ACK returns, the routing request signal is returned. Perform an in-up state 22 in which the path is set while inactive (step 33), and since the switching element has a broadcast function, it is possible to select a path from one starting point processor to multiple destinations. Response signal from all applicable destinations Is checked (step 34), and data transfer starts after returning (step 35). Here, if the request for routing from the starting point is blocked in the access network, the blocking signal is set through the partially set path. Is sent to the starting point processor, but at the time of distribution, no routing is made even if only one is blocked. Control signal indicating that the destination processor is ready to receive data after the path is established Is transmitted from the output ports k and l to the input / output ports i and j through the auxiliary control signal circuit 4 in the state of " 0 " (step 36). A control signal that puts useful data from the starting point processor on the bus and notifies ) Is notified to the destination processor by sending the input ports (i) and (j) from the input ports (i) and (j) to the output ports (k) and (l) through the path set to " 0 " (step 37). Then the control signal ( ), The destination processor reads data from the data bus and receives a control signal ( Is sent to the starting point processor (step 38).

If the data is continuously transmitted by repeating the above operation, the path is released (step 40) by activating the release signal REL to "1" (step 39).

Therefore, the switching element of the present invention is to set the path for data transmission first, and then to transmit data with a control signal through the established path, which is connected to the input and output ports of a plurality of processors, and connected linearly and cross-connected. Or it can be seen that to form a smooth connection by the method of distribution connection.

Claims (2)

Route request signal Alternatively, the release signal REL, the tag signal TAG, or the distributed tag signal BTAG are input to one input terminal, respectively, so that the routing setting request signal is input. When is input, the tag analysis circuit 1 for outputting the route setting signal and the route setting signal are input from the tag analysis circuit 1, and the above input signal is input. , (REL), (TAG), and (BTAG) are input in the same way to send a stop signal (BCK) or a line connection signal and a duplicate request stop circuit (2) and a stop signal from the duplicate stop circuit (2) Or a path state storage circuit 3 for storing a currently set path state by inputting a reset signal RESET and a clock signal CLOCK while the line connection signal is input, and setting a path from the path state storage circuit 3. As the status signal is input, the stop signal from the overlapping request stop circuit 2 Alternatively, the response signal is input to the input / output ports (i) (j) and (k) (l). , Stop signal And control signals ( ), ( ), Auxiliary control signal circuit (4) for transmitting them in both directions and the path setting state signal from the path state storage circuit (3) receives the control signal to the two multiplexers (11), (12) of the path section 20 And a path control circuit (5) which outputs and controls a connection state between an input port (i) (j) and an output port (k) (l). The input / output ports (i) (j) (k) (l) of claim 1, wherein the multiplexers 11 and 12 of the path section 20 are connected by a straight line connection, a cross connection or a distribution connection. Switching device for a circuit-type multi-stage interconnection network to be connected.