KR940005025B1 - Packet type switch element for multi-step connection - Google Patents

Abstract

The switching device comprises a queue logic for temporarily storing input data; a path select logic for selecting a path to transmit the data transmitted through the queue logic to the next stage; and a control logic for controlling the queue logic and the path select logic, thereby simplifying a communication path.

Description

Switching element for packet type multi-stage interconnection network

1 is a block diagram schematically showing a state in which the present invention is applied to a processing element (PE) -to-PE structure.

2 is a schematic diagram showing a connection state of a 2x2 switching element of the present invention.

3 is a schematic diagram showing a state where the 2x2 switching element of the present invention is used in an 8x8 cube interconnection network.

4 is a schematic diagram showing input and output signals for each block of a structure in which the present invention is applied to a PE-to-PE structure.

5 is a schematic diagram showing input and output signals of a 2x2 switching element of the present invention.

6 is a timing diagram of control signals and data of a 2x2 switching element of the present invention.

7 is a block diagram schematically showing the internal configuration of a 2x2 switching element of the present invention.

8 is a block diagram showing the configuration of the culogic of the present invention.

9 is a control signal and timing diagram of QLogic of the present invention.

10 is a block diagram showing the configuration of the path selection logic of the present invention.

11 is a control signal and timing diagram of a path selection logic of the present invention.

12 is a block diagram showing the configuration of the control logic of the present invention.

13 is a control signal and timing diagram of an input control unit in an internal configuration of a control logic of the present invention.

14 is a control signal and timing diagram of the tag control unit in the internal structure of the control logic of the present invention.

15 is a control signal and timing diagram of an output control unit in the internal structure of the control logic of the present invention.

16 is a control signal and timing diagram of the queue control unit in the internal structure of the control logic of the present invention.

17 is a control signal and timing diagram of a path selection control unit in the internal configuration of the control logic of the present invention.

18 is a timing diagram of input / output signals and data of a 2x2 switching element of the present invention.

* Explanation of symbols for main parts of the drawings

3: Cue Logic 3a: Input Cue i

4: path selection logic 4a: upper multiplexer

4b: lower multiplexer 5: control logic

5a: input controller 5b: tag controller

5c: output controller 5d: queue controller

5e: path selection controller

The present invention relates to a switching element that can be used directly in a packet-type connection network of a multi-stage interconnection network that is a data communication path between processors in a parallel processing computer.

In general, a parallel processing computer is a system that uses a plurality of processors to quickly deal with a given problem, and it is already known that a connection system for providing a communication path between these processors is required.

There are various types of access systems used by the parallel processing computers that are developed, such as crossbar switches, time-shared common buses, and multistage interconnection networks.

Among them, the multi-stage interconnection network is widely used because it has the advantage of better connection capability than the time division common bus and lower price than the crossbar switch.

The parallel processing computer using the multi-stage access network can be divided into PE-to-PE (Pro-cessing Element-to-Pro-cessing Element) method and PE-to-M (Pro-cessing Element-to-Memory) method. The PE-to-PE method can refer to it quickly because the processor has its own local memory, and the structure is simpler than that of the PE-to-M method where the data path is bidirectional. It has the advantage of being unidirectional.

However, since the above PE-to-PE method and PE-to-M method are composed of complicated communication paths and communication software that must control circuits according to the characteristics of the system, the operation compatibility is low. I have a problem.

For this reason, there is a need for interconnect networks that can be used more generally.

Accordingly, the present invention provides a switching device for a multi-stage interconnection network generally used in a PE-to-PE system, that is, a packet-type multistage interconnection network in which input and output ports are interconnected by a cube function. It is an object to provide an element.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First turning the Multistage Interconnection Network according to the present invention PE - to - when applied to PE manner as showing a connection between the respective components, a number of processors _{(PE 0), (PE 1} ), ... PE _n-1 represents the interface units IU ₀ , IU ₁ ,. It is connected to the multistage interconnection network 1 through each of (IU _n-1 ).

Each processor PE performs data processing and transmission, and each interface unit IU performs an interface with the PE, an interface with a multi-stage interconnection network, a data transmission procedure between other interface units, and a transmission error detection. .

In addition, the multi-stage interconnection network 1 internally interconnects input and output ports of each switching element by a predetermined function to interconnect data between PEs by interconnecting one PE and another PE (one or more PEs). To make it possible.

2 is a diagram illustrating a connection state of a switching element according to the present invention, that is, a 2 × 2 switching element having two input and output ports of a generalized cube connection network. The upper input port i and the lower input port j The six cases that can be connected to the upper output port k and the lower output port l through a straight or exchange connection method are shown.

3 shows the configuration of the multi-stage interconnection network when applied to the parallel processing system as an example, and shows the configuration of the multistage interconnection network that can be used in the parallel processing system including 8 PEs (N = 8).

The multi-stage interconnection network applicable to such a parallel processing system is a link that interconnects the switching elements by a cube function with 2 × 2 switching elements having a connection function as shown in FIG. )

In general, a cube interconnection network for a system containing N PEs has n (= log ₂ N) stages, each stage containing N / 2 switching elements, and each switching element and The cube function used to construct the link connecting the input and output ports is defined as follows.

Cube ₁ (P _n-1 ) (P _n-2 )... P _{i + 1} P ₁ P _i-1 ... P ₁ P ₀

= P _n-1 P _n-2 ... P _{i + 1} P ₁ P _i-1 ... P ₁ P ₀

Where 0 ≦ i <n, 0 ≦ P <N, and P ₁ is the complement of P ₁ .

On the other hand, as a control method of the multi-stage interconnection network, there is a central control method in which all the switching elements are controlled by one controller and a distributed control method in which each switching element has a control function. There is a circuit switching method for transmitting a packet and a packet switching method for packetizing the data to be transmitted and for transmitting the data by setting a path for each packet.

As a control method of the switching element according to the present invention, a distributed control method is adopted, a packet switching method is adopted as the switching method, and a destination tag method for setting a signal transmission path is applied to the device of the present invention.

In addition, a circular queue consisting of four words is used to temporarily store each packet consisting of two words (16 bits) in a switching element, and two input ports simultaneously have one output port. When contention occurs that requires the priority of each switching element, the priority can be set to be variable, so that the priority of the elements can be adjusted as desired.

4 shows a data transfer procedure between a PE and an interface unit and between an interface unit and a multistage interconnection network in a parallel processing system.

Referring to Figure 4 describes the day difference transmission procedure as follows.

First, when the PE writes predetermined data related to the transmission in the memory (not shown) of the interface unit for the transmission of the information data, the interface unit makes the data into a transmission message including a cyclic redundancy checker (CRC), and After the REL (Release) signal from the interconnection network is inspected, a REQ (Request) signal is generated to the access network, and according to a GRANT signal from the access network, a message related to the transmission is provided to the access network, and at the same time, transmission of information data is started. do.

The multi-stage interconnection network transmits all the information from the source processor to the destination processor through the interface unit of the destination processor according to the message related to the transmission and then acknowledges the ACK from the interface unit of the destination processor. Receipt of the message completes the transmission of the entire data.

In the above transmission procedure, the REQuest signal is a signal for which the interface unit of the starting point processor to transmit data requires transmission to the multi-stage interconnection network, and the RELease signal is multi-stage to prevent data contention or damage to the data being transmitted. The interconnection network is a signal that informs the interface unit of the starting point processor of its transmission status. In addition, the ACKnowledge signal is a signal that the destination processor informs the start processor of the completion of transmission when all data is transmitted.

5 shows an input / output signal of a 2 × 2 packet switching element constituting the multi-stage interconnection network. Input ports (i) and (j) are connected to a preceding switching element or a starting point processor, and an output port (k), (l) is connected to a switching element or a destination processor in the rear stage.

Among the external input signals of the switching elements, the CLK signal is a network clock signal for synchronizing all the switching elements in the multi-stage interconnection network, and the PRIOR signal is a signal representing the priority of each of the two input ports to prevent contention.

When the PRIOR signal is "0", the data of the upper input port (i) among the simultaneously input data is first received and output through one of the two output ports (A switching element receives data from one input port and thus one After outputting through the output port of "(" forwarding data "), the data of the lower input port (j) is advanced.

If the PRIOR signal is " 1 ", the data of the lower input port j is advanced first and then the data of the upper input port i is advanced.

REQ on the input port side (after all subscripts i and j are the name of the port. For example, REQ ₁ represents the port's REQ signal). It is a signal to request the start of transmission to the switching element in order to transmit, and the GRANT signal informs the front end when the switching element which receives the REQ signal can see the status of its queue for data input and can receive the data. A signal that allows data to be transmitted.

In addition, the REL signal is a signal for preventing another REQ signal from being generated at the corresponding input port while receiving data into the input queue of the switching element.

The TAG signal is a signal for setting the transmission path. If the signal is "0", it means transmission to the upper output port k, and if it is "1", it means transmission to the lower output port l.

In addition, a bit corresponding to the stage number to which the switching element belongs is selected among the destination addresses by the TAG signal.

DIN _0-15 refers to the data bus inputted by 16 bits of any packet (32 bits).

Since the length of the packet data applied to the present invention is composed of two words (each 16 bits), it is determined that two words are continuously transmitted by 16 bits when transmitting one packet data.

Looking at the signal of the output port side of the switching element as follows.

REQ (subscript k and l of all signals means port name) on the output port side is a signal that requests the start of transmission of data temporarily stored in the queue in the switching element to the switching element or the destination processor at the rear end. The GRANT signal is a permission signal from the rear end to transmit data by the transmission request signal REQ sent to the output port.

In addition, the REL signal is a signal received from the rear end so that the switching element itself does not generate a REQ signal to the rear end switching device even though the switching element itself is currently transmitting data to the rear end. DOUT _0-15 means 16-bit packet format output data transmitted to the back _stage .

6 shows the time relationship for the signals.

According to the REQ signal of the input port, the switching element provides a GRANT signal to the input port side according to its queue state to allow data transmission and a REL signal to prevent the occurrence of duplicate REQ signals. The transmitting side transmits data to the switching element by the GRANT signal of the switching element. Upon completion of the transmission of a series of packet data, the switching element releases the REL signal, making it ready for another transmission.

7 shows a configuration of a packet switching device according to the present invention, in which the packet switching device stores a queue logic (3) that temporarily stores input data, and then transfers the data transferred through the queue logic (3). A path selection logic 4 for selecting a data transmission path for transmission to a stage, and a control logic for controlling the operation of the two logics 3 and 4 and controlling all input and output signals for the front and rear ends. ).

The cue logic 3 comprises two input queues i, j (3a, 3b).

8 shows a preferred embodiment of the cue logic 3 of one of the elements constituting the switching element according to the present invention, in which the cue logic 3 according to the present embodiment has data of the upper input port i side. A first input queue 3a for temporarily storing the data and a second input queue 3b for temporarily storing data on the lower input port j side. In addition, each of the cues 3a and 3b assigned to each input port (port i, port j) is composed of four cues.

Since the length of the packet data to be input is a 16-bit word, the input queues 3a and 3b of each port are constructed by connecting four 16-bit registers (R _i1 to R _i4 ) and (R _j1 to R _j4 ) in parallel. can do.

In the cue 3a connected to the upper input port, R _i1 receives the first 16-bit data from the front end through the DINi _0-15 terminal by the QINi ₁ signal applied from the control logic 5, and immediately generates the QINi. _{By 2} signals, the second 16-bit data is stored in Ri ₂ via the DINi _0-15 terminals.

In this way, one packet data consisting of two words is input to the queue logic 3a.

These data are sent to the output of the cue logic 3a by the QOUTi ₁ and QOUTi ₂ signals from the control logic 5.

That is, one word data of the packet stored in R _i1 by the QOUTi ₁ signal is transferred to the output DOUTi _0-15 of the cue logic 3a, and then R _i2 in the QOUTi ₂ signal applied from the control logic 5. The other word of the packet stored in D is transferred to DOUTi _0-15 .

This output data is passed to the path selection logic 4 of the switching element. If the output control signals QOUTi ₁ and QOUTi ₂ of the logic logic 3a are not enabled and another packet data is received, the logic logic 3a is generated by the QINi ₃ signal generated by the control logic 5. ) Receives one word of a new packet from DINi _0-15 and stores it in Ri ₃ , and then receives the other word from DINi _0-15 by QINi ₄ signal and stores it in Ri ₄ .

The newly stored packet data is output through DOUTi _0-15 for each word by the QOUTi ₃ and QOUTi ₄ signals (control signals QINi _{1 to} QINi ₄ and QOUTi _{1 to} QOUTi ₄ are described in detail later with reference to FIG. 12). Will be explained).

As in the case of the sub input queue j (3b) type queue i (3a) described earlier in the case of a two word, that is a packet of 16 bits is input through the terminal to DINj _0-15 QINj ₁ ~QINj ₄ signals The data is stored in the registers Rj _{1 to} Rj ₄ of the input queue j (3b), and the data stored by the QOUTj _{1 to} QOUTj ₄ signals are output via the data bus DOUTi _0-15 in units of 16 bits.

The subscripts 1 to 4 of the signals QINi and QINj respectively output from the control logic 5 act as input latch signals of the registers having the subscripts of the numbers, and the subscripts 1 to 4 of the signals QOUTi and QOUTj denote the subscripts of the numbers. It acts as the output enable signal of the excitation register.

As described in detail above, the queue logic 3 has a function of continuously storing data transmitted from the front end and passing it to the back end so that the queue is in a full state (data stored in the queue cannot be delivered to the back end). Only when the packet data is input twice in a row and the four registers are filled with data), redundancy of the data for transmission can be prevented, and when the contention for the transmission port occurs, This can prevent the PE from continuously attempting to transmit only to prevent its own execution.

9 is a timing relationship between the input and output signals of the cue logic 3 according to the present embodiment, and as described in detail above, two input queues (QINi _{1 to} QINi ₄ or QINj _{1 to} QINj ₄ signals) are used. 3a, 3b), two words (one packet) are latched in units of 16 bits and two words (one packet) are output in units of 16 bits by QOUTi _{1 to} QOUTi ₄ or QOUTj _{1 to} QOUTj ₄ signals. Indicates.

FIG. 10 shows a preferred embodiment of the path selection logic 4 which is another component of the switching element according to the present invention. The path selection logic 4 according to the present example comprises two 32 × 16 multiplexers 4a, 4b).

Each of the two multiplexers 4a, 4b accepts the signals MUXk and MUXl output from the control logic 5 as their respective selection signals, and also provides other signals TRANSk ₀ and TRANSk ₁ , and TRANSl provided from the control logic 5. Accept ₀ and TRANSl ₁ as their respective output enable signals.

When the selection (control) signal MUXk is '0', only data on the DOUTi _0-15 side of the data (data received through the input port DOUTi _0-15 or DOUTj _0-15 ) received from the QLogic 3 If it is '1', only the data of DOUTj _0-15 is transferred to the output port (k).

Similarly, when the selection (control) signal MUXl is '0', only data on the DOUTi _0-15 side among the data (from the input port DOUTi _0-15 or DOUTj _0-15 ) received from the cue logic 3 If it is '1', only the data of DOUTj _0-15 is transferred to the output port (l).

After the path is set by the selection control signals MUXk and MUXl, the output port data of the switching element is transferred by the signals TRANSk ₀ , TRANSk ₁ or TRANSl ₀ , TRANSl ₁ from the control logic 5.

That is, the control signal TRANSk ₀ is an output enable signal of the multiplexer. When the control signal TRANSk ₀ is '0', the first word of the routed data is transmitted to the DOk _0-15 terminal of the output port k through the multiplexer 4a. When the signal TRANSk ₁ becomes '0', the second word of the packet is transferred to the output port.

When the control signal TRANSk ₀ becomes '0', the first word of the routed data is transmitted to the DOl _0-15 terminal of the output port l through the multiplexer 4b. When the control signal TRANSl ₁ becomes '0', The second word of the packet is transmitted (control signals MUXk, MUXl, TRANSk ₀ , TRANSk ₁ , TRANSl ₀ and TRANSl ₁ will be described in detail later with reference to FIG. 12).

FIG. 11 shows the timing relationship between the input / output signals of the path selection logic 4 described above. After the data to be output by the signal MUXk or MUXl is selected as described above, the signal TRANSk ₀ , TRANSk ₁ or TRANSl ₀ , TRANSl ₁ transmits word by word to Dl _0-15 terminal of output port (l).

FIG. 12 shows a preferred embodiment of the control logic 5, which is another component of the switching element according to the present invention. The input control unit 5a, tag control unit 5b, output control unit 5c, and queue control unit 5d and a path selection control section 5e.

All of the components 5a to 5e are implemented by a TTL gate, a flip-flop, or the like.

The input control unit 5a is a part for controlling signal exchange with the switching element at the front end or the interface unit at the starting point processor side. The control unit 5a is configured to input the input queue 3a or If 3b) determines that the data can be accepted, it generates a signal (GRANTi or GRANTj) that permits data transmission at the front and prevents another transmission request signal (REQi or REQj) from occurring during data transmission. Send a blocking signal (RELi or RELj) to the front end.

That is, when the REQi signal of "1" is input to the switching element, data transmission is required through the input port i. Therefore, the input control unit 5a transmits the state signal FULLi of the first input queue 3a. Will be described in detail later in the process of explaining the function of the queue control section 5d). Only when the first cue 3a is found to be not full (when FULLi = "0"). The GRANTi signal, which permits the input of data, is set to "1" and passed to the front to allow data transmission. In addition, the input control unit 5a makes the RELi signal "1" and sends it to the front end so that another transmission request signal through the input port i is not generated at the front end.

When RELj signal of " 1 " is input to the input control unit 5a until one packet data consisting of only two words is input to the first input queue 3a, data transmission is performed through the input port j. As it is required, the input control unit 5a refers to the state signal FULLj of the second input queue 3b (this signal will be described later in detail in the process of describing the queue control unit 5d). Only when it is determined that the second input queue 3b is not full (FULLj = "0"), a GRANTj signal allowing data input is made "1" and transmitted to the front end to allow data transmission. .

In addition, the input control unit 5a makes the RELj signal "1" and sends it to the front end so that another transmission request signal through the input port j is not generated from the front end.

However, the input control unit 5a maintains the RELj signal at " 1 " until one packet data composed of two words is provided to the second input queue 3b.

The signals of the input control unit 5a described above are signals related to the input port side of the switching element.

On the other hand, LD0i, LD1i, LD0j, LD1j, INCQPAi, and INCQPAj are signals transmitted by the input controller 5a to the queue controller 5d.

Among the signals, the LD0i and LD1i signals are input by the input control unit 5a to the status signals of the input queue i (3a) and the input queue j (3b). When the queue is determined to be empty, the first word of the packet may be stored in the input queues 3a and 3b, respectively. .

The signals LD1i and LD1j are signals generated one clock CLK later than the LD0i and LD0j signals, which inform the queue control unit 5d so that the second word of the packet can be stored in the input queues 3a and 3b. On the other hand, since the data can no longer be stored in the register of the queue where packets are stored due to LD0i, LD1i, LD0j, and LD1j signals, the cue pointer must be changed.

At this time, the control signals for changing the input pointers for each of the two input queues 3a and 3b are the INCQPAi and INCQPALD1j signals.

The tag control unit 5b is logic that receives the path selection information signals TAGi and TAGj from the front end of the switching element and generates the TTAGi and TTAGj signals which are notified to the output control unit 5c.

In other words, when the packet data is inputted to the queue logic 3 of the switching element, the logic 5b reads the bits corresponding to the stage number of the routing tag to which the switching element belongs, TAGi and TAGj. Accept as.

At this time, the tag control unit 5b receives the position conversion pointer control signals QPAi, QPAj, QPTi, and QPTj of the input queues 3a and 3b (these signals are transmitted from the queue control unit 5d, and their respective functions are controlled by the queue control unit (3). The signal TTAGi or TTAGj is generated and passed to the queue control unit 5d, and the TAGi and TAGj are prepared to accept another tag information.

At the same time, since the TTAGi or TTAGj is routing information of data to be output from the input queues 3a and 3b, the signals TTAGi and TTAGj are also notified to the output control unit 5c and the path selector 5e. In this case, the output control section 5c and the path selection section 5e allow the information to be used as routing information when the packet data is transferred to the next stage.

At this time, when the tag information TTAGi and TTAGj is "0", it is required to form a path to the output port A, and if it is "1", it is required to form a path to the output port l.

In addition, when it is determined that the use of the tag information TTAGi and TTAGj is finished (the new Qpoint change signal INCQPAi and INCQPAj are detected), the tag control unit 5b clears the previous tag information.

The output control section 5c has a signal EMPTYi or EMPTYj indicating that the packet data has been entered from the queue control section 5d to the input queues 3a and 3b (these signals are "1" when there is no data in the input queue and is empty). Is transmitted, the transmission request signal REQi or REQj determined by the routing information TTAGi or TTAGj of the data is transmitted to the rear end. The output control unit 5c performs the same function as the signals having the same name among the signals output from the input control unit 5a as the functions of the REQk, REQl, GRANTk, GRANTl and REIk, RELl signals (subscript k And l means that the port is the signal of the output port (k) and (l) of the switching element, and these signals are input ports of each switching element arranged at the rear end of the connected network as shown in FIG. connected to (i) and (j).

In addition, the output control unit 5c transmits the TR0i, TR1i, TR0j, TR1j, INCQPTi and INCQPTj signals to the queue control unit 5d to transmit the data of the input units 3a and 3b when the transmission permission signal GRANTk or GRANTl is applied from the rear end. To pass.

Signals TR0i and TR0j allow the first word of the packet data to be output to the first input queue 3a and the second input queue 3b to be transmitted, respectively. TR1i and TR1i are input queues to be transmitted, respectively. This signal permits outputting the second word of packet data of i (3a) and input queue j (3b).

In addition, when the data is output from the input queue 3a or 3b, the position control pointer should also be changed. Therefore, the output control unit 5c generates an INCQPAi and INCQPAj for this purpose, so that the queue control unit 5d changes the output pointer of the input queue. Inform.

The queue control section 5d generates the input latch signals QINi _{1 to} QINi ₄ or QINj _{1 to} QINj ₄ from the input control section 5a by the signals LD0i, LD1i, LD0j and LD1j to the cue logic 3.

In addition, the queue controller 5d receives the INCQPAi or INCQPAj signal from the input controller 5a to determine the position of the input units 3a and 3b where the input data is to be stored, and then changes the cue input pointers QPAi or QPAj accordingly. Let's do it.

That is, when the signal LD0i is applied from the input control unit 5a, QIN ₁ or R _i1 or R _i3 of the input queue i (3a) is input according to the value of the current input cue pointer QPAi to input the first word of the packet. QIN ₃ is generated, and when LD1i is applied, an input latch signal QIN ₂ or QIN ₄ is generated for R _i2 or R _i4 of the input queue i 3a to input the second word of the packet.

Thereafter, since R _i1 and R _i2 or R _i3 and R _i4 of the input queue 3a contain data, the input pointer of the cue needs to be changed.

That is, if the value of QPAi is currently "0", it is inverted to "1", and if it is "1", it prepares to receive the next packet.

In addition, the queue control unit 5d transmits the signal QPAi to the tag control unit 5b, so that the tag control unit 5b transmits a TTAGi signal corresponding to the TAGi signal, which is routing information, to the output control unit 5c to transmit the routing information of the data. The output control unit 5c is informed.

Signals LD0j, LD1j and QPAj output from the input control unit 5a are also signals for controlling the input operation of the input queue j (3b) as described above, and the operation relation is the case of the input queue i (3a). Is the same as

On the other hand, when the data of the two input queues 3a and 3b is to be output to the rear end, the queue control unit 5d uses the logic logic (seventh) by the signals TR0i, TR1i and TR0j, TR1j from the output controller 5c. In addition to generating the output enable signals QOUTi _{1 to} QOUTi ₄ or QOUTj _{1 to} QOUTj ₄ , the input queue that stores the data to receive and output the signals INCQPTi and INCQPTj provided from the input controller 5a. After determining the position of 3a, 3b), the output pointer OPTi or OPTj of the queue is changed accordingly.

That is, when the signal TR0i is applied from the output controller 5c, the output enable of R _i1 or R _i3 of the input queue i (3a) according to the value of the current input queue pointer QPTi to output the first word of the packet. The signal QOUT _i1 or QOUT _i3 is generated, and when TR1i is applied, an output enable signal QOUT ₁₂ or QOUT ₁₄ for R _i2 or R _i4 of the input queue i 3a is output to output the second word of the packet.

Thereafter, since data is output to R ₁₁ and R ₁₂ or R ₁₃ and R ₁₄ of the input queue 3a, the output pointer of the queue needs to be changed.

In other words, if the value of the signal QPTi is currently "0", it should be inverted to "1" and if it is "1" to change the next packet.

In addition, the queue control unit 5d reports the relationship between the input / output pointers QPAi and QPTi or QPAj and QPTj of the two input queues 3a and 3b (applied to the annular queue algorithm). If the queue is empty, EMPTYi or EMPTYj is set to "1". If the queue is full of data, FULLi or FULLj is set to "1" to indicate that the queue is full.

The path selection controller 5e selects an output port of data based on the lighting information.

That is, the path selection controller 5e receives the routing information TTAGj of the data stored in the input queue i 3a from the tag controller 5b, and if the value is "0", the output port A is required. If the signal MUXk is set to "0" and the routing information TTAGi is "1", the output port l is required. Therefore, the selection control signal MUX1 is set to "0" and transmitted to the path selection logic (see 4 in Fig. 7). By doing so, data of the input queue i (3a) can be output to the output port k or l, but the value is maintained until both words of one packet are output.

On the other hand, when the routing information TTAGj of the routing information TTAGj of the data stored in the input queue i (3b) is input from the tag control unit 5b to the routing information TTAGj, when the value of the routing information TTAGj is "0", the selection control signal MUXk Is "1" and the value of the TTAGj signal is "1", MUX1 is made to "1" and transmitted to the path selection logic 4 so that the data of the input queue j (3b) is output to the output port k or l. But keep the value until both words in a packet are output.

If two routing information (TTAGi and TTAGj) are simultaneously input to the path selector 5e with the same value of "0" or "1" (in case of contention), another PRiOR, which is another input signal, is reported. If the value is "0", the data of the input queue i (3a) can be output to the output port k or l first. If the value is "1", the data of the input queue j (3b) is output to the output port k or l first. Enable output to l.

In addition, the path selection control unit 5e receives the data transmission permission signal GRANTk or GRANTl from the rear end and transmits the output enable signal TRANSk ₀ , TRANSk ₁ or TRANSl ₀ , TRANSl of the multiplexer of the path selection logic (see 4 in FIG. 7). Provide ₁ to ensure that latched data is output to the selected output port.

That is, when the transmission permission signal GRANTk is applied to output data to the output port k, the path selection control section 5e first generates a signal TRANSk ₀ , so that one packet latched in the path selection logic (see 4 in Fig. 7). After the first word of is output to the output port k, the signal TRANSk ₁ is generated again so that the second word is output to the output port k.

On the other hand, when the transmission permission signal GRANTl is applied to output data to the output port l, the path selector 5e first generates a signal TRANSl ₀ so that the first word of one packet latched in the path select logic 4 is generated. After outputting to the output port l, generate the signal TRANSl ₁ again so that the second word is output to the output port k.

FIG. 13 shows the correlation of input and output signals to the input control unit 5a of the control logic 5. As described above, after receiving a REQi or REQj signal and checking the state of the queue, GRANTi and GRANTj Alternatively, RELi and RELj signals are generated, and at the same time, LD0i, LD1i, LD0j, LD1j and INCQPAi and INCQPAj are transmitted to the queue control unit 5d.

FIG. 14 shows the correlation of the input / output signals to the tag control unit 5b of the control logic 5. As described above, the queue state signals LD0i, LD1i, QPAi, QPAj, QPTi, QPTj) and the TTAGi or TTAGj signal are generated by the input signals TAGi or TAGj, and the TTAGi or TTAGj signals are disabled by INCQPTi and INCQPTj, which are signals for changing the cue pointer.

FIG. 15 shows the correlation of the input / output signals to the output control unit 5c of the control logic 5, and as described above, by the tag information TTAGi and TTAGj from the tag control unit 5b. It sees the RELk or RELl signal status from the rear end and generates REQk or REQl signal and disables it by GRANTk or GRANTl signal.

FIG. 16 shows the correlation of the input / output signals to the queue control unit 5d of the control logic 5. As described above, the control signals from the input control unit 5a and the output control unit 5c are In addition to the input and output pointers of the queue, the input latch signal and the output enable signal of the queue are also generated.

FIG. 17 shows the correlation of input and output signals to the output control section 5e of the control logic 5. As described above, tag information (TTAGi and TTAGj) and queues from the tag control section 5b are described. After setting the path based on the cue status signals EMPTYi and EMPTYj from the control section 5d, an output enable signal is generated by the GRANTk or GRANTl signals from the rear stage.

FIG. 18 illustrates the correlation of the external input / output signals of the entire switching device according to the present invention. As described above, the transmission request signals REQi and REQj for i and j are accepted and the permission signal ( It shows that GRANTi, GRANTj) and stop signal (RELi, RELj) are sent out, and the data of input port is input in 16 bit word unit and transmitted to the back stage.

Claims (4)

In a parallel processing system containing N PE (processing elements), it has log ₂ N stages, each of which has two input ports (i, j) and two output ports (k, l). In the multi-stage interconnection network (1) each including N / 2 switching elements, interconnecting one PE and the other one or more PE through the interface means and enables data communication between the PE, the switching The device selects a queue logic 3 for temporarily storing data input through the two input ports i and j, and a path for transferring data transmitted through the queue logic 3 to the next stage. Controlling the queue logic 3 and the path selection organization 4 in response to the path selection logic 4 and the input signals provided from the front and rear ends to control the setting of the path as well as the input / output of the data. Control logic (5) Packet switching element Multistage Interconnection Network method which comprises. The cue logic of claim 1, wherein the cue logic 3 includes four registers Ri _i to R _i4 connected in parallel to each other, and the cue input control signals Q INi transmitted from the control logic 5. _{1 to} QINi ₄ ) and the queue output control signals QOUTi _{1 to} QOUTi ₄ to control the data DINi _0-15 input through any one of the two input ports to the path selection structure 4. A first input queue 3a to transmit; Other cue input control signals QINj _{1 to} QINj ₄ and other queue output control signals including four registers R _j1 to R _j4 connected in parallel to each other and transmitted from the control logic 5. A second input queue 3b for transferring data DINj _0-15 , which is input through the other one of the two input ports controlled by (QOUTj _{1 to} QOUTj ₄ ), to the path selection logic 4; 3. A switching element for a packet type multi-stage interconnection network comprising: 3. 3. The path selection tissue (4) according to claim 2, wherein the path selection tissue (4) comprises two multiplexers (4a, 4b), each of which is a path selection signal transmitted from the control logic (5). Are controlled by the controllers MUXk and MUXl and selectively latch any one of two pieces of data provided from the first and second input queues 3a and 3b, respectively, and then from the control logic 5 Outputs the latched data in word units controlled by the two transmit enable signals TRANSNS0 and TRANSk1 and the other two transmit enable signals TRANSl0 and TRANSl1, respectively. The packet method of claim 1, in response to the priority signal PRiOR provided from the first and second input queues (3a, 3b), one of the two data provided from each of the data is selected first and latched first. Switching stations for multistage interconnection networks . 3. The path selection logic (4) according to claim 2, wherein the path selection logic (4) comprises two multiplexers (4a, 4b), each of the two multiplexers (4a, 4b) being route selection signals transmitted from the control logic (5). 2 which is controlled by (MUXk, MUXl) and selectively transferred one of two data provided from the first and second input queues 3a and 3b, respectively, and then transferred from the control logic 5. Outputs the latched data in word units controlled by the two transmit enable signals TRANSNS0 and TRANSk1 and the other two transmit enable signals TRANSl0 and TRANSl1, respectively. A switching element for a packet multi-stage interconnection network, characterized in that one of the data is first selected and latched. 4. The method of claim 3, wherein the first and second input queues 3a and 3b are in a state capable of accepting data in response to the routing request signals REQi and REQj in front of the control logic 5. At the same time, it generates transmission permission signals GRANTi and GRANTj that allow data to be transmitted to the front end, and at the same time, stop signals RELi and RELj to support the generation of another request signal at the front end during data transmission. An input control unit 5a for providing the front end and generating predetermined control signals LD0i, LD1i, LD0j, LD1j, INCQPAi, INCQPAj related to the control of the cue logic 3; When data is input from the front end to the queue logic 3, path selection information (TAGi, TAGj) corresponding to the number of the stage to which it belongs is selected from the routing tag information, is stored and received, and the first and the first A tag control unit 5b for outputting tag information TTAGi and TTAGj in response to the position conversion pointer control signals QPAi, QPAj, QPTi and QPTj of the input queues 3a and 3b of the second; The tag information TTAGi provided from the tag control unit 5b in response to the input queue status signals EMPTYi and EMPTYj indicating that the first and second input queues 3a and 3b are empty. , TTAGj), and transmits the routing request signals REQk and REQl to the rear stage, and receives the transmission permission signals GRANTk and GRANTl and the stop signals RELk and RELl provided from the rear stage, and transmits them. Signals TR0i, TR1i, TR0j, TR1j, INCQPTi, INCQPTj for controlling data stored in the first and second input queues 3a and 3b to be transmitted to the rear end in response to the permission signals GRANTk and GRANTl. An output control unit 5c for outputting a; The input control signals LD0i and LD1i from the input controller 5a are checked by checking whether the cues are empty or full while controlling the transmission position and the reception position of the first and second input queues 3a and 3b. Data input to the first and second input queues 3a and 3b in response to the transmission control signals TR0i, TR1i, TR0j, and TR1j from LD0j, LD1j and output control section 5c. A queue control unit 5d for controlling the output; In response to the tag information TTAGi and TTAGj from the tag control unit 5b and the output permission signals GRANTk and GRANTl from the rear end, the path setting of the path selection logic 4 and input / output of data are performed. And a path selector (5e) for controlling the switching.