KR910009145Y1 - Jitter improving circuit of vcr - Google Patents

Abstract

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Description

Video jitter improvement circuit

1 is an overall circuit diagram other than the video jitter improvement circuit.

* Explanation of symbols for the main parts of the drawings

A: Fixed delay circuit B: Time delay detector

C: Variable Oscillator D: Variable Delay Circuit

E: Output C: Color Synchronization Circuit

D: reference clock generator OP: comparator

F / V-con ₁ , F / V-con ₂ : Frequency voltage converter

R ₁ -R ₄ : Resistor Vco: Voltage controlled oscillator

TR ₁ : Transistor LPE: Low Pass Filter

The present invention relates to the jitter (Jitter) improvement circuit of the video, and more particularly to the jitter improvement circuit to improve the horizontal resolution and image quality by improving the jitter caused by the uneven rotation of the drum in the VTR.

Conventionally, when a video signal is obtained on a rotating body in a VTR or a video disc player (VDP), the video signal is uneven with respect to time due to uneven rotation of the rotating body.

Therefore, the drum servo of the VTR is adjusted to the maximum uniformity or the distance between the horizontal sync signal and the horizontal sync signal, which is a video signal, has been improved. However, a satisfactory effect cannot be obtained.

The present invention can improve the jitter on the new signal side of the video signal by using a fixed delay circuit and a variable delay circuit to detect the frequency of the color synchronization signal and fix it to 3.58 MHz to solve the above problems. It is to be able to improve the horizontal resolution and image quality by, so as to describe the present invention in detail by the accompanying drawings as follows.

A color delay circuit from the video signal input from the video signal input terminal Video-IN of the fixed delay circuit to fix the video signal input from the video signal input terminal Video-IN to the color synchronizer circuit C. Detects a signal and converts it into a voltage corresponding to a frequency through a frequency-to-voltage converter (F / V-con ₁ ) and generates a reference frequency of 3.58 MHz in the reference clock generator (D) to convert the generated frequency into a frequency-to-voltage converter. A resistor (R) for comparing the two voltages inputted from the time delay detecting unit (B) and the time delay detecting unit (B) converting the voltage corresponding to the frequency through F / V-con ₂ to generate the difference voltage. ₁ ), (R ₂ ), (R ₃ ) Comparator (OP) Variable oscillation unit (C) consisting of voltage controlled oscillator (Voc) and a fixed delay circuit (A) and a fixed delayed video signal from the fixed delay circuit (A) Oscillation input from the variable oscillator (c) A variable delay of the variable delay by the frequency circuit (D) and said variable delay circuit (D) variable delayed output sinhojung transistor to eliminate the oscillation frequency (TR _1), a resistance (R ₄₎ Buffer (Buf) and the low-pass filter constructed from It is composed of the output unit (e) consisting of (LPF), the operation and effect of the present invention configured as described above are as follows.

When a video signal is input from the video signal input terminal (Video-IN), the video signal is input to the signal delay unit (a) and the time delay detector (b), respectively.

Accordingly, the video signal inputted to the time delay detecting unit B generates a color synchronizing signal synchronized with the burst signal by the color synchronizing circuit C, and is input to the frequency-voltage converter F / V-Con ₁ . .

Therefore, the frequency-to-voltage converter (F / V-con ₂ ) converts the voltage corresponding to the frequency into the variable oscillator (C), while the reference oscillation frequency is used in the 3.58MHz clock generator (D) of the time delay detector (B). When is generated, the frequency voltage converter F / V-con ₂ converts the voltage corresponding to the frequency into the variable oscillator (c).

Therefore, in the variable oscillator C, two voltages input from the time delay detector B are input to the comparator OP through the resistors R ₁ and R ₂ , that is, the inverting terminal of the comparator OP ( The voltage corresponding to the frequency obtained by the color synchronization circuit C is input to −), and the voltage corresponding to the frequency oscillated by the clock oscillator D is input to the non-inverting terminal (+) of the comparator OP.

Accordingly, in the comparator OP, when the color synchronizing frequency voltage is greater than the reference frequency voltage, the output of the comparator OP becomes smaller. On the contrary, when the color synchronizing frequency voltage is smaller than the reference frequency voltage, the output of the comparator OP becomes large.

In other words, when the video signal read in HD is read late, the frequency is 3.57MHz slightly smaller even when synchronized with 3.58MHz in the color synchronization circuit (C), and about 3.59MHz when read quickly. In comparison with OP), the output of the comparator OP becomes small and when read late, the output of the comparator OP causes the door voltage controlled oscillator Vco to oscillate quickly.

Therefore, in the voltage controlled oscillator Vco, as the voltage output from the comparator OP is large and small, the frequency is oscillated in the voltage controlled oscillator Vco small (approximately 3.57 MHz) or large (approximately 3.59 MHz) and thus the variable delay circuit (D). ) Is applied.

This process is explained in more detail as follows.

As described above, since the jitter component is generated due to the time difference read from the HD, the video input signal read from the HD causes the screen to flicker.

In other words, the screen can be seen clearly when read at the correct time interval. However, in case of NTSC (color television system), when the HD switching time interval of 60㎐ is shifted or when read quickly as shown in Table 1, it is 1 field. Appears on the left side of the screen and on the right side of the screen when read late, resulting in screen flicker.

TABLE 1

When such a video signal is input, the color synchronizing circuit C is matched with a burst signal of 3.58 MHz, but the synchronization of the correct 3.58 MHz is not synchronized, and the comparator OP is compared with the output of the 3.58 MHz reference clock generator D. The compared difference is output to the voltage controlled oscillator Vco to oscillate.

In this way, it is applied to the variable delay circuit (D) oscillated by the voltage controlled oscillator (Vco).

And the fixed delay circuit can adjust the screen by delaying the part that reads quickly, but the part that reads late can't be pulled forward. If you delay a little bit, the screen will match.

On the other hand, in the fixed delay circuit (a) to which the video signal is input, the video signal is fixed according to the time delay in the time delay detecting unit (b) and then the variable delay circuit is controlled by the oscillation frequency received from the variable oscillation unit (c). Delayed).

When the video signal is inputted, the variable delay circuit D) delays the video signal delayed by the oscillation frequency input from the voltage controlled oscillator Vco of the variable oscillator C to output the time-corrected signal. The oscillation frequency is removed through the buffer TR and the low pass filter LPF composed of the transistor TR ₁ and the resistor R ₄ , and the oscillation frequency is removed through the image output terminal out. Only the image output terminal (out) is to be output.

In other words, when the LPF is NTSC, as shown in the figure below,

With a range of approximately 4.5 MHz, residual components (oscillation frequency) such as clock signals (range of 15 to 27 MHz) are removed by the low pass filter (LPF).

The oscillation frequency is removed by the low pass filter (LPF) so that only the video signal is output to the image output terminal (out).

As described above, the present invention converts an input video signal into a voltage in the time delay detection unit, and then applies it to the time delay unit by varying the oscillation in the variable oscillation unit. By eliminating the oscillation frequency through the filter and outputting only the video signal, the jitter is eliminated. Therefore, the horizontal resolution can be improved and the stability of the screen can be increased.

Claims (1)

A fixed delay circuit (A) for fixedly delaying the input video signal, a color synchronization circuit (C) for detecting the video signal as a color synchronizing signal, and converting a frequency into a voltage (F / V-con ₁ ) Resistance (R ₁ ) and (R ₂ ) for comparing and oscillating the voltage input from the time delay detection unit (B) and the time delay detection unit (B) including (F / V-con ₂ ) and the reference clock generator (D). , (R ₃ ) Variable which delays the fixed delayed signal input from the fixed delay circuit (A) by the oscillation frequency of the variable oscillator (C) and the variable oscillator (C) consisting of a comparator (OP) voltage controlled oscillator (Vco). It consists of an output part (d) consisting of a resistor (R ₄ ) transistor (TR ₁ ) low-pass filter (LPF) which removes the oscillation frequency among the signals output from the delay circuit (r) and the variable delay circuit (d). Jitter improvement circuit for video.