KR850007178A - Error correction system of teletext system - Google Patents

Abstract

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Description

Error correction system of teletext system

As this is a public information case, the full text was not included.

2 is a block diagram of an embodiment of the invention. 3 is a timing diagram for explaining the embodiment of FIG. 4 is a flowchart art for explaining an embodiment.

* Explanation of symbols for the main parts of the drawings

10: CPU data bus, 11: CPU address bus, 12: data bus control circuit, 13: local data bus, 14: address switching circuit, 15: address generating circuit, 17: timing control circuit, 18: bus control Signal, 19: buffer memory, 20: data transfer circuit, 22: framing detection signal, 24: data register, 26: synth register, 27: adder, 28: low gate circuit, 31: majority circuit, 33: threshold value generation Circuit, 38: correction gate circuit, 41: adder, 46: vertical blanking signal, 48: horizontal synchronizing signal, 50: error stair signal, 71: color burst, 90: data register output 8-bit register

Claims (6)

An error correction circuit having at least a syndrome register, a data register and a majority decision circuit to correct an error in the packet, a buffer memory for storing original pre-correction data and post-correction data to be corrected; A local data bus (13) for connecting the buffer memory and the error correction circuit; An address switching circuit (14) for switching an address of the buffer memory (19) between an address signal supplied to the error correction circuit and an address signal from an external circuit; A data bus control circuit (12) for connecting either the local data bus (13) or an external circuit bus with the buffer memory (19); Error correction of the teletext system, characterized in that the data transfer between the buffer memory 19 and the error correction circuit is performed by a logical hardware means connected without using the programmed software's operating time. system. 2. The apparatus of claim 1, further comprising: an address generating circuit (15) for supplying an address signal to said buffer memory (19); A data transfer circuit (20) for transferring data between the buffer memory (19) and a data register (24) and a syndrome register (26) in the error correction circuit; And a timing control circuit (17) for supplying a timing signal for operation of the error correction circuit. 2. The error correction system of claim 1, wherein the buffer memory 19 has an area for storing the first pre-correction data to be corrected and another area for storing the post-correction data. . 2. The error correction system of claim 1, wherein the address generation circuit (15) determines an address for storing the received signal by counting the number of horizontal sync pulse signals of the TV received signal. 3. The data transmission circuit of claim 2, wherein the data transmission circuit 20 transmits received data to a local data bus according to a signal whose clock run of the packet of the teletext signal is synchronized with the signal and a framing signal of the packet of the teletext signal. An error correction system for a teletext system, which comprises a means. The error correction signal according to claim 1, wherein the error correction signal generated at the output of the majority vote circuit is counted, a correction number signal indicating a number held in a counter, and a correction over signal when the number exceeds a predetermined value. An error correction system of a teletext system, characterized by comprising a correction water counter sent to a circuit. ※ Note: The disclosure is based on the initial application.