JPS6244625Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention divides a character signal consisting of a character string and a simple figure into each scanning line during a predetermined horizontal scanning period in a vertical blanking period of a color television signal, and divides the character signal into a packet format, for example. Regarding a character signal superimposition device for superimposing and broadcasting, in particular, the phase shift of the character signal superimposition device that occurs based on the phase jitter of a horizontal synchronization signal when superimposing a character signal can be reduced by a simple configuration. It is something.

In conventional character signal superimposition devices of this kind, in order to set the timing of character signal superimposition on a color television signal, a predetermined horizontal scanning period is selected and a fixed time interval is set from the rising edge of the horizontal synchronizing signal. From that point on, a predetermined number of clock signals consisting of a clock pulse train having a repetition frequency related to the color subcarrier frequency were counted to determine the timing for superimposing character signals. That is, in the conventional character signal superimposing device of this kind, as shown in FIG. , horizontal and vertical synchronization signals HS and VS are supplied to the timing pulse generation circuit 3, and the color subcarrier signal is also supplied to the timing pulse generation circuit 3.
SC is supplied to the clock generation circuit 4. The timing pulse generation circuit 3 generates a timing pulse T indicating the above-mentioned clock counting start time for setting the superimposition position in the horizontal scanning period at which a character signal is to be superimposed, and supplies it to the character signal generation circuit 5. Clock generation circuit 4 generates continuous clock pulses CL having a repetition frequency that is 4/5 times the frequency of input color subcarrier signal SC, and also supplies them to character signal generation circuit 5. The character signal generating circuit 5 counts clock pulses CL from the arrival of the above-mentioned timing T, which has a fixed time interval with respect to the horizontal synchronizing signal in the horizontal scanning period in which the character signal is to be superimposed, and calculates the clock pulses CL as described above. A time point for starting character signal superimposition is set, and a character signal string of a predetermined number of bits is supplied to the superimposing circuit 1 from the starting point of superimposing, and in the superimposing circuit 1,
The character signal string is superimposed every predetermined horizontal scanning period in the vertical retrace interval of the input color television signal, and a superimposed output signal is sent out.

As mentioned above, in the conventional character signal superimposing device of this kind, the character signal generating circuit 5 changes the clock pulse CL from the time of input of the timing pulse T formed from the horizontal and vertical synchronizing signals HS and VS to its rising edge. The character signal superimposition start point is set by counting at the point in time, but each horizontal and vertical synchronization signal
Since HS, VS and the color subcarrier signal SC do not have a specific relative phase relationship, the relative relationship at the rising edge of the timing pulse T and clock pulse CL is not uniquely determined, but is mutually dependent. Sometimes they are far apart, and sometimes they almost coincide. However, horizontal and vertical synchronization signals
Since both HS, VS and the color subcarrier signal SC have extremely good stability for a color television image transmitter, the timing pulse T and clock pulse CL generated in connection with these signals are extremely stable. Since it has good stability, once the rising edges of both signals almost match, that state will continue for a long time unless the input color television signal is switched. However, while the phase of the clock pulse train CL, which has a repetition frequency multiplied by the color subcarrier frequency, is always approximately constant, the synchronization signal, especially the horizontal synchronization signal HS, to which the timing pulse T is associated is When a signal is transmitted over a long distance, it is often subject to phase jitter caused by noise on the transmission path. Therefore, as mentioned above, when the rising points of the timing pulse T and the clock pulse CL are almost the same, as shown by the time widths in the respective signal waveform diagrams shown later, the horizontal synchronizing signal HS is applied. If there is phase jitter, phase jitter will also occur at the rising edge of the timing pulse T, so the clock pulse CL that is close to the rising edge of the timing pulse T
There will be cases where the context with respect to the rising point of is constantly changed. As a result, as described above, the character signal superimposition start point, which is set by counting a predetermined number of clock pulses CL that appear after the rising edge of the timing pulse T, is determined by the timing pulse T's rising edge point depending on the phase jitter of the timing pulse T. Since it is before and after the rising point of pulse T, it is always almost 1
It will fluctuate by the clock cycle. Therefore, an irregular phase shift occurs in the superimposed position of the superimposed text signal, and depending on the model of the teletext receiver,
Text broadcasting is caused by erroneously detecting a control digital signal inserted immediately before a text information signal to identify and extract the text information signal multiplexed during a specific horizontal scanning period in the vertical retrace period of a television signal. This may result in unreceivable reception or a severe deterioration in image quality.

In order to prevent unreceivable reception and image quality deterioration due to the phase shift of character signals, conventional character signal superimposition devices also have a phase synchronization function, as shown in Figure 2, in contrast to the configuration shown in Figure 1. A synchronous disk 6 for genlock etc. is inserted between the synchronous separation circuit 2 and the timing pulse generator 3, and the timing pulse T is inserted between the synchronous separation circuit 2 and the timing pulse generator 3.
In addition to maintaining an appropriate fixed time interval between the rising points of the clock pulse CL and the clock pulse CL, the horizontal and vertical synchronization signals HS and VS are phase-synchronized with respect to the color subcarrier signal SC to achieve appropriate phase synchronization. It generated horizontal and vertical synchronization signals HS' and VS'. If the timing pulse T is formed in relation to the horizontal and vertical synchronizing signals HS' and VS', even if there is phase jitter in the timing pulse T based on the phase jitter of the synchronizing signal, the rising point of the clock pulse CL will be Since the counting result of the clock pulse CL can be far enough away from the rising edge of the timing pulse T to be completely unaffected by its phase jitter, the phase of the clock pulse CL can be separated enough from the rising edge of the timing pulse T to the extent that it is not affected by the phase jitter. Shifts no longer occur irregularly.

However, in this conventional character signal superimposition device, synchronization signals HS and VS and color subcarrier signals
Since a synchronization board is used for phase synchronization with the SC, not only is the configuration complicated and expensive, but if the synchronization board goes out of sync, the scanning line on which the character signal should be superimposed will shift. However, there was a serious drawback in that the image quality deteriorated much more severely than the image quality deterioration caused by the phase shift described above.

The object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to provide a character signal superimposition device with a simple structure that does not cause other problems such as loss of synchronization and does not cause a phase shift in the character signal superimposition position. Our goal is to provide the following.

That is, in the character signal superimposition device of the present invention, when the rising points of the timing pulse T and the clock pulse CL are close to each other, the phase of the clock pulse CL with a duty ratio of 1/2 is inverted or the phase of the clock pulse CL is changed by 180 degrees, that is, π. By shifting the clock pulse CL by the same amount, the rising point of the clock pulse CL can be made to be far apart from the rising point of the timing pulse T, and a simple structure can be used to prevent a phase shift from occurring at the start of character signal superimposition due to phase jitter occurring in the timing pulse T. A phase setting circuit is used to appropriately set the phase of the clock pulse train CL, and it is possible to set the phase of the clock pulse train CL appropriately from a predetermined time point with a predetermined time interval with respect to the horizontal synchronization signal during a predetermined horizontal scanning period of a color television signal. In a character signal superimposing device that superimposes a character signal at a timing related to a time point when a predetermined number of points of a predetermined phase of a clock signal having a repetition frequency related to a color subcarrier frequency is counted, a timing signal generated at the predetermined time point; The clock phase setting circuit is characterized in that the clock phase setting circuit sets the phase of the clock signal in such a manner that the point of the predetermined phase is separated from the predetermined time point according to the result of phase comparison with the clock signal. .

The present invention will be described in detail below with reference to the drawings.

As mentioned above, in the character signal superimposing device of the present invention, when the rising edge of the clock pulse CL is close to the rising edge of the timing pulse T, the rising edge of one signal waveform is changed to a falling edge. In order to separate the rising points of both clock pulses from each other, phase inversion is applied to the clock pulse train CL, but such phase inversion of the clock pulse train cannot be performed at least during the character signal superimposition period. Furthermore, once the clock phase is set, the set phase is maintained for a sufficient period of time because the clock pulse train itself is stable, as described above. This should be done prior to the start of superimposition. That is, for example, when switching programs in which the input color television signal on which the character signal is to be superimposed originates from a different station, if the required phase inversion is performed after determining the clock phase prior to superimposing the character signal, The clock phase is maintained continuously.

FIG. 3 shows an example of the basic configuration of the character signal superimposition device of the present invention, which sets the clock phase as described above. Therefore, the illustrated configuration
A clock phase setting circuit 7 is added to the conventional configuration shown in the figure, and the other configurations and functions are the same as in the first example.
The illustrated conventional configuration is exactly the same as described above. That is, in the illustrated configuration, the horizontal and vertical synchronization signals HS and VS and the color subcarrier signal SC extracted from the input color television signal via the synchronization separation circuit 2 are sent to the timing pulse generation circuit 3.
and is supplied to the clock phase setting circuit 7 and the clock generation circuit 4, respectively. In the timing pulse generation circuit 3, horizontal and vertical synchronization signals
Based on HS and VS, a timing pulse T having a fixed time interval with respect to the horizontal synchronizing signal HS is generated during a predetermined horizontal scanning period and supplied to the character signal generation circuit 5. is a continuous clock pulse train with a repetition frequency that is 4/5 times the frequency of the input color subcarrier signal SC.
CL is generated and supplied to the clock phase setting circuit 7.

FIG. 4 shows an example of a detailed configuration of the clock phase setting circuit 7, which forms the basis of the device of the present invention in the basic configuration shown in FIG. The clock phase setting circuit shown in FIG. 4 is composed of a comparison gate generation circuit 8, a coincidence detection circuit 9, a clock phase inversion circuit 10, a gate generation circuit 11, and an HT pulse generation circuit 12. Among them, the comparison gate generation circuit 8 is
As mentioned above, in order to set or invert the clock phase during a period other than the character signal superimposition period, based on the horizontal and vertical synchronization signals HS and VS,
As shown in waveforms a and b, it has a time width that almost matches the horizontal scanning period other than the input color television signal superimposition period, and as shown in waveforms c and d, the horizontal synchronizing signal HS is within that time width. Comparison gate signal _G1 shown in waveforms b and c set to include one
is generated and supplied to the coincidence detection circuit 9. Also,
The HT pulse generation circuit 12 generates a signal from the sequential horizontal synchronizing signal HS shown in waveform d, which almost matches the rising edge of the horizontal synchronizing signal HS as shown in waveforms c and e. It rises at a certain time interval set equally,
A pulse HT having a waveform e having a short pulse width is generated and supplied to the coincidence detection circuit 9. Therefore, among the many pulses HT that occur sequentially,
As described above, each field contains one timing pulse that substantially coincides with the timing pulse T, which is the starting point of the superimposition start time, in the character signal superimposition horizontal scanning period. Furthermore, the gate generation circuit 11
are the rising points of successive clock pulses in the clock pulse train CL', which is set to a required clock phase by inverting the phase of the clock pulse train CL from the clock generation circuit 4 via the clock phase inversion circuit 10 as necessary. A gate signal G ₂ with a short time width including 2 is generated and supplied to the coincidence detection circuit 9. Therefore, in the coincidence detection circuit 9, when the pulse periods of the input gate signals G ₁ and G ₂ and the pulse HT all match, that is,
In the horizontal scanning period other than the character signal superimposition period, the timing pulse T, which coincides with one of the pulses HT, and the clock pulse CL' should be adjusted to such an extent that there is a possibility that the timing pulse T and the clock pulse CL' may be swapped due to the influence of the phase jitter of the timing pulse T. When the rising points of the output clock pulses CL' are close to each other, the coincidence detection output signal S is generated to control the clock phase inverting circuit 10, so that the rising points of the output clock pulses CL' are sufficiently separated from each other.

The operation waveforms of each part of the clock phase setting circuit having the configuration shown in FIG. 4 are as shown in waveforms a to _i shown in FIG. When this occurs, the phase of the input clock pulse CL is inverted to produce the output clock pulse CL', and when the gate signal _G2 and the pulse HT do not match and are separated from each other as shown by waveforms g and i, the input clock pulse CL is Let it be the output clock pulse CL' as it is. The timing chart of each signal waveform during such a clock phase inversion operation is shown in waveform a in FIG.
The timing charts of the various signal waveforms when the clock phase is not inverted are shown in the waveforms f in Fig. 6.
Shown in ~i.

Next, another example of the configuration of the clock phase setting circuit is shown in FIG. 7, and its respective signal waveforms and timing charts are sequentially shown as waveforms A to f in FIG. 8. _In the configuration example shown in _FIG .
4, each gate signal G ₁ , G ₂
When pulses HT and HT are simultaneously supplied to the AND circuit 13, the flip-flop 14 is inverted by the "1" output, and the state of the inverted output is maintained and guided to the resampling circuit 15, which outputs the output from the clock phase inverting circuit 10. By resampling with clock pulse CL', the coincidence detection output signal S
The inversion time of the clock pulse CL' is made to coincide with the rise time of the output clock pulse CL', and the coincidence output signal S' is supplied to the clock phase inversion circuit 10 to control the inversion of the clock phase. With this resampling operation, the eighth
The generation of a false clock pulse P, which occurs in the output clock pulse CL' when the phase of the clock pulse CL is reversed, as shown by waveform f in the time chart of the figure, is minimized.

In the character signal superimposing device of the present invention having the basic configuration shown in FIG. 3, the clock phase setting circuit 7 having the configuration shown above inverts the clock phase as necessary to set the output clock pulse CL in a desired manner. ' is supplied to the character signal generation circuit 5. In the character signal generating circuit 5, a clock pulse is generated in accordance with the arrival of the timing pulse T.
Start counting CL′ and count the predetermined number of clock pulses.
At the time when CL' is counted, a character signal of a predetermined length in the form of a packet signal is generated, and is supplied to a superimposing circuit 1 to be superimposed on a predetermined horizontal scanning period of an input color television signal and sent out. When superimposing them, the rising points of timing pulse T and clock pulse CL' are sufficiently separated, so even if there is phase jitter in timing pulse T, no phase shift occurs in the superimposition position of the character signal.

In the above explanation, the clock pulse repetition frequency used for character signal generation and transmission is set to 4/5 of the color subcarrier frequency, and the phase of the timing pulse T described above is determined by using the clock pulse train of this repetition frequency as is. Although the effect of jitter has been prevented, the effect of phase jitter can be prevented only when the amount of phase jitter occurring in the timing pulse T is smaller than 1/2 of the clock period. However, if the amount of phase jitter exceeds 1/2 of the clock period, the effect of the phase jitter cannot be avoided by the above-described circuit operation based on phase inversion of the clock pulse. Even in such a case, if the horizontal synchronization signal HS is guided to an automatic phase control circuit (APC circuit) to stabilize its phase, it is possible to reduce phase jitter caused by the transmission path, etc. When the phase jitter is reduced, the clock pulse CL
By multiplying the repetition frequency of , it is possible to reduce the phase shift amount based on the phase jitter of the timing pulse T set at the character signal superimposition start point by counting clock pulses, or to reduce the phase shift amount at the character signal superimposition start point when the clock phase is reversed. If the repetition frequency of the clock pulse CL is lowered and restored after reducing the amount of phase jitter, there will be no change at the rising edge of the clock pulse, so the amount of phase shift described above can be reduced absolutely. Therefore, the amount of phase shift at the start of character signal superimposition can be significantly reduced compared to the case where the influence of phase jitter is prevented by leaving the clock frequency as it is. .

As mentioned above, an example of the configuration of a clock phase setting circuit that sets the clock phase by multiplying and lowering the repetition frequency of the clock pulse CL is shown in FIG. 9, and the signal waveforms and timing chart of each part are shown in FIG. The waveforms a to g in FIG. 10 are sequentially shown. The illustrated configuration is an example in which the clock frequency is doubled and halved by the clock multiplier circuit 21 and the clock down-down circuit 22 before and after the clock phase inversion circuit 10, respectively. As shown by waveform g in the figure, it is possible to halve the amount of phase shift when the clock phase is reversed.

As is clear from the above description, according to the present invention, by simply adding a circuit with a simple configuration to the character signal superimposition device, it is possible to control the relative phase between the timing pulse and the clock pulse used for setting the character signal superimposition start point. This makes it possible to significantly reduce the phase shift of the character signal superimposition position compared to the conventional method, and to prevent the occurrence of transient disturbances when setting the clock phase due to clock phase inversion, thereby preventing malfunction of the character signal generation circuit. can be prevented.

In the above, an example has been described in which the duty ratio of the clock pulse is set to approximately 1/2 and the phase is inverted to separate the rising time of the timing pulse T and the rising time of the clock pulse CL. Of course, the present invention is not limited to this, and may be constructed by changing the duty ratio of the clock pulse and using a delay circuit, etc., as long as the above-mentioned effects of the present invention are not impaired.

Furthermore, the device of the present invention can be widely applied to broadcasting systems that superimpose packet-format character signals on color television signals, so it can be applied to signal superimposition in text broadcasting, data broadcasting, and the like.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of a conventional character signal superimposing device, FIG. 3 is a block diagram showing an example of the structure of the character signal superimposing device of the present invention, and FIG. 4 is a block diagram showing the clock phase thereof. A block diagram showing an example of the configuration of a setting circuit, FIGS. 5 and 6 are waveform diagrams sequentially showing signal waveforms of each part in the configuration shown in FIG. 4, and FIG. 7 shows another configuration of the clock phase setting circuit. FIG. 8 is a block diagram showing an example. FIG. 8 is a waveform diagram sequentially showing the signal waveforms of each part in the configuration shown in FIG. 7. FIG. FIG. 10 is a waveform diagram sequentially showing signal waveforms at various parts in the configuration shown in FIG. 1...Superimposition circuit, 2...Synchronization separation circuit, 3...
Timing pulse generation circuit, 4...Clock generation circuit, 5...Character signal generation circuit, 6...Synchronization board,
7... Clock phase setting circuit, 8... Comparison gate generation circuit, 9... Coincidence detection circuit, 10... Clock phase inversion circuit, 11... Gate generation circuit, 12
...HT pulse generation circuit, 13...AND circuit, 1
4...Flip-flop, 15...Resampling circuit, 21...Clock multiplication circuit, 22...Clock down/down circuit.

Claims (1)

[Claims for Utility Model Registration] 1. During a predetermined horizontal scanning period of a color television signal, a clock signal having a repetition frequency related to the color subcarrier frequency is transmitted from a predetermined time point having a predetermined time interval with respect to a horizontal synchronization signal. In a character signal superimposing device that superimposes a character signal at a timing related to a time when a predetermined number of points of a predetermined phase are counted, the predetermined signal is superimposed according to the result of a phase comparison between the timing signal generated at the predetermined time and the clock signal. A character signal superimposition device comprising a clock phase setting circuit that sets the phase of the clock signal in such a manner that a phase point is separated from the predetermined time point. 2. The clock phase setting circuit includes at least the following:
a first gate generating circuit that generates a first gate signal for a period including a horizontal synchronizing signal period approximately corresponding to one horizontal scanning period in which the character signal of the color television signal is not superimposed; a second gate generation circuit that generates a second gate signal that substantially corresponds only to the point; and a coincidence detection circuit that detects that the first gate signal, the second gate signal, and the timing signal coincide in time. Equipped with
2. The character signal superimposition device according to claim 1, wherein the phase of the clock signal is set in accordance with the coincidence detection output of the coincidence detection circuit. 3. Reduce the duty ratio of the clock signal to approximately 1/2.
In addition, the clock phase setting circuit includes at least a clock phase inversion circuit that inverts the phase of the clock signal depending on the proximity of the predetermined phase point of the clock signal to the predetermined time point. A character signal superimposition device according to claim 1 or 2 of the patented utility model claim. 4. After setting the phase in the manner described above for a multiplied clock signal obtained by multiplying the repetition frequency of the clock signal by a predetermined ratio, the repetition frequency of the multiplied clock signal is lowered by the ratio. A character signal superimposition device according to claim 1, characterized in that the character signal superimposition device is configured to set a phase of .