KR100291715B1 - Data Packet Processing System - Google Patents

Abstract

In a system for processing digital data streams divided into packet units representing MPEG coded image information, the encoder executes a transport encoder 20 for forming a data packet, and various signal processing functions such as error correction processing and modulation, for example. For output processors 40 and 48. Request / acquire data packet from transport encoder for processing during acquisition interval. The system also includes devices 25 and 30 to ensure that the reference (sync) bytes of the initial data packet are automatically aligned with the beginning of the acquisition interval, even when any system reset occurs. In the described embodiment, the alignment of the first data packet following a system reset is a joint of the Start Of Packet (SOP) flag that occurs concurrently with the logical networks 32, 36, 38 that control data passing in response to the reference bytes and flags. It is facilitated by the work.

Description

Data packet processing system

Recently, systems for processing and transmitting digital high definition television signals have been developed in the field of video signal processing and transmission. One such system is US Pat. No. 5,168,356, filed by Acamporra et al. In this system, a codeword data stream is sent to a transport processor, which contains a codeword provided according to the MPEG data compression standard as known in the art. The main function of the transport processor is to convert variable length codeword data into packed data words. Packed data word accumulations, called data packets or data cells, are preceded by a header that contains information for identifying the associated data word with other information. The output of the transport processor is therefore a packetized data stream containing a series of transport packets. The transport packet format improves resynchronization and signal recovery at the receiver, for example, if signal transmission is interrupted due to a transport channel interruption, by providing header information, the receiver may have lost or modulated the transmitted data. When re-entry points can be determined for the data stream.

At the end of the encoder / transmitter of a system employing the packetized datastream format, the output modulator typically derives data packets from the preceding encoder (transport processor) and processes these data as required by the particular system. For example, processing by a modulator may include a variety of functions, including the ability to add forward error correction (FEC) bytes to the packet boundary to correct errors, and against burst errors in transmission media. Protecting byte interleaving, trellis (or other) coding for robustness, spectral shaping, and interleaving of the resulting symbol datastream for additional burst error protection have.

The modulator can operate in two ways to perform this function. The modulator may obtain (request) data from the transport encoder per constant rate packet or obtain packet data with variable length pauses between acquiring packets, each pause The variable length of the stop is a function of the time required to achieve the process mentioned above. In the first case, the modulator must provide large data buffers to accommodate the data rate conversion, for example during FEC and symbol generation. These buffers must also be provided to the receiver modulator. The latter variable pause technique is preferred because no large buffer is required, and the start-stop nature of the process is easily done by existing compression and transmission encoders without the need for additional hardware.

The modulator is a control element of a good variable interruption system. In such a case, the modulator causes the transport datastream to correctly receive one data packet, where one data packet is 188 bytes for a system according to the MPEG-2 compression standard, as is known. The data flow is suppressed to carry out the FEC and other processes described above. In order to properly process a datastream packet in a system employing the MPEG-2 compression standard, the first data received by the modulator, for example in response to a data packet enable signal, must be a sync byte since the sync byte indicates the beginning of the packet. Should be

TECHNICAL FIELD The present invention relates to the field of digital video signal processing, and more particularly, to a system for maintaining packet alignment in a packetized data system suitable for use in high definition television systems.

1 is a block diagram showing a portion of a video signal processor and encoder comprising an apparatus according to the invention.

2 is a timing diagram for signals related to the operation of the system shown in FIG.

3 shows a detail of a part of the apparatus of FIG. 1;

4 shows another embodiment of the apparatus shown in FIG.

5 is a timing diagram for signals associated with the apparatus of FIG.

FIG. 6 shows a detail of a part of the apparatus of FIG. 4; FIG.

The present specification recognizes that alignment of the first byte interval of the modulator data enable signal to the start of a packet is difficult unless a complex interface is merged with a multi-level protocol. It is also recognized that even with such complex interfaces, significant problems can arise, for example, when the system experiences a reset state or system fluctuations associated with system operation. If the transport encoder has valid data when it comes back on-line during the modulator data enable period, the condition may appear at an unrecoverable offset between the beginning of the data packet and the subsequent initiation of the modulator enable signal from the start and consequently Incorrect data processing can be performed.

A system in accordance with the principles of the present invention automatically freezes a reference byte (eg, sync byte) at the beginning of a data acquisition interval when the preceding encoder requests data, even when there is any system reset / restart. This problem is solved by allowing it to be printed. In an exemplary embodiment, alignment by the first data packet following a system reset is facilitated by using, with the control logic network, the initiation of a packet flag that occurs concurrently with the reference byte.

In FIG. 1, variable length compressed codewords according to the MPEG-2 standard are provided by the video signal processing source 10 to the input processor 12 of the transport processor / encoder 20. The main function of the transport processor 20 is to pack the codeword into a fixed length data word, which is finally formed of fixed length (188 byte) data packets, each of which is a data packet. Will be placed before the header. Input processor 12 provides a variable length codeword to data packer 14 and provides control signals and flags to controller 15 and header generator 16. For example, the controller 15 monitors the accumulation of word length data from the input processor 12 to complete a fixed length data word, and sends the appropriate word address and word control signal to the data packer 14. The word address allows variable length codewords to be concatenated properly. The word control signal describes a concise word and provides marking and alignment flags when needed. The codeword source 10 may merge the data packer 14 and the controller 15. In such a case, multiple sources of packed data may be multiplexed directly to the input of the data / header combiner 18. Suitable headers are provided by the header generator 16 to indicate program source, service type, and other information regarding payload data.

The packed data from the packer 14 is passed to the data-header combiner 18, i.e., the packet generator, which also writes data write and enable signals that can write valid data to the input FIFO buffer in the packet generator 18. Received from the packer 14. Each time a packed data word is valid, the packed data word is sent to the packet generator 18. Similarly, the transport header is sent to the input FIFO buffer of the packet generator 18 whenever the header is valid.

The information used by the header generator 16 to form the header is obtained from the input processor 12 and the controller 15. The header generator 16 also provides a write enable output signal to the packet generator 18 to indicate that the header is ready and that the header can be written to the input FIFO. Each header contains information related to the data of the packet connected with the header. The header information assists in synchronization, program identification, descrambling control, demultiplexing, path routing, and payload form of the receiver. In this example, the first header section includes MPEG sync bytes. Note that the header generator 16 also generates a Start Of Packet flag in parallel with the sync byte occurring at the start of packet in the system. The packet generator 18 places each packed data payload with a suitable header in front, as described below, and sends the resulting transport packet and the parallel SOP flag to the transport stream interface device 25.

Transport packets and SOP flags from the transport processor 20 are transmitted to the modulator 40 by the interface device 25 and the logic circuit 30. The modulator 40 includes an output processing and modulation device 48 that performs various signal processing functions on the packetized data before the packetized data is configured for transmission to an output channel such as a satellite, cable, or terrestrial broadcast channel. Include. In this regard, the output device 48 may include a modulation network including FEC, interleaving, coding, spectral shaping and, for example, a quadrature amplitude modulation (QAM) network or a residual sideband (VSB) modulation network. have. The data packets processed by the output device 48 are obtained by elements 42, 44, 46 coupled with the modulator 40 integrated into the logic circuit 30 and the interface 25. These elements merge with each other such that the first data entry of the acquisition window interval is an MPEG-2 sync byte that marks the start of the packet. Since the modulator is a control factor, the start of the packet must reach the origin of the acquisition signal (inside the modulator) that coincides with the occurrence of the first byte interval of the signal. In particular, these elements are merged with each other so that the MPEG synchronization at the beginning of each data packet, even when the modulator 40 requests / extracts the transport packet for processing, and even when a chaotic condition such as any system reset occurs. Allow the bytes to be automatically aligned at the beginning of the data acquisition interval. As will now be discussed, such alignment can be done quickly after a system reset, or a chaotic state such as clock sleep or phase jump agitation, and in this example is easily facilitated by using the initiation of a packet (SOP) flag that coincides with the sync byte. Can be.

The operation of the system of FIG. 1 will be described with reference to the signal timing diagram of FIG. 2. The window signal generator 42 of the modulator 40 generates a modulator (Mod) window signal including an enable period and a short period of disable period. The enable period represents the time taken by the modulator to obtain a data packet for processing. As described above, the disable interval indicates the time taken to provide the FEC, interleaving, and coding functions by processing the obtained packet by the modulator. The length of each disable interval is a function of the time required for modulator 40 to process the packet. Although the processing time is typically the fixed length described above, the modulator may send specific transmitter information, such as equalization training, for which transmission of packet data may be disabled. However, the described synchronization system also works in the specific case where the disable period between packets is any period. In this example, the disable periods are shown to have a fixed length for simplicity and to facilitate a clear understanding of the following discussion of the timing relationship between the signals shown.

In relation to the modulator window signal, generator 42 also generates start and stop timing signals, each of which includes a series of positive fields for one clock period. The rising edge of the start pulse coincides with the start of the enable period and the rising edge of the stop pulse coincides with the end of the enable period. The modulator window signal is delayed by one clock period by the device 44 to produce an acquisition signal, which is shown in the lower part of FIG. This signal controls the operation of the data acquisition device 46, obtains a data packet (data B described later) during the acquisition interval, and transmits the obtained data packet to the modulator 48 for processing. The acquisition signal is the same as the modulator window signal except that one clock delay associated with the modulator window signal is delayed. The modulator window signal, acquisition signal, stop and start signal operate from time to time and are not subject to start-stop operation.

In FIG. 2, a signal designated as transport data In corresponds to a packetized data stream signal appearing at the output of interface 25 in response to an input transport packet applied to interface 25. The operation of the system of FIG. 1 will first describe a situation in which any agitation occurs that will result in a system reset in the transport processor 20, in which case the output buffer typically associated with the packet generator 18 is " flushed " (flush) ", which frees the buffer. This state is described by the first 20 bytes of the transport data (In) signal of FIG. 2, which contains the symbol "?". In this example, the valid data packet to be obtained by the apparatus 46 and 48 for processing is defined by a 16 byte interval 123456789ABCDEF that contains the sync byte at the start of the packet. The sync byte interval of each packet is highlighted by shading. The SOP (In) flag generated by the transport processor shown in FIG. 2 occurs simultaneously with the sync byte section in the transport data (In) signal.

The Transport Enable signal is generated by the set-reset flip-flop 38 in the network 30 in response to the rising edge of each start pulse from the generator 42 and the generator 42 being flipped. By setting flop 38, the transport enable signal starts a start pulse one clock later. The transport enable signal is usually time-aligned to the acquisition signal and similarly defines the packet acquisition interval.

In the following sequence of times, the time intervals T1-T2 and T2-T3 define the normal enable and disable intervals of the modulator window signal, which are executed from time to time, respectively. Under normal conditions, the transport enable period begins at time T4 after the start pulse and indicates that modulator 40 is about to acquire a packet for processing. However, at this time, the packet data is invalid due to any disruptive reset state in which the preceding FIFO buffer is empty. This lack of packet data is indicated by the low logic level of the data valid signal and the cause thereof will be described with reference to FIG. Since the data valid signal is low, the modulator registers 34 (or in FIG. 4) during the acquisition period T4-T5 and all the time preceding this period when the acquisition window signal is high and the data valid signal is low. The data held in the register 55 is obtained continuously. This is a normal startup phenomenon.

The positive performance data valid signal appears at time T5 and indicates the appearance of the first valid data in the form of sync bytes of the transport data (in) signal (shaded region). The positive data valid signal is a logic circuit responsive to the provision of a transport enable signal indicating that packet data has been found and a "buffer fullness" flag indicating that the data is present in the preceding buffer (in the form of sync bytes). 3). With the appearance of SOP (IN) at time T5, which coincides with the re-appearance of valid sync bytes in the data stream, an alignment process is started in which the start of an upcoming data packet is properly aligned with the acquisition interval of the acquisition signal.

In connection with the circuit 30 of FIG. 1, packet alignment processing is performed by the interface 25 transition register 32 (“D” flip-flop) to indicate a clock delayed by SOP A at the “Q” output of the register 32. Start with the SOP flag from. The SOP A flag resets the flip-flop 38 by the logic OR gate 36 and causes the positive transport enable signal to return to the low logic level at time T6. This reset operation disables the output register of interface 25 (shown in FIG. 3), thus stopping the flow of data even if the modulator window signal is not affected. The interruption of the data flow is reflected in the data valid signal. The data valid signal operating at the transport enable signal level is truncated and simultaneously returned to the low logic level. The resetting of the flip-flop 38 by the SOP flag generates an ineffective next stop pulse. The output register 312 of FIG. 3 and the registers 32 and 34 of FIG. 1 hold consecutive data words. These registers thus form a pipeline structure and operate with shift register behavior. To stop the shift process, all register stages must be disabled at the same time.

Register 32 and similar serial device 34 are clocked by signal transport Clk, which is the inversion of clock modulator Clk applied to modulator 40. The data inputs of registers 32 and 34 are enabled by the positive data valid signal. Since the positive data valid signal is prohibited by the resetting operation of the SOP A flag at time T6, the registers 32 and 34 cannot next respond to the input data. As a result, each register output repeatedly holds the last data byte read. In the case of the register 32, the repeated output data is data from the first data stream byte section ("1") along the sync byte section as indicated by the data A signal in FIG. In the case of register 34, the repeated output data is sync byte duration data as indicated by the data B output signal of FIG.

The next start pulse “sets” the flip-flop 38, whereby the positive transport enable component starts at time T7 aligned with the falling edge of the start pulse. When flip-flop 38 is set to resume normal operation at this point, the sync byte of data B ("sticky" at the output of register 34) is in the enable period of modulator window signal initiation at time T7. The first byte to appear. The positive data valid signal starts at the same time and causes registers 32 and 34 to pass data from input to output, as indicated by data A and data B in FIG. The positive transport enable and data valid signal components are aligned with the acquisition intervals of the acquisition signal (e.g., T7-T8 and T9-Y10), so that each acquisition interval contains a complete data packet containing a sync byte followed by 15 data bytes. Include as appropriate. All successive SOP A pulses align with the stop pulse as shown, and if system fluctuations do not occur, then data acquisition is automatically realigned by an independent reset operation of the SOP flag as described.

Thus, it can be seen that the described system advantageously achieves proper alignment of packets within the packet acquisition interval immediately after any system fault or reset / restart. In particular, the packet sync byte appears appropriately at the start of a packet acquisition interval with a minimal disruptive offset of the packet data stream. Some examples fit this point. The first case is when a packet longer than a fixed length of 188 bytes is wrongly placed in the datastream. The stop signal resets the flip-flop 38 of FIG. 1, and the next packet produces an abnormal packet that does not start with the sync byte because the sync byte remains in the FIFO 310 (FIG. 3). The appearance of the sync byte causes the data flow to stop again as a result of the reset of the flip-flop 38 when the start signal resumes the data flow. This produces a second abnormal packet but from this point synchronization is achieved. The second case is when a packet with fewer than 188 bytes is wrongly placed in the data stream. The start of packet (SOP) flag resets the flip-flop 38 of FIG. 1 and produces an abnormal packet. The successive appearance of the stop pulse is unnecessary because flip-flop 38 has already been reset. The third case is when the stop signal from the modulator arrives early. Similar to the first case, two consecutive abnormal packets are made. Also, the case where the stop signal occurs late is similar to the second case. In all cases, synchronization is automatically restored. In particular, in noisy environments, there is an advantage of breaking the stop signal line to the OR gate 36 (which eliminates the need for the gate 36) and using only the SOP flag to reset the reset flip-flop 38.

Under normal conditions, the system is reset and data passing to the modulator 40 is inhibited in response to the appearance of a positive SOP (A) flag or positive stop pulse, where the plug or pulses coincide normally. Data passing continues to be prohibited during successive modulator processing intervals between acquisition intervals. Data passing resumes when registers 32 and 34 are enabled again in response to the next start pulse, thereby allowing registers 32 and 34 to pass data and fit as the first data word of the acquisition window under normal circumstances. Provide a sync byte.

3 shows the interface device 25 of FIG. 1 in more detail. Transport packets and SOP flags from transport processor 20 are provided to each input of FIFO buffer 310. The buffer 310 also receives a write clock and a write enable signal from the transport processor. The modulator clock signal from network 30 (FIG. 1) is applied to the clock input of output register 312 and the transport enable signal from network 30 is applied to the enable input of output register 312. The transport data signal (transport packet) and the SOP flag from the FIFO 310 are transmitted to the network 30 of FIG. 1 by the register 312. The fullness flag provided by the FIFO 310 can be programmed to indicate the status of the data polarity of the FIFO 310, eg, from 1 byte to several bytes or packets in the FIFO 310. The fullness flag output from the register 312 and the transport enable signal from the network 30 are provided to a logical AND gate 318 that generates a data valid signal when the fullness flag and the transport enable signal are present. .

The transport clock provided back to the network 30 is derived from the modulator clock signal after inverse conversion by the inverter 314, which represents a delay of less than one clock cycle. When the modulator clock signal and the transport enable signal emanate from the modulator and register properly with each other, there may be an arbitrary delay (e.g. cable and device delay) between the modulator and the transport processor because the two signals pass through the same delay path. However, the modulator clock signal and the transport enable signal appear in the FIF0 310 and the output register 312 of FIG. 3 to maintain such registration. The transport data signal has a defined relationship to the modulator clock at the transport output. However, the relationship with the modulator clock signal that occurs when the transport data signal reaches the modulator input depends on the cable delay because only the transport data passes through the delay path. This problem is solved by sending a replica of the modulator clock, the transport clock, along with the transport data to ensure registration. Preferably the inverse of the modulator clock is sent since this signal is correctly located with the transport data (normally centered on the rising edge). If the delay between the modulator and the transport processor is accurately defined, the transport clock can be eliminated and the delay trimmed conversion of the modulator clock can be used in the modulator.

The generation of a positive data valid signal indicates that there is data in the FIFO 310, valid or invalid as indicated by the fullness flag, and that the modulator is requesting data (as indicated by the transport enable signal). . If the FIFO 310 contains invalid data, such data is transmitted to the modulator during the acquisition period. In practice, however, this typically occurs rarely because both the FIFO 310 and the output buffer of the transport processor are emptied when system disturbances require transport resets, and the first data byte is a valid sync byte.

The device of FIG. 6 is a variant of the device of FIG. 3. 6 is similar to FIG. 3 except that enable register 610 has been added as shown. The use of registers 610 improves noise immunity, which may be required in the case of long cable connections between the network 30 and the transport interface 25. The use of registers 610 adds one clock delay to the system, which is compensated for by modifying network 30 as shown in FIG. The network 30 of FIG. 4 is similar to the network 30 of FIG. 1 except that a register 55 is added. Since the register 55 adds one more clock delay, the delay generated by the element 44 increases by an amount corresponding to the two clock delays. A timing diagram for the system of FIG. 4 is shown in FIG. 5. The system of FIG. 4 is similar to the system of FIG. 1 except that data packets from the data C output of register 55 are obtained for processing during the acquisition period, for example, between times T7 and T8 of FIG. The disclosed apparatus may be further modified to include additional registers or otherwise modified to compensate for the additional delay generated by the device corresponding to register 610 of FIG. 6.

In an alternative system of the system described above, the End of Packet flag may be used instead of the Start of Packet flag as disclosed. In that case the point of detection moves to the output of register 34 of FIGS. 1 and 4. A sync byte structure (eg 47 Hex) can also be found in the datastream itself. This is difficult due to the value of the sync byte that can be achieved, although the given start / stop (enable / disable) nature of the system operation is not the only one. Using a time variable disable interval becomes more complex (eg, a programmable counter may be needed that varies with each packet cycle).

The present invention is applicable to a system for maintaining packet alignment in a packetized data system suitable for use in a high definition television system.

Claims (16)

A system for processing a packetized digital data stream containing video information, the system comprising: transport processor means (20, 25) for generating a data packet in response to input data (10) and by said transport processor means; Means for processing the received data packet, said processing means 40 for acquiring said data packet in an acquiring interval and processing said data packet in processing intervals between said acquiring intervals and transmitting said data packet to said processing means; Means (25, 30, 32, 34), said transport processor means and said data packet processing means, and in response to a state of the data stream from said transport processor means, Facilitate automatic alignment of the reference data component (sync byte) of the data packet at the beginning of each acquisition interval A data packet processing comprising synchronization means (32, 36, 38, 312, 314, 318) for facilitating automatic alignment when an abnormal operating state in which a normal data stream from the transport processor means is disrupted is stopped. system. 2. The data packet processing system of claim 1, further comprising means for generating a signal (fullness flag) indicative of a memory occupation state of said transport processor means, said synchronization means responsive to said occupation state signal. . 3. The data packet processing system of claim 2, wherein said transport process means is reset in response to said abnormal operating state. 2. The apparatus of claim 1, further comprising means for providing a signal SOP indicating a packet boundary and means 36 for adjusting the operation of the synchronization means in accordance with the function of the signal indicating the boundary. Data packet processing system. The data packet processing system of claim 1, wherein the data packet includes MPEG code information, and the reference data component is a synchronization component that precedes the data packet. The data packet processing system of claim 1, wherein the acquisition sections are sections having a substantially constant duration, and the processing sections are variable sections. The data packet processing system according to claim 1, wherein said processing means is means for executing an error correction processing and a modulation function. The data packet processing system of claim 1, further comprising means (16) for generating a flag (SOP) simultaneously with the generation of said reference data component at the start of a data packet. 9. The control means (32, 34) according to claim 8, wherein the synchronization means resets the synchronization means such that, in response to the data packet and the flag (SOP), no data passes to the processing means during the processing interval. 36, 38). 10. The apparatus of claim 9, further comprising: means for providing a periodic window signal comprising enable intervals associated with the acquisition intervals and interfering disable intervals associated with the processing intervals; Means (42) for providing timing signals (Start, Stop) to the control means, respectively, coincident with the start of the enable periods and the end of the enable periods of the periodic signal associated with the enable periods of the window signal. Means (44) for providing an acquisition signal, corresponding to said acquisition intervals of said processing means, for controlling the acquisition of data to be processed by said processor means, and said enable intervals of said window signal And the intervals related to the disable intervals normally and respectively, and enable the data enable interval (transport enable; Tran Ena means (38) for providing an enable signal to the control signal, the enable signal comprising a first state and a second state associated with passing of data and prohibiting passage of data, respectively, in response to the flag. And said providing means (38). 2. The apparatus of claim 1, wherein the reference data component is a synchronization component, and the transport processor means generates addition of alignment flags corresponding to each of the synchronization components to the data packet, and the transmission means responds to the alignment flags. Data packet processing system is prohibited from passing data to said processor means. 12. The data packet processing system as claimed in claim 11, wherein said synchronization means comprises forbidden storage means (32, 34) to prevent data from being passed to said processor means in response to said alignment flags. 2. The apparatus of claim 1, further comprising: means for providing a first clock signal (Mod clock) to said processing means and said transport means (25, 310, 312), and a copy of said first clock signal (Tran Clock). Tran Data) means for transmitting from said transport means to said transmission means. 2. The apparatus of claim 1, further comprising: means for providing a first clock signal to said processing means and said transport means (25, 310, 312), said transport means being connected to said transport means, and Means (314) for deriving a second clock signal and means for providing said second clock signal to a clock input of said transmitting means. 15. The data packet processing system of claim 14, wherein the second clock signal is an inversion signal of the first clock signal. A system for processing a packetized digital data stream containing video information, the system comprising: transport processor means (20,25) for generating a data packet in response to input data, the transport processor means being unpredictably reset Means for processing the transport processor means (20, 25) for interrupting the data stream of the data packet from the transport processor means and for data packets generated by the transport processor, wherein The processing means 40 for acquiring and processing the data packet in processing intervals between the acquisition intervals, means 25, 30 for transmitting the data packet to the processing means, the transport processor means and the Coupled to processing means for processing a data packet, the beginning of an acquisition interval being Packet data processing system including the reference of the data packet that appears after a reset of the processor means spot data component (synchronization byte) automatic synchronization means (32, 36, 38, 312, 314, 318) to coincide with the.