JPH10501941A - Synchronization of packetized digital data stream to output processor in television signal processing system - Google Patents

Abstract

In a system for processing a packetized digital data stream representing MPEG encoded image information, an encoder includes a transmission encoder (20) for forming a data packet, and error correction processing and modulation. And an output processor (40, 48) for executing various signal processing functions such as. During the acquisition period, the output processor requests / acquires data packets from the transmission encoder for processing. The system also includes a device (25, 30) that ensures that the reference byte (sync byte) at the beginning of the data packet is automatically aligned with the beginning of the acquisition period in the event of any system reset. Including. In the illustrated embodiment, the alignment of the first data packet following a system reset includes a Start Of Packet (SOP) flag that matches the reference byte and logic that controls the passage of data in response to the flag. It can be easily performed by the cooperative operation of (32, 36, 38).

Description

DETAILED DESCRIPTION OF THE INVENTION            To output processor in television signal processing system            Synchronization of packetized digital data streams                                 Background of the Invention   The invention relates to the field of digital video signal processing, For more details, HDTV Packetized data suitable for use in high definition television systems. System for maintaining packet alignment in data systems About.   Recent developments in the field of video signal processing and transmission include: Digital HDTV Systems for processing and transmission. One such system is U.S. Pat. 168, No. 356 . In this system, Codes including code words conforming to the well-known MPEG data compression standard A codeword data stream is transmitted by a transport processor (transport proc). essor). The main function of the transmission processor is to pack variable-length codeword data. Packing into a written data word. Of packed data words Accumulation is called a data packet or data cell, other In the information, In particular, a header containing information identifying the relevant data word is prepended. Be killed. That is, The output from the transmission processor is The sequence of transmitted packets And a packetized data stream. The format of the transmission packet is For example, after signal disruption due to transmission channel interference, Loss or obstruction of transmission data In the event of corruption, the point of reentry into the data stream is By providing header data that can be determined by r), Resynchronization and signal at the receiver Expanding the advantages of signal restoration.   Encoding in systems that use the packetized data stream format At the transmitter / transmitter end, An encoder (transmission processor) generally preceded by an output modulator ) To extract data packets from the data according to the requirements of the particular system. To process. For example, For processing by the modulator, Forward error to packet boundary -Correction (Forward Error Correction; FEC) bytes, On transmission media Byte interleaving for protection against burst errors, Be stubborn The addition of trellis (or other) codes for Spectral shaping, Further additional Interleaving of symbol data streams obtained for burst error protection It includes various functions including error correction processing by Bing.   The modulator can operate in two different ways to perform these functions . The modulator acquires data from the transmission encoder at a constant rate for each packet (required Request), Or packet data with a variable length pause during packet acquisition Data can be obtained. Each of this variable length pause Perform the process described It should be a function of the time needed to get it. In the first case, The modulator provides a large data buffer, For example, during FEC and symbol generation Data rate conversion. These buffers are It can also be provided with a receiver modulator. Need to be provided. The latter variable pause technology is No large buffer is required, Additional c Processing by existing compression transmission encoder circuits without the need for hardware This is preferable because it can easily cope with the nature of starting and stopping.   The modulator is the control element in a preferred variable pause system. In such a case, The modulator can receive exactly one data packet as the transmitted data stream You. This data packet is As is well known, a system conforming to the MPEG2 compression standard Is 188 bytes. The data flow is The aforementioned FEC and other processes Is prohibited from permitting the execution of the transaction. For systems that use the MPEG2 compression standard In order to process data stream packets correctly in Start of packet Is a sync byte. For example, Data packet The first data received by the modulator in response to the There must be.                                 Summary of the Invention   The beginning of the modulator data enable signal requesting data from the transmit encoder The alignment of the byte period and the start of the packet is Complex with multi-level protocols It will be recognized herein that it would be difficult without including the appropriate interface. Sa In addition, Even with such a complex interface, For example, to power on the system Indicates that the system encountered a reset condition due to system instability. If It will be appreciated that difficult problems can arise. This transmission encoder changes Data available because it can be returned online during the controller data enable period If you have Such a condition is the start of a data packet and the modulation after that point. Causes an irrecoverable offset during the next start of the detector enable signal. I This results in faulty data processing.   In a system according to the principles of the present invention, When data is requested from the preceding encoder If Even if there is any system reset / restart, Data path The reference byte (eg, sync byte) prepended to the packet is the data acquisition period By ensuring that it is automatically aligned with the first part (begginig) of deal with. In the illustrated embodiment, The first data packet following a system reset Alignment by Packet start flag (Start O f Packet flag) can be easily used with control logic.                               BRIEF DESCRIPTION OF THE FIGURES   In the drawing,   FIG. 1 shows a part of a video signal processor and an encoder including a device according to the invention. It is a block diagram of.   FIG. 2 is a timing diagram of signals related to the operation of the system shown in FIG.   FIG. 3 shows some details of the apparatus of FIG.   FIG. 4 shows another embodiment of the apparatus shown in FIG.   FIG. 5 is a timing diagram of signals related to the apparatus of FIG.   FIG. 6 depicts details of a portion of the apparatus of FIG.                               Detailed description of the drawings   In FIG. Variable length compression codeword (variable length com) conforming to MPEG2 standard pressed codewordes) from the video signal processing source 10 to the transmission processor / enco To the input processor 12 of the coder 20. The main functions of the transmission processor 20 are as follows. , Eventually make up a fixed length (188 byte) data packet, This codeword is Packing into fixed-length data words, each preceded by a header . Input processor 12 provides variable length codewords to data packer 14, Conte Provides roll signals and flags to controller 15 and header generator 16 . For example, The controller 15 stores word length data from the input processor 12. (accumulation) Confirm completion of fixed-length data word, Suitable wa Sends data address and word control signal to data packer 14 . The word address is Ensure proper concatenation of variable length codewords. Word control Roll signals can be marked and aligned as needed to account for short words. Provide a flag. The codeword source 10 includes a data packer 14 and a controller. Roller 15 can be incorporated. In such a case, Multiple packed data Inputs to the data / header combiner 18 Can be multiplexed directly to Program source, Service type, And other pay A suitable header representing information related to the payload data Provided by header generator 16.   PACKED DATA from packer 14 is combined with data / header Vessel 18, That is, it is transported to the packet generator, This data / header combiner 1 8 is a data write (write) and enable (enable) signal from the packer 14 Also received Valid data to input FIFO buffer of packet generator 18 (valid data) can be written. It seems that packed data is available if there is, The packed data words are sent to packet generator 18. You. Similarly, If a transmission header is available, From header generator 16 It is sent to the input FIFO buffer of the packet generator 18. Header di The information used by the generator 16 to form the header is: Input processor 12 and the controller 15. The header generator 16 also A write enable output signal is provided to the packet generator 18 to provide a header Indicate that you are ready, Enables the header to be written to the input FIFO. Each header is The header contains information associated with the data in the accompanying packet. This header information Synchronization at the receiver, Program identification, Scran Bull release control, Demultiplexing, Path routing, Peiro Assist the code type, In this embodiment, the first header period includes an MPEG sync byte. including. The header generator 16 At the start of a packet in this system The packet starts in parallel with the generated sync byte (SOP: Start Of Packe t) It turns out that a flag is also generated. The packet generator 18 has a suitable head. Prepended to each packed data payload, The resulting transmission packet And the parallel SOP flag are described in the transport stream interface unit described later. To the client 25.   The transmission packet and the SOP flag from the transmission processor 20 are interface· The signal is transferred to the modulator 40 by the unit 25 and the logic circuit 30. The modulator 40 outputs A processing and modulation unit 48, this is, For example, satellite, cable, Or earth Before configuring for transmission to an output channel, such as the upper broadcast channel, Performs various signal processing functions on the In this regard, the output unit 48 FEC , Interleaving, Coding, Spectral shaping, and, For example, quadrature amplitude modulation ( Includes modulation circuits including QAM) or Vestigial Sideband Modulation (VSB) circuits (network) be able to. The data packets processed in unit 48 are: With the logic circuit 30 An element 42 associated with the modulator 40 cooperating with the interface 25, 44, Use 46 Is obtained. These elements work together, First data of acquisition window period Entries are guaranteed to be MPEG2 sync bytes that indicate the start of a packet I do. Since this modulator is a control factor, The start of the packet is The beginning of this signal Acquisition signal (inside the modulator) that coincides with the occurrence of the byte period gnal). Especially, The modulator 40 transmits the packet for processing. When requesting / extracting Disruptive conditions such as any system reset ndition) These elements work together Each data path MPEG sync byte at start of packet automatically starts data acquisition period Ensure alignment. As discussed below, Such an alignment is Confusion such as stem reset, Or clock slip or phase jump Quickly achieved after the instability of In this embodiment, the packet matching the sync byte is This can be easily done by using the start flag (SOP).   The following description of the operation of the system of FIG. See the signal timing diagram in FIG. Perform in light of this. The window signal generator 42 inside the modulator 40 Enable (Enable) period, Includes a shorter duration Disable period Generate modulator window (Mod Window) signal. The enable period is Strange Displays the time interval when the controller attempts to retrieve a data packet for processing. I forgot. The disable period is The modulator processes the packets it gets Uni FEC, Interleaving, Represents the time interval when providing encoding etc. The length of each disable period is Modulator 40 processes any packet Is a function of the time required for Although the processing time is typically a fixed length, , The modulator contains transmitter specific information, For example, equalization train (equalization trainning) May be sent, Transmission of packetized data can be invalidated. But, The synchronization system described here The disable period between packets is It works even in special cases of arbitrary duration. In this embodiment, During the sable period, The following theory of the timing relationship between the simplification and the illustrated signal To facilitate clear understanding of the light, It is shown as having a fixed length. You.   In relation to the modulator window signal (Mod Window), generator 42 is A start (Sta) that includes a series of positive pulses each one clock period long rt) and stop timing signals are also generated. Before the start pulse Is coincident with the beginning of the enable period, The leading edge of the stop pulse is enabled. Coincides with the end of the bull period. Modulator window signal to unit 44 Therefore, an acquisition signal (Acquisition) is generated after being delayed by one clock cycle, This is the figure 2 is shown below. This signal is Data packets during the acquisition interval (see below) To obtain the data B) Processing the acquired data packet To control the operation of the data acquisition unit 46 which conveys it to the modulator 48. The acquisition signal is , Except that the modulator window signal is delayed by one clock. And the same as the modulator window signal. Modulator window signal issue, Acquisition signal, Stop and start signals are free-running. And Not subject to start / stop operations.   In FIG. The signal labeled Tran Data (In) To interface 25 Of the interface 25 according to the applied input transmission packet data stream. It corresponds to the packetized data stream signal that appears at the output. Fig. 1 The operation of the stem is Any confusion occurs, System reset to the transmission processor 20 This is first described in the context of a situation that causes In such a case As a table, The output buffer associated with the packet generator 18 " This empties this buffer. This state is shown in Tran Data ( In) shown in the first 20 bytes of the signal, This is the symbol "? "Is included. This In the example of the unit 46, 48 is a valid data packet to be obtained for processing Is A 16-byte period (123 bytes) including the sync byte period at the beginning of the packet 456789ABCDEF). The sync byte period for each packet is , Highlighted with diagonal lines. The SOP (In) flag generated by the transmission processor is FIG. Is shown just above the Tran Data (In) signal, Match the sync byte period. Transport Enable; Tran Enable) signal from generator 42 In response to the leading edge of each start pulse of Produced by lip flop 38, As a result, the flip-flop 38 is set. To The transmission enable signal starts one clock after the start pulse. The transmission enable signal is usually time aligned with the acquisition signal (Acquisition), Similarly, a packet acquisition period is defined.   In the following sequence of events, Time intervals T1 to T2 and T2 to T3 Nominally enable and disable the free-run modulator window signal Table period. Under normal conditions, Transmission Enable (Tran Enable) The period begins after the start pulse at time T4, Modulator 40 is Indicates an attempt to obtain a ket. But at this time, Preceding Due to any confusion reset condition (assumed) that emptied the FIFO buffer Pa No packet data is available. The lack of packet data indicates that the data valid signal (Dat a Valid) signal. The starting point of this is related to FIG. It will be explained in a series. Since the data valid signal is at a low level, the modulator sets the acquisition interval T4 to T 5, the data held in the register 34 (or the register 55 in FIG. 4) is continuously And get At all times before this interval, the acquisition window signal (acquisition w indow signal) is high, And the data valid signal is low. This is a normal This is a boot-up phenomenon.   A positive going data valid signal appears at time T5, Tran Data (In) Sync -Indicates that the first valid data has appeared in the form of bytes (hatched area). Positive The data valid signal is Transmission enable indicating that packet data is being retrieved Bull (Tran Enable) signal, Data in the preceding buffer (in the form of sync bytes) Depending on the presence of the "Buffer Fullness" flag, Generated by the logic circuit (FIG. 3). At time T5, Data stream With the appearance of the SOP (In) flag at the same time as the reappearance of the valid sync byte in This next data Real time alignment of the beginning of the data packet with the acquisition period of the acquisition signal. (Realignment; (Reordering) process starts.   Referring to the circuit 30 of FIG. Packet alignment processing is interface Starting with the SOP flag from 25, Register 32 ("D" type flip flow 1) is delayed by one clock as SOP A to the “Q” output of the register 32 And appear. The SOP A flag is supplied to the flip-flop 3 via the logical OR gate 36. Reset 8 A positive transmission enable signal is set to a logic low level at time T6. Return to This reset operation occurs at the output of interface 25 (as can be seen from FIG. 3). Disable the force register, This stops the passage of data, Modulator The window signal is not affected. Stopping the data flow is inconsistent with the data valid signal Will be reflected. The data valid signal (Data Valid) indicates the transmission enable signal level. Because it is a function, It is truncated and returns to a logic low level at the same time. SOP signal Resets the flip-flop 38 by The next stop pulse has no effect Become. The output register 312 of FIG. 3 and the register 32 of FIG. 34 is Consecutive Holds data words. Therefore, these registers Pipeline structure And operates in a shift register system. To stop the shift process, All of The register stages must be disabled at the same time.   Register 32 and a cascaded similar unit 34 Modulator 40 The clock is clocked by a signal Tran Clk obtained by inverting the clock Mod Clk applied to the clock. Register 32, 34 data inputs Enabled by positive data valid signal. Correct Data valid signal is prohibited at time T6 by the reset operation of the SOPA flag. Because it is stopped Registers 32 and 34 cannot respond to input data. As a result, Each register output is the last data byte read Is repeatedly held. In the case of the register 32, The repeated output data is Fig. 2 The first following the sync byte period as shown as the Data A signal From the data stream byte period ("1"). Register 34 in the case of, The repeated output data is The output signal of data B (Data B) shown in FIG. As shown, the data is in the sync byte period.   The next start pulse "sets" flip-flop 38, This is positive The transmission enable (Tran Enable) component starts at time T7, Start Pa Align with the falling edge of Luz. At this time, flip-flop 38 is set When normal operation is resumed, Sync byte of data B (this is Regis The module "stuck" at the output of the data 34) starts at time T7. This is the first byte that appears during the enable period of the data window signal. Positive day Data valid signal starts at the same time, Data A and data B signals of FIG. Registers 32 and 34 can carry data from input to output as shown To do. The positive transmission enable and data valid signal components are (for example, T7 to T8 and T9 to T 10), Each acquisition period is a sync byte followed by 15 data bytes Correctly contains a complete data packet containing The subsequent SOP A pulse Cis If system instability does not occur, stop pulses and all are aligned as shown. Columns (matching in time) After system instability, data acquisition is as described Automatically realigned by independent reset operation of SOP flag You.   From the above, The system described is Any system fault (fault) or reset / Advantage of correct packet alignment within packet acquisition period immediately after restart It can be seen that this is achieved. In particular, the packet sync byte Packet data Appears correctly at the beginning of the packet capture period with minimal offset confusion in the stream I do. Several examples can be noted in this regard. The first case is Fixed length 188 This is the case when packets longer than bytes are erroneously placed in the data stream. The stop signal resets the flip-flop 38 of FIG. For example, Since sync bytes remain in FIFO 310 (FIG. 3), The next packet is Create an abnormal packet that does not start with a link byte. Start signal is If you restart the data flow, Flip-flop 3 due to generation of sync byte As a result of resetting 8, Data flow stops again. This is the second anomaly Generates a packet, From this point on, synchronization is achieved. The second case is De If less than 188 bytes of packets are misplaced in the data stream It is. Start of Packet; SOP) flag is the flip-flop of FIG. Reset rop 38, An abnormal packet is created. Subsequent stop pal The emergence of This is redundant because the flip-flop 38 has already been reset. The third case is This is the case where the stop signal from the modulator arrives early. Two Continuous abnormal packets It is created as in the first case. Also, Stop letter The case where the signal occurs with a delay is the same as the second case. In all cases , Synchronization is restored automatically. Especially in noisy environments, Strike to OR gate 36 Disconnect the signal line (this eliminates the need for gate 36) SOP It is advantageous to reset flip-flop 38 using only the lag.   Under normal conditions, The system is reset, Data to modulator 40 The passage is In response to the occurrence of either a positive SOP (A) flag or a positive stop pulse Banned. They are, Usually they are in time. The passage of data Taking It remains inhibited during the subsequent modulator processing between acquisition periods. You In response to the next start pulse to "set" knit 38, register 32 and When 34 becomes valid again, Data passage is resumed and registers 32 and 34 Can now carry data, The first in the acquisition window under normal circumstances A correctly positioned sync byte is provided as a data word.   FIG. 2 shows the interface unit 25 of FIG. 1 in more detail. Biography The transmission packet from the transmission processor 20 (transpot packets) and the SOP flag Provided at each input of the FO buffer 310. The buffer 310 This transmission Write clock (Write clk) and Write enable (Write Enable) signal is also received. The modulation clock (Mod clock) from the circuit 30 (FIG. 1) is output. Applied to the clock input of the force register 312, The transmission enable (T ran Enable) signal is applied to the Enable input of the output register 312 . The Tran Data signal (transmission packet) and the SOP flag from the FIFO 310 are Les It is transferred to the circuit 30 of FIG. Provided by FIFO310 The fullness flag is FIFO 310 data full state, example For example, one to several bytes or several packets remaining in the FIFO 310 Can be programmed. Whether the charge flag output from the register 312 and the circuit 30 These transmission enable signals are provided to a logical AND gate 318, Charge flag and biography A data valid signal is generated when both of the transmission enable signals are present.   The transmission clock (Tran Clock) provided to the circuit 30 in reverse is: Inverter 314 Taken out after inversion by Indicates a delay less than one clock period. Modulation clock The signal and the transmission enable signal are correctly aligned with each other when generated from the modulator. If Any delay between the modulator and the transmission processor (eg cable or data Vice delay), Both signals go through the same delay path Because This as it appears in the FIFO 310 and output register 312 of FIG. The arrangement will be maintained. The transmission pallet signal (Tran Data) Transmission output smell Have a defined relationship to the modulation clock. But, Transmission pallet signal Reaches the modulator input, The relationship with the generated modulated clock is related to the cable delay Depends on This is because the transmitted pallet signal has traversed the delay path. This question The title is Transmits the transmission clock (Tran Clock), which is a copy of the modulation clock (Mod Clock) The problem is solved by sending it together with the pallet signal (Tran Data) to guarantee the alignment. You. Preferably, Modulated clock is well aligned with transmitted pallet signal (rise An inverted version of the modulation clock is transmitted because of the nominal center of the leading edge. Modulator and transmission If the delay between the processors is well defined, Transmission clock can be removed , A delay trimmed version of the modulation clock can be used for the modulator.   The occurrence of a positive data valid signal (Data Valid) Data exists in FIFO 310 (Valid or inactive as indicated by the fill flag) If the modulator has data ( (Indicated by a transmission enable signal). FIFO3 If 10 contains invalid data, Such data is collected during the acquisition period To the modulator. But, In reality, FIFO 310 and transmission processor In the event of system instability such that both output buffers require a transmission reset Empty, Since the first data byte is typically a valid sync byte, , This rarely happens.   The apparatus of FIG. 6 is a modification of the apparatus of FIG. FIG. Enable Regis (ENA. resister) 610 is the same as FIG. 3 except that it is added as shown. It is. The register 610 is used to determine the length between the circuit 30 and the transmission interface 25. Provides improved noise immunity, such as those required for You. Using the register 610 introduces another one clock delay into the system However, this delay is compensated for by modifying circuit 30 as shown in FIG. You. 4 is the same as the circuit 30 of FIG. 1 except that a register 55 is added. Is the same as Since the register 55 introduces a further delay of one clock, the element That the delay caused by 44 has increased to an amount corresponding to the delay of two clocks Become. The timing diagram for the system of FIG. 4 is shown in FIG. In FIG. The system receives data packets from the Data C output of register 55. During the acquisition period, for example, the points captured for processing between times T7 and T8 in FIG. Except for this, it is the same as the system of FIG. The disclosed device can be further modified to Compensate for additional delays introduced by elements corresponding to Additional registers can be included to compensate.   Another example of the disclosed system discloses an End of Packet flag. It may be used instead of the Start of Packet flag as described above. This In such a case, the detection point moves to the output of the register 34 in FIG. 1 and FIG. . In addition, the sync byte structure (for example, 7 Hex) is created from within the data stream itself. You may search. This can be difficult because the value of this sync byte is not unique. However, the nature of system operation start / stop (enable / disable) It is achievable if obtained. Using a time-variable disable period reduces complexity Increase (for example, a programmable May be needed).

────────────────────────────────────────────────── ─── Continuation of front page    (81) Designated countries EP (AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, M C, NL, PT, SE), OA (BF, BJ, CF, CG , CI, CM, GA, GN, ML, MR, NE, SN, TD, TG), AT, AU, BB, BG, BR, BY, CA, CH, CN, CZ, DE, DK, ES, FI, G B, HU, JP, KP, KR, KZ, LK, LU, LV , MG, MN, MW, NL, NO, NZ, PL, PT, RO, RU, SD, SE, SK, UA, US, UZ, V N (72) Inventor Banting, Richard, Michael             United States New Zealand             08609 Hamilton Square fuse               Drive 1015 Apartment Nan             Bar 10 (72) Inventors Ryans, Paul, Wallace             United States New Zealand             08533 New Egypt Kenyon             Live 9

Claims (1)

[Claims] 1. For processing packetized digital data streams containing video information In the system of   A transmission processor for generating a data packet in response to input data (10) Means (20, 25);   Means for processing the data packet generated by the transmission processor means. Obtaining the data packet during an acquisition period, and Processing means (40) for processing during a processing period during the acquisition period;   Means (25, 30, 32, 34) for carrying a data packet to said processing means When,   Connected to the transmission processor means and the means for processing the data packet. Data path according to the state of the data stream from the transmission processor. The reference data component (sink byte) of the socket and the normal operation of the system. Facilitates automatic alignment with the beginning of each acquisition period When an abnormal condition that disrupts the normal data stream from the Synchronizing means (32, 36, 38, 312, 3) for facilitating the automatic alignment 14,318) and   An apparatus comprising: 2. Generates a signal (full flag) indicating the memory occupation state of the transmission processor means Further comprising means for:   2. The method according to claim 1, wherein the synchronization means is responsive to the occupancy state signal. On-board equipment. 3. The transmission processor means may be reset according to the abnormal state 3. The device according to claim 2, wherein: 4. Means for providing a signal (SOP) indicative of a packet boundary;   Means for adjusting the operation of the synchronization means as a function of the signal representing the boundary (36) , 38, 318) and   The apparatus of claim 1, further comprising: 5. The data packet includes MPEG encoded information;   The reference data component is a sync component prepended to a data packet. The device according to claim 1, characterized in that: 6. The acquisition period exhibits a substantially constant duration;   The method of claim 1, wherein the processing period may indicate a variable duration. On-board equipment. 7. The processing means includes means for performing an error correction process and a modulation function. The device according to claim 1, characterized in that: 8. A flag (SOP) that matches the reference data component at the beginning of the data packet 2. The apparatus according to claim 1, further comprising means (16) for generating Place. 9. The synchronization means,   Resetting the synchronization means according to the data packet and the flag (SOP). Control means for prohibiting the passage of data to the processing means during the processing period. The device according to claim 8, characterized in that it comprises (32, 34, 36, 38). 10. Including an enable period associated with the acquisition period, and associated with the processing period. Means for providing a periodic window signal interleaving a disable period (42) and   The control means controls the start and the beginning of the enable period of the window signal. At the end of the enable period, the timing signals (start, stop, Means (42) for providing   Having a periodic acquisition period associated with the enable period of the window signal; Providing an acquisition signal corresponding to the acquisition period of the processing means, Means (44) for controlling the acquisition of the data to be processed;   The control means includes a data enable period (Tran Enable). C) The enable and disable periods of the signal each include a period normally associated therewith. Interleaved and related to the passage and prohibition of data, respectively, according to the flag. Means (38) for providing an enable signal indicating the first and second states;   The apparatus of claim 9, further comprising: 11. The reference data component is a sink component,   The transmission means comprises one of each of the sink components to be added to the data packet Generates an alignment flag that matches   The transporting means sends a signal to the processor in accordance with the alignment flag. The apparatus of claim 1, wherein preventing the passage of data is prohibited. 12. The synchronization means controls the processor in accordance with the alignment flag. Preventing data from passing to the stage (via 36, 38, ENA inputs) is prohibited Apparatus according to claim 11, comprising storage means (32, 34). 13. A first clock is provided to the processing means and the transmission means (25, 310, 312). Means for providing a clock signal (Mod clock);   The replica (Tran Clock) of the first clock signal is transmitted to the data (T (ran Data) together with the means for transmitting to the conveyance means.   The device according to claim 1, comprising: 14． A first clock is provided to the processing means and the transmission means (25, 310, 312). Means for providing a clock signal (Mod clock);   A second clock signal from the first clock signal associated with the transmission means; Means for obtaining (Tran Clock) (314);   Means for providing said second clock signal to a clock input of said transport means;   The device according to claim 1, comprising: 15. The second clock signal is obtained by inverting the first clock signal. 15. The device according to claim 14, wherein 16. For processing packetized digital data streams containing video information In the system for   A transmission processor for generating a data packet in response to input data (10) Means (20, 25) for resetting the transmission processor by an unexpected reset. A transmission protocol that can disrupt the data stream of data packets from the stage. Sessa means,   Means for processing the data packet generated by the transmission processor means. Obtaining the data packet during an acquisition period, and Processing means (40) for processing during a processing period during the acquisition period;   Means (25, 30) for transporting data packets to said processing means;   Connected to the transmission processor means and the means for processing the data packet. Appears at the beginning of the acquisition period after resetting the transmission processor means Automatic alignment of reference data components (sync bytes) in data packets Synchronization means (32, 36, 38, 312, 314, 318)   An apparatus comprising: