JPH06225273A - Error correction device - Google Patents

Abstract

PURPOSE:To attain an error correction processing by accurately detecting a frame position by receiving digital data including an error correction code at a specified time position in a frame. CONSTITUTION:A frame synchronizing signal is inserted to the horizontal blanking period of a digital video signal. Then, a frame synchronization detecting circuit 3 detects the signal. A frame synchronization protecting circuit 10 respectively detects a frame synchronizing state and a frame step-out state by the detection result. At the time of generating the frame synchronization signal outputted by the frame synchronization detecting circuit 3, an error correction timing generation circuit 4 gives an error correction timing signal to an error correction circuit 2. When the frame synchronization protecting circuit 10 detects the synchronizing state, the error correction circuit 2 corrects the erroneous code of an input signal. Thereby, the error correction processing can accurately be executed at a normal frame position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device for preventing erroneous detection of a frame sync signal included in a digital video signal.

[0002]

2. Description of the Related Art In recent years, in transmission and recording of video signals, digital type devices with little deterioration in image quality have begun to prevail in place of conventional analog type devices. In the horizontal blanking period of the digital video signal of each horizontal scanning line, a frame synchronization signal indicating a block or packet delimiter of the signal is inserted. Since the frame synchronization signal is an important signal, an error correction code is used so that a code error can be corrected.

The BTA (Broadcasting Technology Development Council) is the HDT
Among the V devices, the standard of the interface between the video devices used for studio program production and having digital video input or output was set. The BTA standard S-002 is called a 1125/60 system HDTV video signal encoding and bit parallel interface standard.
(Hereafter referred to as BTAS-002 standard)

In the BTAS-002 standard, an error correction code is used in the frame sync signal portion of the video signal.
Then, in order to clarify the timing relationship between the video signal and the analog synchronization waveform, the video timing reference code is inserted in the horizontal blanking period. This video timing reference code is SAV (S
tart of Active Video) and EAV (End of Active Video) at the end of each video data block. In each video equipment, SA is selected from the transmitted digital signals.
V and EAV are detected, and the frame synchronization timing of the video signal is detected. One frame here corresponds to one horizontal scanning line of an analog HDTV video signal.

A timing reference code of the BTAS-002 standard is shown in FIG. Each timing reference code consists of 4 words of 3FF, 000000 and XYZ in hexadecimal notation. The first three words (word numbers 1 to 3) are fixed value prefix information. The last one word (word number 4) is used to identify the field, the field blanking period,
And information indicating the identification of SAV and EAV, respectively. The states of F, V, and H of word number 4 are specifically shown in FIG. In this figure, F, V, and H are protection bits P0 and P.
It has a fixed relationship with 1, P2, and P3. When receiving these signals, it is possible to correct a 1-bit error by this bit string and detect a 2-bit error. No error correction code is added to the video data.

Next, a conventional error correction device used for transmitting an HDTV digital video signal will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration example of a conventional error correction device. In this figure, the data input terminal 1 is BTA
This is a terminal to which an S-002 standard video signal is input. The error correction circuit 2 inputs the digital video signal from the data input terminal 1, and if there is a code error in the signal of the video timing reference code shown in FIG. 7, the protection bits P0 to P3.
Is a circuit for correcting an error in a code by using. The frame synchronization detection circuit 3 is a circuit that detects a frame synchronization signal from the output signal of the error correction circuit 2.

The error correction timing generation circuit 4 receives the error correction timing signal during the reception period of the next video timing reference code delayed by one frame (one line of the video signal) from the frame synchronization detection signal output from the frame synchronization detection circuit 3. Is output to the error correction circuit 2. The data output terminal 5 is a terminal for outputting a digital video signal including an error-corrected frame synchronization signal to a video demodulation circuit (not shown).

The operation of the error correction device thus configured will be described with reference to FIGS. 10 and 11. 10 and 11 are explanatory diagrams showing output signals of each block of the error correction device. BT as shown in the timing (a) of FIG.
A video signal A of AS-002 standard is input to the error correction circuit 2 via the data input terminal 1. In the first video timing reference code, there is no code error in word numbers 1 to 3, and it is assumed that a code error occurs in the part indicated by ● in word number 4. This signal has a 1-bit error, and the code error is easily corrected by the error correction circuit 2.

Next, the frame synchronization detection circuit 3 detects the 4-word signal including these SAV and EAV from FIG. 10 (b).
The frame synchronization detection signal B shown in is generated and the signal is given to the error correction timing generation circuit 4. The error correction timing generation circuit 4 generates the error correction timing signal C shown in FIG. 10C during the output period of the timing reference code one frame after, as shown in the timing (b) of FIG. Output to 2. The error correction circuit 2 corrects the error of the digital video signal which is currently input based on the correction timing signal C, and the corrected BTAS-00 is corrected as shown in the timing period (b) of FIG.
The video signal D of 2 standards is output. The frame synchronization detection circuit 3 also outputs a frame synchronization detection signal B used in the next frame period.

As described above, since the frame sync detection signal B is correctly detected at the timing (a), the error correction timing signal C is correctly output at the timing (b). Therefore, the 1-bit code error generated in the timing (b) video signal A is correctly corrected and becomes the timing (b) video signal D.

[0011]

Data input terminal 1
It is assumed that the signal of the BTAS-002 standard input to the input terminal has a plurality of code errors in a part and enters a state as shown in FIG. That is, in the digital video signal E, a code error occurs in the portions indicated by black circles in the word numbers 1 and 3 of the timing reference code, and as shown in the timing (d) of FIG. Bit garbled, and the same code as the timing reference code was generated.

As shown in the timing (c) of FIG. 11, a transmission error occurs in the timing reference code, the original frame synchronization signal is not detected, and as shown in the timing (d) of FIG. Consider a case where a false frame synchronization detection signal F which is erroneously formed in a part of the video data is generated. At this time, the error correction timing generation circuit 4 delays by one frame and generates the error correction timing signal G in the period of the timing (e) shown in (c). For this reason, error correction is performed at a timing that does not have to occur. The error correction first detects an error and then inverts the value of the bit in which the error is detected. If the error correction is performed at the wrong timing, the error is mistakenly detected and the wrong bit inversion occurs. This causes a problem that a new code error occurs.

When the error correction timing generation circuit 4 is composed of a frame period counter and its decoding circuit and always outputs the error correction timing signal once or several times for each frame, a big problem occurs. Cause In this case, even if the error correction device does not detect the synchronization pattern by mistake, if the synchronization pattern cannot be detected, an error correction signal may be output at an incorrect sampling point, increasing the number of code errors. Further, in this case, there is a problem that the correct frame position is not known and the error correction timing signal is also incorrect.

The present invention has been made in view of the above conventional problems, and corrects a code error that has occurred, and prevents the occurrence of a new code error due to erroneous detection of a code. It is an object of the present invention to realize a digital video signal error correction device capable of performing the above.

[0015]

The present invention receives a digital signal including an error correction code in a timing reference code inserted at a specific time position of a frame within a frame indicating one horizontal scanning period of the digital video signal. An error correction device for correcting a code error, which detects a frame synchronization pattern included in a timing reference code and generates a frame synchronization detection signal, and a frame synchronization detection signal from the frame synchronization detection circuit. At the time of output, it is identified whether the cycle and phase of the frame sync signal in the frame sync pattern are stable for a certain period of time, and if the cycle and phase of the signal are stable, it is determined to be the frame sync state
If it is unstable, it is determined that the frame is out of sync, and the frame sync status signal, latest match detection result signal, and load enable signal are output from the frame sync protection circuit, the output result of the frame sync detection circuit, and the frame sync protection circuit. The error correction timing generation circuit that generates the error correction timing signal and the internal synchronization position signal respectively by the output load enable signal and the frame synchronization protection circuit detect the frame synchronization state, and the latest match detection result signal is the same. At this time, an error correction circuit that corrects an error of the digital video signal when the signal of the error correction timing generation circuit is output is provided.

[0016]

According to the invention of the present application having such characteristics,
The frame synchronization detection circuit detects a frame synchronization pattern included in the timing reference code in a frame indicating one horizontal scanning period of the digital video signal and generates a frame synchronization detection signal. The frame synchronization protection circuit, when outputting the frame synchronization detection signal from the frame synchronization detection circuit, identifies whether or not the cycle and phase of the frame synchronization signal are stable for a certain period of time, and if the cycle and phase of the signal are stable, the frame synchronization protection circuit It is determined to be in the synchronized state, and if it is unstable, it is determined to be out of frame synchronization. The error correction timing generation circuit generates an error correction timing signal based on the output result of the frame synchronization detection circuit. Next, the error correction circuit corrects the error of the digital video signal when the signal is output from the error correction timing generation circuit when the frame synchronization protection circuit determines that it is in the frame synchronization state and the latest match detection result signals match. This allows error correction to be performed at an accurate position in the frame. This makes it possible to accurately correct the error code that has occurred and to prevent the occurrence of a new code error due to incorrect error correction.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An error correction device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the error correction device of this embodiment. In this figure,
Since the data input terminal 1, the error correction circuit 2, the frame synchronization detection circuit 3, the error correction timing generation circuit 4, and the data output terminal 5 are respectively provided, it is the same as the conventional example, and the description thereof is omitted.

The frame synchronization protection circuit 10 is a circuit for discriminating whether or not the frame synchronization detection signal b supplied from the frame synchronization detection circuit 3 is a normal signal based on its cycle and generation timing. If there is, an H level signal is output to the error correction circuit 2. The signals output from the frame synchronization protection circuit 10 to the error correction circuit 2 are the latest match detection result signal c that outputs H when the latest match detection results match, and the synchronization state that outputs H in the frame synchronization state. There is a signal d.

Further, the error correction timing generation circuit 4 is in a frame out-of-sync state and when the latest match detection result is a mismatch, the load enable signal g for controlling the loading of the frame counter in the error correction timing generation circuit 4 is set.
Is set to H, the frame counter is loaded with the frame synchronization signal, and the frame counter is made to match the phase of the latest frame synchronization detection signal.

FIG. 2 is a block diagram showing a configuration example of the error correction timing generation circuit 4 and the frame synchronization protection circuit 10. In the figure, the broken line portion is the error correction timing generation circuit 4, and the other portion is the frame synchronization protection circuit 10.
Is. The input terminal 21 is the frame sync detection circuit 3 of FIG.
This is an input terminal for the frame synchronization detection signal output by. This signal is given to the input terminal D of the AND circuit (AND) 22 and the D-type flip-flop (FF) 23.

The frame counter 24 is a circuit which inputs a regular frame synchronization detection signal for a certain period of time, detects the cycle and phase of this signal, and continuously generates an internal synchronization position signal in the same phase as the frame synchronization detection signal. . Further, the frame counter 24 generates an error correction timing signal at a timing at which the error correction circuit 2 should correct an error in one frame. The phase of the error correction timing signal e matches the phase of the output pulse of the frame counter 24, and the output terminal 3
4 and is supplied to the error correction circuit 2.

The Q output terminal of the FF 23 is connected to the D input terminal of the FF 25. Similarly, the Q output terminal and the D input terminal of the FF 25, FF 26, and FF 27 are connected in series.
Each of the FFs 23 and 25 to 27 is a D-type flip-flop and constitutes a four-stage shift register. The output of the frame counter 24 is given to the clock input terminals C of the FFs 23 and 25 to 27. The output of the frame counter 24 is the internal synchronization position signal h shown in FIG. The Q output of the FF 23 of FIG. 2 is output from the output terminal 33 as the latest match detection result signal c.

The AND circuit 28 is a circuit for inputting the Q outputs of the FFs 23, 25 and 26, respectively, and taking the logical product of these. The AND circuit 29 is a circuit that inputs the Q-bar outputs of the FFs 23, 25, 26 and 27 and calculates the logical product of them. The outputs of the AND circuits 28 and 29 are given to the set input terminal S and the reset input terminal R of the FF 30, respectively. FF
Reference numeral 30 denotes an RS flip-flop, whose Q-bar output is input to the AND circuit 31. AND circuit 31 is FF
This is a circuit for inputting the Q-bar outputs of 23 and 30 and taking the logical product of them. The output of the AND circuit 31 is the AND circuit 22.
Given to. The output of the AND circuit 31 is the load enable signal g in FIG. On the other hand, the Q output of the FF 30 is output from the output terminal 32 as the synchronization state signal d.

The operation of the error correction device including the frame synchronization protection circuit 10 and the error correction timing generation circuit 4 thus constructed will be described with reference to FIGS. 3 and 4 are explanatory diagrams showing the output signals of the respective blocks of the error correction device in the present embodiment, and (a) to (e) show the same signal. As shown in FIG. 3A, the BTAS-002 standard digital video signal a is applied to the data input terminal 1.
Suppose that is input with an accurate cycle and phase over several frames. At the timing (b) of FIG. 3, the frame synchronization detection signal b shown in (b) is output at the same cycle and phase as the timing (a), and the latest match detection result signal c shown in (c) changes to H level. . After that, the frame synchronization detection signal is output at the same cycle and phase over the timings (c) and (d) in FIG. 4, whereby the synchronization state signal d changes to the H level as shown in (d). Then, the error correction circuit 2 of FIG. 1 performs error correction on the input signal when the latest match detection result signal c and the synchronization state signal d are both at H level.

At the timing (e) in FIG. 4, since the digital video signal a is input in the same cycle and phase, the error code in the frame synchronization pattern is corrected, and the error-corrected code is shown in FIG. 4 (f). The error is corrected to show the video signal.

The operation of the frame synchronization protection circuit 10 and the error correction timing generation circuit 4 will be described here. 5 and 6 are signal waveform diagrams showing the operation of each part of the frame synchronization protection circuit 10 and the error correction timing generation circuit 4,
(A) to (j) show the same signal. FIG. 5 shows the operation when the frame sync detection signal and the internal sync position signal of the frame counter 24 are out of phase, and FIG. 6 is the operation when the phase of the frame sync detection signal and the internal sync position signal are in phase. It shows the operation.

The operation of the frame synchronization protection circuit 10 when the sync state shifts to the out-of-sync state will be described.
As shown in FIG. 5A, it is assumed that the frame synchronization detection signal is input at the position where the phase is delayed as shown by the solid line from the normal position shown by the broken line. In the section before the timing (T1), the frame counter 24 outputs the internal synchronization position signal in the same phase as the frame synchronization detection signal.
As shown in (a), the phase of the frame synchronization detection signal is delayed in the section of timing (T1). Therefore, FF23
When the clock is input, the frame synchronization detection signal at the D input end becomes L level, and the Q output of the FF 23 becomes L level as shown in FIG. In this way, the frame synchronization protection circuit 10 continues in the phase where the frame synchronization detection signal is delayed.
Is input to the Q output of the FFs 25 to 27, the Q output of FIG.
As shown in (f) to (T2), (T2), (T
At 3) and (T4), the L level changes.

At the timing (T1) in FIG. 5 (g),
An L level signal is input to the set input terminal of the FF 30 via the AND circuit 28. Then, at the timing (T4) in FIG. 5H, the reset signal is input to the reset input terminal of the FF 30 via the AND circuit 29. Therefore, as shown in FIG. 5 (i), the Q output of the FF 30 becomes L level at the timing (T4), and the synchronization state signal d becomes L level from the output terminal 32 and is output in the out of synchronization state.

On the other hand, at timing (T4), the Q-bar outputs of FF23 and FF30 both become H level, and the H-level load enable signal g is input to the AND circuit 22 via the AND circuit 31. Therefore, when the frame synchronization detection signal is input through the input terminal 21, the AND circuit 22
Gives a pulse as shown in FIG. 5 (j) to the frame counter 24 as a load signal. When this load signal is given, the frame counter 24 generates an internal synchronization position signal synchronized with the phase of the input frame synchronization detection signal as shown in FIG. 5 (b). As described above, the frame synchronization protection circuit 10 has a protection function for preventing the generation of the internal synchronization position signal and the error correction timing signal at the frame cycle of the wrong timing due to the false frame synchronization detection signal generated by the transmission error or the like. Has achieved.

The timing (T5) in FIG. 6 is the first section in which the frame counter 24 shifts from the out-of-synchronization state to the synchronization state. In this case, the Q bar outputs of the FFs 23 and 30 are both at the H level in the first period, and the AND circuit 31 outputs the H level load enable signal to the AND circuit 22. Therefore, when the frame synchronization detection signal is input from the input terminal 21, the AND circuit 22 uses the pulse as shown in FIG.
Give to.

As shown in FIG. 6A, it is assumed that the phase of the frame sync detection signal input from the frame sync detection circuit 3 via the input terminal 21 and the phase of the internal sync position signal generated by the frame counter 24 match. This internal synchronization position signal is input to the FFs 23, 25, 26, 27 as a clock signal, and the frame synchronization detection signal is given to the D input terminal of the FF 23. Therefore, from the timing (T5) in FIG.
At (T8), the Q outputs of the FFs 23, 25, 26, 27 change to the states shown in FIGS. 6 (c) to 6 (f).

The output of the AND circuit 28 becomes H level at timing (T7) as shown in FIG. 6 (g). On the other hand, the output of the AND circuit 29 becomes L level at the timing (T5) when the Q bar output of the FF 23 changes as shown in FIG. 6 (h). Therefore, the Q output of FF30 is shown in FIG.
As shown in (i), when three pulses of the frame synchronization detection signal of the same phase are continuously input, the H level is set at that time (timing (T7)), and the synchronization state signal is output from the output terminal 32. In this way, the frame synchronization protection circuit 1
When the frame synchronization detection signal is detected several times in succession at the timing predicted by the frame counter 24, 0 is determined to be the synchronization state.

In FIG. 1, the error correction timing generation circuit 4 outputs the error correction timing signal e at the correct time and phase as shown in the timing (e) of FIG. 4 (e). On the other hand, if the frame synchronization detection signal is not input to the regular position of the frame period as in the state before the timing (b) in FIG. 3, the frame is detected as shown in the timing (a) in FIG. The synchronization state signal d output from the synchronization protection circuit 10 becomes L level. Therefore, the error correction circuit 2 does not perform the error correction of the code and outputs the input video signal as it is from the data output terminal 5.

At the timing (d) in FIG. 4, the synchronization status signal d output from the frame synchronization protection circuit 10 becomes H level. Therefore, at the next timing (e), the error correction circuit 2 corrects the error of the input signal at the generation time of the error correction timing signal e output from the error correction timing generation circuit 4.

By providing the frame synchronization protection circuit 10 in this way, an accurate frame position can be detected. Like the digital video signal a at the timing (e) in FIG.
When a 1-bit error occurs in the last byte of the timing reference code in the frame synchronization state, the error correction circuit 2 can perform correct error correction processing by the error correction timing signal d. Further, as shown in FIG. 3 (e), BTAS-
This eliminates a malfunction that causes a new error in the error correction timing signal e of the 002 standard.

In addition, when it is going to shift from the out-of-sync state to the out-of-sync state, it takes several frames to reach the completely out-of-sync state. The latest match detection result signal c is obtained when the frame synchronization detection signal is not input once at the timing position predicted by the frame counter 24 in FIG.
Immediately, it changes to the L level and the error correction operation is stopped.
As a result, error correction is performed at wrong timing during a period of a plurality of frames which are shifting from the synchronized state to the out-of-synchronized state, and a malfunction in which a code error propagates to other portions is prevented.

[0037]

As described above, according to the present invention, since the frame synchronization protection circuit is provided, when a digital video signal containing an error correction code is received at a certain fixed time position in the frame, The sync and out-of-sync states can be identified. Therefore, if the error correction is performed only in the synchronized state, it is possible to prevent the malfunction of correcting the error at the wrong timing, and it is possible to perform the highly reliable error correction using the frame synchronization detection signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an error correction device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a frame synchronization protection circuit used in the error correction device of the present embodiment.

FIG. 3 is an explanatory diagram (part 1) of a signal showing an operation of the error correction device according to the present embodiment.

FIG. 4 is an explanatory diagram (part 2) of a signal showing the operation of the error correction device of the present embodiment.

FIG. 5 is a signal waveform diagram (No. 1) showing the operation of the frame synchronization protection circuit of the present embodiment.

FIG. 6 is a signal waveform diagram (part 2) showing the operation of the frame synchronization protection circuit of the present embodiment.

FIG. 7 is an explanatory diagram showing a timing reference code of BTAS-002 standard.

FIG. 8 is an explanatory diagram showing a bit configuration of a word number 4 of a timing reference code.

FIG. 9 is a block diagram showing a configuration example of a conventional error correction device.

FIG. 10 is an explanatory diagram (part 1) of a signal showing the operation of the conventional error correction device.

FIG. 11 is an explanatory diagram (part 2) of a signal showing the operation of the conventional error correction device.

[Explanation of symbols]

 1 data input terminal 2 error correction circuit 3 frame synchronization detection circuit 4 error correction timing generation circuit 5 data output terminal 10 frame synchronization protection circuit 22, 28, 29, 31 AND circuit 24 frame counter 23, 25, 26, 27, 30 FF

Claims (3)

[Claims] 1. An error for correcting a code error by receiving a digital signal including an error correction code in a timing reference code inserted at a specific time position of a frame within a frame indicating one horizontal scanning period of the digital video signal. A correction device, which detects a frame synchronization pattern included in a timing reference code and generates a frame synchronization detection signal, and a frame synchronization pattern when the frame synchronization detection signal is output from the frame synchronization detection circuit. It is determined whether the cycle and phase of the frame synchronization signal inside are stable for a certain period of time.If the cycle and phase of the signal are stable, it is determined to be the frame synchronization state. If they are unstable, it is determined to be out of frame synchronization. However, the frame synchronization status signal, the latest match detection result signal, and the load enable signal are output respectively. A protection circuit; an error correction timing generation circuit for respectively generating an error correction timing signal and an internal synchronization position signal according to an output result of the frame synchronization detection circuit and a load enable signal output from the frame synchronization protection circuit; An error correction circuit that corrects an error of the digital video signal when the protection circuit detects the frame synchronization state and the latest match detection result signal is a match, and outputs the signal of the error correction timing generation circuit. Characteristic error correction device. 2. The digital video signal and the error correction timing generation circuit are BTA (Broadcasting Technology Development Association) S-0.
2. The error correction device according to claim 1, wherein the error correction device is 02 standard HDTV digital data. 3. The correction timing generation circuit generates an internal synchronization position signal at the same cycle as the frame synchronization signal given from the frame synchronization detection circuit, and the phase of the internal synchronization position signal is made the same as the frame synchronization signal by a load signal. The frame synchronization protection circuit receives the frame synchronization signal from the frame synchronization detection circuit and shifts the internal synchronization position signal output from the frame counter as a clock signal. This is set when the logical product of the shift register of the first stage and the output of the first stage to the (N-1) th stage of the shift register of the N stage is true, and the logical product of the inverted outputs of the shift registers of the first stage to the Nth stage is true. Is reset when
A flip-flop that outputs an out-of-sync or out-of-sync signal, and an AND circuit that, when the flip-flop outputs an out-of-sync signal, applies a frame sync detection signal of the frame sync detection circuit to the frame counter as a load signal, 3. The error correction device according to claim 1, further comprising: