KR200310455Y1 - Standby bus test circuit at exchange - Google Patents

Abstract

The present invention relates to a standby bus test circuit in an exchange, and in particular, a standby bus failure in a GS (Global Serial) bus that is implemented as a redundancy for communication between control processors does not add a separate processor load. It relates to a standby bus test circuit at an exchange to detect a fault.

The present invention performs the loopback test using IPC data under the control of the control unit for the GS-bus, which is implemented by the duplication of the active bus and the standby bus, and checks the normal operation of the active bus and the standby bus. By checking the data input after loopback in the logic section to verify the bus in real time, the status of the corresponding active bus and standby bus is checked to improve the reliability and stability of the system.

Description

Standby bus test circuit at exchange

The present invention relates to a standby bus test circuit in an exchange, in particular, in an exchange that detects standby bus failure in a GS (Global Serial) bus that is implemented as a redundant controller for communication between control processors without adding a separate processor load. It relates to a standby bus test circuit.

In general, the GS-bus, which is an Inter Processor Communication (IPC) transmission bus that is responsible for communication between processors in an exchange, is implemented in redundancy for the stability and reliability of IPC data communication. This is done.

In the conventional exchange, the standby bus test apparatus includes a GS bus, which is implemented by dualizing an active bus and a standby bus, as shown in FIG. 1, and processors 1 and 2 communicating through the GS bus. Is done.

Each of the processors 1 and 2 enables the IPC data communication under the control of the controllers 1a and 2a for controlling the IPC data communication and the control of the controllers 1a and 2a. GS-bus logic units 1b and 2b to be inspected, and A-BUS 1c and 2c and B-BUS 1d that interface IPC data between the GS-bus logic units 1b and 2b and the GS-bus. , 2d).

As described above, a standby bus test operation in a conventional exchange will be described. A-BUS 1c and 2c are used as active buses and B-BUS 1d and 2d are described as standby buses.

The standby bus state on the GS bus is checked in case an error occurs on the active bus on the GS bus. At this time, to check the standby bus in the GS-bus, A-BUS (1c, 2c), which is a corresponding active bus that transmits and receives current IPC data, is transferred to B-BUS (1d, 2d).

Therefore, the loopback test is performed using the IPC data between the processors 1 and 2 through the corresponding B-BUSs 1d and 2d to determine the standby bus state of the GS buses through the corresponding B-BUSs 1d and 2d. Could.

At this time, in order to identify the standby bus failure status of the GS-bus through the corresponding B-BUS (1d, 2d), the switch structure that requires real time is added to the periodic function of temporarily switching the bus to perform a loopback test. Inadequate

In this way, if the test is performed while the standby bus in the GS-bus through the corresponding B-BUS (1d, 2d) has failed, a loss of online messages may occur, which may affect the reliability and stability of the exchange. It may cause problems.

The present invention has been made in view of the above-described problems. For the GS-bus implemented by the duplication of the active bus and the standby bus, the loopback test using the IPC data is simultaneously performed under the control of the control unit. It checks whether the bus is operating normally. By comparing the input data after loopback in the GS-bus logic unit, it verifies in real time whether there is an abnormality of the bus. And to provide stability.

1 is a block diagram showing a standby bus test circuit in a conventional exchange;

2 is a block diagram illustrating a standby bus test circuit in an exchange according to an embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

10,20: processor 12: GS-bus logic section

11, 21: control unit 12-1, 22-1: first comparison circuit unit

12-2, 22-2: second comparison circuit section 12-3, 22-3: third comparison circuit section

12-4 and 22-4: fourth comparison circuit section

12-5, 22-5: Interrupt occurrence and status register

13, 23: A-BUS 14, 24: B-BUS

In order to achieve the above object, the standby bus test apparatus in the switch according to the embodiment of the present stage is configured to control the IPC data communication between the control unit and the GS-bus implemented by dualizing the active bus and the standby bus. An exchanger having an A-BUS and a B-BUS for interfacing, comprising: a first non-converting unit for comparing the IPC data applied through the A-BUS with the IPC data applied from the control unit and checking the same; A second comparison circuit unit comparing the IPC data applied through the A-BUS and the IPC data applied through the B-BUS and checking whether the same is the same; A third comparison circuit unit for comparing the IPC data applied through the B-BUS with the IPC data applied from the controller to check whether they are identical; A fourth comparison circuit unit which selects one of the IPC data applied through the A-BUS and the B-BUS, compares it with the IPC data applied through the control unit, and checks whether it is the same; The abnormality of the GS-bus through the A-SUS and B-BUS by storing the state of each test result in a status register and generating an interrupt signal according to whether each test result from the first comparison circuit part to the fourth comparison circuit part is present. And an interrupt generation and status register unit for reporting the presence or absence to the control unit.

Hereinafter, with reference to the accompanying drawings will be described in detail a practical example of the present invention.

In the switch according to the embodiment of the present invention, the standby bus test apparatus is illustrated in FIG. 2, and the processors 10 and 20 and the GS-bus are implemented in redundancy for the stability and reliability of communication. IPC data is transmitted / received through GS-bus with redundant communication.

The processor 10, 20 includes a control unit 11, 21, a GS-bus logic unit 12, 22, an A-BUS 13, 23, and a B-BUS 14, 24. .

The controllers 11 and 21 control the GS-bus logic units 12 and 22, the A-BUS 13 and 23, and the B-BUS 14 and 24 to enable IPC data communication.

The GS-bus logic units 12 and 22 enable IPC data communication under the control of the controllers 11 and 21, and check whether there is an abnormality of the GS-bus.

The A-BUS 13 and 23 and the B-BUS 14 and 24 interface IPC data between the GS-bus logic units 12 and 22 and the GS-bus.

Here, the GS-bus logic units 12 and 22 may include first comparison circuit units 12-1 and 22-1, second comparison circuit units 12-2 and 22-2, and third comparison circuit unit 12. -3, 22-3, fourth comparison circuit sections 12-4, 22-4, and interrupt generation and status register sections 12-5, 22-5.

The first comparison circuit unit 12-1 and 22-1 compares the IPC data applied through the A-BUS 13 and 23 with the IPC data applied from the control units 11 and 21 to check whether they are the same. do.

The second comparison circuit unit 12-2 and 22-2 compares the IPC data applied through the A-BUS 13 and 23 with the IPC data applied through the B-BUS 14 and 24. Examine whether or not.

The third comparison circuit unit 12-3 and 22-3 compares the IPC data applied through the B-BUSs 14 and 24 with the IPC data applied from the controllers 11 and 21 to check whether they are identical. do.

The fourth comparison circuit unit 12-4 and 22-4 is provided through the IP [data and the A-BUS 13 and 23 and the B-BUS 14 and 24 that are applied through the control units 11 and 21. One of the authorized IPC data is selected, compared and checked for equality.

The interrupt generation and status register sections 12-5 and 22-5 are the result of each test from the first non-communication section 12-1 and 22-1 to the fourth non-communication section 12-4 and 22-4. The state is stored in the status register according to whether the interrupt signal is generated and whether or not the GS-bus via the A-BUS 13 and 23 and the B-BUS 14 and 24 is abnormal to the controller 11 and 21. report.

Referring to the operation of the present invention configured as described above in detail with reference to Figure 2 as follows.

In the electronic switchboard, the GS-bus and the corresponding processors 10 and 20 that are in charge of the communication of the processors 10 and 20 are implemented in redundancy for communication stability and reliability, and transmit and receive IPC data through the active bus.

At this time, if the A-BUS (13, 23) in the processor (10, 20) is assumed to be an active bus and the B-BUS (14, 24) is a standby bus, for communication between the processors (10, 20) Communication is performed through the corresponding active buses A-BUS 13 and 23.

By the way, in case an error occurs in the data line of the A-BUS 13, 23 which is the corresponding active bus, the abnormality of the data line of the B-BUS 14, 24 which is the standby bus is verified.

First, under the control of the controllers 11 and 21 in the processors 10 and 20, IPC data is simultaneously transmitted by the A-BUS 13 and 33, which are the corresponding active buses, and the B-BUS 14 and 24, which is the corresponding standby bus. The loopback test is then performed via the GS-bus.

Accordingly, the GS-bus logic units 12 and 22 in the processors 10 and 20 compare the IPC data input after looping back through the GS-bus to verify whether the GS-bus is abnormal in real time. The first comparison circuits 12-1 and 22-1 in the corresponding GS-bus logic units 12 and 22 transmit the received data received by the control unit 11 and 21 and the transmissions transmitted from the active bus. Compare data and check for equality.

In the second comparison circuits 12-2 and 22-2 in the GS-bus logic units 12 and 22, the received data received under the control of the control units 11 and 21 and the transmission transmitted from the standby bus. Compare data and check for equality.

The third comparison circuits 12-3 and 22-3 in the GS-bus logic units 12 and 22 compare the active data with the transmission data transmitted from the standby bus and check whether they are identical.

In the fourth comparison circuits 12-4 and 22-4 in the GS-bus logic units 12 and 22, the received data, the corresponding active bus and the corresponding standby bus are received under the control of the controllers 11 and 21. Select one of the transmission data transmitted from the to compare and check the same.

Accordingly, after performing a comparison test of the data from the first comparison circuit unit 12-1 and 22-1 to the fourth non-intersection unit 12-4 and 22-4, at least one of the results of the comparison test is performed. In the wrong case, the interrupt signal is applied to the interrupt generation and status register sections 12-5 and 22-5 in the GS-bus logic sections 12 and 22.

Thus, the corresponding interrupt generation and status register sections 12-5 and 22-5 in the GS-bus logic sections 12 and 22 record the status of the corresponding comparison test result in the status register and write to the corresponding control sections 11 and 21. An interrupt is generated to report the abnormal state of the bus to the upper processor.

However, if the communication between the processors 10, 20 is different back-plane (IP-C) is performed through the cable, the data of the A-BUS (13, 23) or B-BUS (14, 24) If an error occurs on the line, it cannot be detected.

To prevent this, the received data of the A-BUS 13, 23 and the received data of the B-BUS 14, 24 are compared to the data lines of the A-BUS 13, 23 and the B-BUS 14, 24. When an error occurs, the interrupt is generated and set in the status register section 12-5 and 22-5, and an interrupt is generated so that the processor can detect an abnormal bus.

As described above, the present invention examines the normal operation of the active bus and the standby bus through a loopback test using IPC data under the control of the control unit for the GS-bus implemented by the duplication of the active bus and the standby bus. In addition, by checking the input data after loopback in the GS-bus logic unit to verify the bus in real time, the status of the active bus and the standby bus can be identified to improve the reliability and stability of the system.

Claims (1)

Control unit 11, 21 for controlling IPC data communication, and A-BUS 13, 23 and B-BUS 14, 24 for interfacing IPC data with GS-bus implemented by dualization of active bus and standby bus. In an exchanger having First comparison circuits 12-1 and 22-1 comparing the IPC data applied through the A-BUS 13 and 23 with the IPC data applied from the controllers 11 and 21 and checking whether they are the same; ; Second comparison circuits 12-2 and 22- that compare the IPC data applied through the A-BUS 13 and 23 and the IPC data applied through the B-BUS 14 and 24 to check whether they are identical. 2) and; Third comparison circuit parts 12-3 and 22-3 for checking the same by comparing IPC data applied through the B-BUSs 14 and 24 with IPC data applied from the controllers 11 and 12; ; Selecting one of the IPC data applied through the A-BUS (13, 23) and the B-BUS (14, 24) to compare with the IPC data applied through the control unit (11, 21) and check whether the same Eleventh comparison circuit sections 12-4 and 22-4; According to whether each test result from the first comparison circuit unit 12-1 and 22-1 to the fourth comparison circuit unit 12-4 and 22-4 is stored, the state of each test result is stored in a status register and an interrupt signal is generated. To generate an interrupt and report the abnormality of the GS-bus via the A-BUS 13 and 23 and the S-BUS 14 and 24 to the controller 11 and 21. 22-5) standby bus test circuit in the exchange, characterized in that consisting of.