KR920007140B1 - Electronic switching maintenance system - Google Patents

Abstract

The circuit checks that the only one terminal control unit sends data utilizing a data transmission bus occupying signal and a down counter so that the maintenance unit detects faults of terminal. The circuit includes a transmission order violation detector (40) for generating interrupt signalwhen the transmission order is violated, a duplicated transmission detector (50) for checking that overlapped data transmission signal is occured, and a long time transmission bus occupation detector (60) for checking the long time transmission bus occupation.

Description

Data transmission bus monitoring circuit of electronic switching device

1 is a configuration of a signal terminal group device to which the present invention is applied.

FIG. 2 is a block diagram of a processor unit in the signal terminal group maintenance device of FIG.

3 is a block diagram of a logic unit in the signal terminal group maintenance device of FIG.

4 is a frame format diagram of a signal message used in the present invention.

5 is a block diagram showing the configuration of a data transmission bus monitoring circuit according to the present invention.

Figure 6 is a circuit diagram of an embodiment of the transmission sequence violation monitoring unit of Figure 5;

7 is an input / output signal timing diagram of a transmission sequence violation interrupt generation unit.

* Explanation of symbols for main parts of the drawings

1: Processor 2: Logic

3: signal terminal network node 4: level 1 matching device

5, 6: Signal terminal bus 7: Signal terminal group maintenance device

8: signal terminal 20: central processing unit circuit

21: Self redundancy control circuit 22: Logic part and level 1 matching device matching circuit

23: signal terminal bus matching circuit 30: input / output port circuit

31: clock generation circuit 32: redundancy control circuit

33: interrupt control circuit 34: data transmission bus monitoring circuit

35: data receiving bus monitoring circuit 36: triplex signal monitoring circuit

37: maintenance command transmission and signal terminal status reading circuit

38: signal terminal network node matching circuit

39: signal terminal bus matching circuit 40: transmission sequence violation monitoring unit

41, 410: address latch circuit 42, 420: flag latch circuit

43, 430: comparator 44, 440: interrupt generation circuit

45, 450: down counter 46, 460: sending address latch circuit

47, 470: Transmission counter latch circuit 50: Simultaneous simultaneous transmission monitoring unit

51: Duplicate simultaneous sending address latch circuit 52: Duplicate simultaneous sending address latch circuit

60: long time transmission bus occupancy monitoring unit

61: long time transmission bus occupied address latch circuit

62: long time transmission bus occupied signal generating circuit

The present invention relates to a data transmission bus monitoring circuit in a signal terminal maintenance device implemented in a common line signaling device of an electronic switch, and more particularly, to a transmission in a signal terminal group having a plurality of signal terminal control devices and a device for performing maintenance thereof. The present invention relates to a data transmission bus monitoring circuit of an electronic switch signal terminal maintenance device that monitors whether only one signal terminal control device transmits data at a time.

There is a maximum of 32 signal terminal controllers in one signal terminal group, and only one signal terminal controller can transmit data at the time of transmission. The maintenance device detects the failure of the signal terminal in real time. In order to maximize the reliability of the common line signaling device by performing diagnosis and quick troubleshooting, it is necessary to detect whether data is actually transmitted in a round robin manner as described above.

The present invention has been made in accordance with the above-mentioned request, and the state when an abnormality occurs in comparison with the value of the transmission bus occupied address generated by using the data transmission bus occupied signal and the down counter and the value extracted through the originating address of the message sent by the signal terminal control apparatus. The object of the present invention is to provide a data transmission bus monitoring circuit of a signal terminal maintenance apparatus for reporting and maintaining information at a higher level.

In order to achieve the above object, the present invention provides a signal terminal maintenance apparatus for an common exchange signaling apparatus of an electronic exchange, which monitors data transmission status within a signal terminal group having a plurality of signal terminal control apparatuses and a device for performing the maintenance thereof. In the data transmission bus monitoring circuit, a transmission sequence violation monitoring means connected to a clock generation circuit, a signal terminal bus matching circuit, an input / output port circuit, an interrupt control circuit, and an internal data bus to generate an interrupt when a transmission sequence violation occurs, and a plurality of signals. Connected to the terminal control unit, the redundant processor unit in the signal terminal maintenance unit, the interrupt control circuit, and an internal data bus to simultaneously monitor whether two or more of the signal terminal control unit and the processor unit overlap and occupy data transmission signals. Transmission monitoring means, said transmission sequence violation monitoring means, clock generation time A signal terminal connected on the terminal bus is composed of an interrupt control circuit and a long time transmission bus occupancy monitoring means connected to the internal data bus for monitoring a device occupying the transmission bus for a fixed time and generating an interrupt in the presence. The device and the signal terminal maintenance device detect an abnormal condition when sending a message at a higher level.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a structural diagram of signal terminal groups in a common line signaling apparatus to which the present invention is applied. The signal terminal group includes a plurality of signal terminals 8, signal terminal buses 5 and 6, and a signal terminal group maintenance apparatus 7. The signal terminal bus is divided into a data transfer bus group 6 and a maintenance signal group 5, and the signal terminal group maintenance device includes a redundant processor unit 1 and a redundant logic unit 2. Operation and standby (active / standby).

The logic unit 2 may change its state by its redundancy control or under the control of an operating processor, and all input signals may be received regardless of its own state, and all output signals may be operated in a logic unit. In this case, the logic unit is driven only in the standby state and is configured to maintain a tai state.

The data transfer bus group 6 is a serial bus capable of accommodating up to 32 signal terminal control devices 8 and is composed of a data transmission bus, a data reception bus, a data transmission / reception clock, a synchronization signal, and a data transmission bus occupied signal. The signal is operated in triple mode. The signal terminal network node 3 serves to provide a communication path between a group of signal terminals and a higher level processor. The maintenance signal group 5 refers to all the signal groups for controlling whether or not the data transmission signal group is normally operated, the signals for monitoring and the respective signal terminal control devices. The level 1 matching device 4 has a function of receiving data from a maximum of 32 signal terminal controllers, multiplexing the data from the time switch, and demultiplexing the data from the time switch to the signal terminal controller.

2 is a block diagram of a processor unit in a signal terminal group maintenance unit, which includes a central processing unit circuit 20, a self-duplication circuit 21, a logic unit, a level 1 matching device matching circuit 22, and a signal terminal bus matching circuit ( 23). The central processing unit circuit 20 is composed of a general-purpose CPU and a memory, a program, and a peripheral circuit to perform a function of centrally controlling a group of signal terminals and a level 3 function and a function of transmitting and receiving a message through a signal terminal bus. The logic section and the level 1 matching device 22 have a function of extending the address bus and the data bus, which are the system buses of the processor section, to the level 1 matching device 4, and receive interrupts from the logic section and the level 1 matching device. That is, a function of sending a stamp, a reset signal is sent to the logic unit 2 and the level 1 matching device 4, and the collection state and the redundancy state control function of the logic unit 2 and the level 1 matching device 4 are performed. . The self-redundancy control circuit 21 initially operates only one side, and if one side is dismounted, the mounted board becomes an operating state, and if a board in an operating state fails, the standby board becomes an operating state. In addition, by placing a switch on each board, the ON time is always in operation state, and if both boards fail at the same time, one side maintains the operation state.

3 is a block diagram of the logic unit in the signal terminal group maintenance apparatus, and performs its own redundancy function, processor matching function, node matching function, and maintenance related function. The input / output port circuit 30 operates the logic related circuit or collects and transfers necessary data according to the contents of the address bus and the data bus input from the processor unit. The clock generation circuit 31 generates a node clock having the same phase as a data transmission / reception clock which is a signal terminal bus clock, and supplies each signal terminal and a signal terminal network, and also supplies a synchronization signal of the signal terminal bus to all signal terminals. The redundancy control circuit 32 operates in an operation and standby manner, and when a change is made in the redundancy state, a board transitioned from the standby state to the operation state sends a level 1 interrupt to the processor. The interrupt control circuit 33 has eight types of level 1 interrupts, seven of which occur in the logic unit 2 and one of which occurs in the level 1 matching device 4. Each of the seven types of interrupts generated in the logic section has status registers to determine the cause of the interrupt. It is also configured to enable or disable interrupts for each cause by creating an interrupt enable register. The data transmission bus monitoring circuit 34 has three functions: a function of monitoring whether a signal terminal that does not match the transmission sequence is transmitting a message, and a function of monitoring a case where two or more signal terminals simultaneously transmit a message, and There is a function that can distinguish the signal terminals occupying the data transmission bus for more than one time, and these three functions are each sent by the level 1 interrupt to the processor unit. The data reception bus monitoring circuit 35 determines whether a signal terminal is normally received through a data reception bus through a data reception bus, and if not, informs the processor unit of the destination address information using a level 1 interrupt. The signal terminal bus is composed of a data transmission / reception clock, a synchronization signal, a data transmission bus occupancy signal, and a data transmission / reception bus, and is operated as a triple. When a fault occurs in any of the three signal lines, the triple signal monitoring circuit 36 detects this. The generated part information is stored in the buffer and delivered to the processor unit as a level 1 interrupt. Maintenance command transmission and signal terminal status reading circuit 37 is a circuit that attempts to control when the signal terminal fails and fails to operate normally. Clearing signal terminal alarm status, allowing signal terminal bus occupancy, signal terminal bus occupancy not allowed, signal Terminal test request and signal terminal reset request. The signal terminal network node matching circuit 38 converts the data of the signal terminal bus and the node clock of the clock generation circuit into differential signals and transmits and receives them to the signal terminal network node. The signal terminal bus matching circuit 39 is a circuit for connecting to a signal terminal bus operated in a triple operation. The signal terminal bus matching circuit 39 receives two signal lines having the same logic level among the three signal lines upon reception and outputs one signal as three signal lines upon transmission. Has the function.

4 shows a signal message frame format used in the present invention. The start flag F marks the start of one signal unit and the end flag F marks the end of one signal unit. The start flag of one signal unit is usually the end flag of the preceding signal unit, and the bit pattern of each flag is '01111110'. The destination address and the source address are each composed of 16 bits, where A1 is the destination processor address and A2 is the destination processor node address. , A3 represents the source signaling terminal address and A4 represents the source signaling terminal node address. DATA stands for No.7 message and does not exceed 291 bytes at maximum. The Frame Check Sequence (FCS) is used to detect errors of all signal units and consists of 16 bits. The signal message frame transmission sequence is transmitted in order from the least significant bit (L) as shown in FIG.

5 is a block diagram showing the configuration of a data transmission bus monitoring circuit according to the present invention, which is largely divided into a transmission sequence violation monitoring unit 40, a redundant simultaneous transmission monitoring unit 50, and a long time transmission bus occupancy monitoring unit 60. The transmission sequence violation monitoring unit 40 includes an address latch circuit 41, a clock generation circuit (31 in FIG. 3) connected to a clock generation circuit (31 in FIG. 3) and a signal terminal bus matching circuit (39 in FIG. 3). The flag latch circuit 42 connected to the address latch circuit 41, the comparator 43 connected to the address latch circuit 41 and the down counter 45, the address latch circuit 41 and the flag latch circuit 42. And an output terminal connected to the comparator 43 and an output terminal connected to an interrupt control circuit (33 of FIG. 3), a down counter 45 connected to the comparator 43 and the output counter latch circuit 47. Input / output port circuit (30 in FIG. 3) and the address latch circuit An input terminal is connected to the 41 and the interrupt generating circuit 44, and an output terminal is connected to the output address latch circuit 46 connected to the processor unit (1 in FIG. 1) through an internal data bus IDB 0-7, and an input / output port circuit. (30 in FIG. 3), an input terminal is connected to the interrupt generating circuit 44 and the down counter, and an output terminal is connected to a processor counter (1 in FIG. 1) via an internal data bus IDB 0-7. 47), the redundant simultaneous transmission monitoring unit 50 has an input terminal connected to up to 32 signal terminal control devices 8 and a redundant signal terminal maintenance processor unit 1, and the output terminal has an interrupt control circuit (see FIG. 3) is connected to the redundant simultaneous transmission detection circuit 52 consisting of a PROM and the input terminal is connected to the 32 signal terminal control device 8 and the redundant signal terminal maintenance processor unit 1, and the output terminal is internally connected. Processor section via data bus (IDB 0-7) It consists of a connected simultaneous simultaneous address latch circuit 51, and the long-term transmission occupancy monitoring unit 60 has an input terminal connected to a clock generation circuit (31 in FIG. 3) and an output terminal connected to an interrupt control circuit (33 in FIG. 3). An input terminal is connected to the long time transmission bus occupancy signal 62, the long time transmission bus occupancy signal generation circuit 62, and the down counter 45 of the transmission sequence violation monitoring unit 40, and the output terminal is an internal data bus IDB 0-. 7) a long time transmission occupancy address latch circuit 61 connected to the processor section (1 in FIG. 1).

The data transmission bus monitoring circuit configured as described above allows the signal terminal control apparatus to collect and maintain all abnormal conditions occurring when the data transmission bus is occupied and report them to a higher level.

The transmission sequence violation monitoring unit 40 receives the signal terminal bus clock NCLK1 * from the clock generating circuit (31 in FIG. 3) before transmitting all data on the signal terminal bus to the signal terminal network node (3 in FIG. 1). ) Is latched to the flag latch circuit 42 and the address latch circuit 41 respectively. The flag latch circuit latches the flag F, and the address latch circuit latches the destination address A1, the destination node address A2, and the source address A3, respectively. Of course, the signal terminal transmission data is transmitted upward through the signal terminal network node matching circuit (38 in FIG. 3) through the first shift register, and the address portion is extracted as described above for every message frame. At the moment when 4 bytes of information are latched, the interrupt generating circuit 44 latches the input data combining the flag F and the destination address A1 using the inverted signal terminal bus clock NCLK1 to send the source address A3. ) Is read and output on the sending address bus inside the monitoring circuit.

As above, the address of the message is extracted from the transmitting data bus and the initial value 0 is input by using the data transmission occupancy signal (TXAST *), synchronization signal (MSYNC *) and signal terminal bus clock (NCLK1 *) on the signal terminal bus. The down counter 45 starts counting down. This down counter is operated in the same manner as the transmission mediation circuit of the signal terminal 8, and when the specific signal terminal is transmitting data, the counter stops and the counting is continued. The originating address (output of the address latch circuit 41) and the output address of the down counter 45 are the input data of the comparator 43 and the output signal (if the two addresses are different from each other). MATCHTX * is negated and sent to the interrupt generating circuit, and the interrupt generating circuit 44 requests the outgoing data error interrupt signal INTTXERR * to the interrupt control circuit (33 in FIG. 3). The interrupt control circuit 33 sends a level 1 interrupt to the processor unit (1 in FIG. 1) when the corresponding item among the eight interrupts is enabled, and reads the transmission address using the input / output port circuit (30 in FIG. 3) in the interrupt routine. Generates a signal TXDRRD * and a send counter read signal TXCNTRD * to access the feed address latch 46 and the feed counter latch 47, respectively, and read their values using the internal data bus IDB 0-7. Transfer to processor section (1 in FIG. 1). The processor unit 1 sends an interrupt acknowledgment signal to the interrupt generation circuit 44 to clear the interrupt state for the corresponding message to the initial state.

Simultaneous redundancy transmission monitoring unit 50 is a circuit that monitors the passage of up to 32 signal terminal control devices (8 in FIG. 14) and two or more of redundant signal terminal maintenance devices occupying data transmission signals. In each device, a separate data transmission occupancy signal TXEN * is extended to be input to the redundant simultaneous transmission detection circuit 52. The redundant simultaneous transmission detection circuit is composed of five PROMs (Programmable Read Only Memory) to generate an interrupt when two or more of the 34 data transmission occupancy signals TXEN * are asserted. The PROM is composed of two stages, allowing up to nine data transmission occupancy signals (TXEN *) to be input using four PROMs in the first stage, and two output data bits are finally collected from one PROM in two stages. It is. The first stage outputs when the data transmission occupancy signal (TXEN *) is not asserted according to the input data in each PROM, when only one is asserted, and when there are two or more asserts. Input data as two levels of input data. Step 2 is when the PROM is enabled and the data transmission occupancy (TXEN *) input signals of the four PROMs are not all asserted, and only one of the four PROM data assertion signals (TXEN *) is asserted ( In the case of assert, it does not generate an interrupt only when inputting the data outputted in step 1, but otherwise it is designed to generate an interrupt. When an interrupt occurs, the corresponding address of the input / output port circuit (30 in FIG. 3) is accessed to read the device sending the data transmission occupancy signal from the duplicate simultaneous transmission address latch 51 and report to the upper level.

As described above, the long time transmission bus occupancy monitoring unit 60 includes a long time transmission bus occupancy signal generation circuit 62 and a long time transmission occupancy address latch 31. The long time transmission bus occupancy signal generation circuit 62 uses a counter and counts the time by receiving the long time occupancy clock LASTCLK from the clock generation circuit (31 in FIG. 3). This time shall be calculated to be greater than the time required for each device connected on the signaling bus to send the maximum number of messages specified. If the transmission bus is occupied for a fixed time or more, the transmission bus monitoring signal (LASTDT) is generated through the counter and the loop for a long time and the transmission bus occupancy interrupt (INTLAST *) is generated. By reading the long time transmission occupancy address latch 61 connected to the counter 45 output, the transmission bus occupancy address can be identified to identify the device.

6 is a detailed circuit diagram of the transmission sequence violation monitoring unit 40 of the data transmission bus monitoring circuit according to the present invention, where 410 is an address latch circuit, 420 is a flag latch circuit, 430 is a comparator, and 440 is an interrupt generation circuit. , 450 is a down counter, 460 is a sending address latch circuit, 470 is a sending counter latch circuit, and as shown in the drawing, the address latch circuit 410 is a clock generating circuit (31 in FIG. 3) and a signal terminal bus matching circuit. A first shift register 411 connected to (39 in FIG. 3), a clock generation circuit and a second shift register 412 connected to the first shift register, a clock generation circuit and a third shift register connected to the second shift register. And a D flip-flop circuit 414 connected to the first shift register 411. The first shift register 411 latches a source address (A3 in FIG. Soft register 412 latches the incoming sikimyeo addressable node (degrees A2. 4), in the third shift register 413, thereby latching the destination address (the fourth-degree A1). In addition, signal terminal transmission data is sent to the signal terminal network node matching circuit through the first shift register 411, and the source address A3 is transferred to the address address bus inside the supervisory circuit through the D flip-flop circuit 414. Output

The flag latch circuit 420 is composed of one shift register. The flag latch shift register 421 is connected to the third shift register 413 of the clock generation circuit and the address latch circuit, and the flag (F: 'in FIG. 01111110 ').

The down counter 450 is composed of four bit up / down counters 451 and 452, each of which has an input terminal coupled to a clock generation circuit and a signal terminal bus matching circuit and an output stage comparator. 430 and the output counter latch circuit 470. As the address latch circuit extracts the address portion of the message on the transmit data bus, the down counter is used for the data transmission occupancy signal TXAST * and the synchronization signal NSYNC * from the signal terminal bus matching circuit and the signal terminal bus from the clock generation circuit. Outputs the address of the transmission bus occupied device using the clock (NCLKI *). The initial value is "0" to start counting down, and stop counting when a specific signal terminal is transmitting data. Do it.

The comparator 430 is composed of a sending address bus inside the supervisory circuit and an 8-bit address comparator 451 connected to the output terminal of the down counter 450. The comparator 430 is an originating address (A3: D flip) of a message being transmitted to the data transmitting bus. The output address of the flop circuit 414) and the output address of the down counter 450 are inputted, and when the two addresses are different from each other, a transmission match signal MATCHTX * is negated and output.

를 어드레스 래치회로의 D플립플롭회로(414의 CK)에 연결한 제 1D플립플롭(445), 상기 비교기(431)의 출력단에 데이터 입력단(D)을 연결하고 상기 제 1D플립플롭의 정출력단(Q)에 클럭 입력단(CK)을 연결한 제 2D플립플롭(446), 5V 전원에 데이터 입력단(D)을 연결하고 상기 제 2D플립플롭(446)의 정출력단(Q)에 클럭 입력단(CK)을 연결하며 정출력단(Q)은 송출 어드레스 래치(461) 및 송출 카운터 래치회로(471)의 클럭 입력단(CK)에 연결하고 부출력단

은 인터럽트 제어회로(33)에 연결한 제 3D플립플롭(417), 및 인터럽트 제어회로로부터의 송출 에러신호(TXERR*)와 리셋트 신호(RESET*)를 논리합(AND)하여 상기 제 2D플립플롭(446)의 리셋트 입력단(R)으로 출력하는 AND 게이트(448)로 구성되어 있고, 반전된 신호단말 버스 클럭(NCLK1*)을 이용하여 플래그(F) 및 착신 어드레스(A1)를 조합한 입력 데이터를 래치시켜 발신 어드레스(A3)를 송출하도록 하며 비교기(431)로부터의 송출 매치 신호(MATCHTX*)를 이용하여 송출 데이터 래치신호(THIATCH)를 송출 어드레스 래치신호(460) 및 송출 카운터 래치회로(470)로 출력하고 송출 데이터 에러 인터럽트 신호(INTTXERR*)를 인터럽트 제어회로(제3도의 33)로 출력한다. 미설명 부호 443b 및 443c는 인버터이다.The interrupt generator 440 may include a first NAND gate 441 connected to an output terminal of the third shift register 413 of the address latch circuit 410, and an output terminal connected to an output terminal of the shift register 421 of the flag latch circuit 420. 2NAND gate 442, an inverter 443a connected to an output terminal of the first NAND gate 441, an OR gate 414 connected to an output terminal of the inverter and the second NAND gate 442, and a data input terminal at an output terminal of the OR gate D) and the inverter 443d connected to the clock generator circuit to the clock input terminal (CK) and to the negative output terminal.

Is connected to the first flip-flop 445 connected to the D flip-flop circuit 414 of the address latch circuit, and the data input terminal D is connected to the output terminal of the comparator 431, and the positive output terminal of the first D flip-flop ( 2D flip-flop 446 with a clock input terminal CK connected to Q), and a data input terminal D with a 5V power supply, and a clock input terminal CK with a positive output terminal Q of the 2D flip-flop 446. The output terminal Q is connected to the clock input terminal CK of the output address latch 461 and the output counter latch circuit 471, and the negative output terminal

Is AND of the 3D flip-flop 417 connected to the interrupt control circuit 33 and the transmission error signal TXERR * and the reset signal RESET * from the interrupt control circuit, and the second D flip-flop And an input gate (448) outputted to the reset input terminal (R) of (446). The input is a combination of the flag (F) and the destination address (A1) using the inverted signal terminal bus clock (NCLK1 *). The data is latched so that the originating address A3 is transmitted and the outgoing data latch signal THIATCH is sent out using the outgoing match signal MATCHTX * from the comparator 431. 470), and output data error interrupt signal INTTXERR * to the interrupt control circuit (33 in FIG. 3). Reference numerals 443b and 443c are inverters.

The sending address latch circuit 460 is an 8-bit latch circuit 461 connected to an input terminal D1-D8 to a sending address bus inside the monitoring circuit and an output terminal Q1-Q8 connected to an internal data bus IDB 0-7. 74LS374) to latch the originating address A3 output through the D flip-flop circuit 414 of the address latch circuit.

The output counter latch circuit 470 is an 8-bit latch circuit 471: 74LS374 having an input terminal D1-D8 connected to the down counter 450 and an output terminal Q1-Q8 connected to the internal data bus IDB 0-7. It latches the transmission address sent from the down counter 450.

FIG. 7 is a timing diagram of input / output signals of the transmission sequence violation interrupt generation unit, and is shown in the order of symbols (a-e) shown in the main part of FIG.

As shown in the drawing, when the input data of the comparator 430 does not match, the transmission match signal MATCHTX * is output as “1” and the second D flip-flop output signal e which is maintained at the initial state “0”. Generates an interrupt on the rising edge according to the state of the outgoing match signal MATCHTX *. The dashed line in the figure shows a normal operating state.

As described above, the present invention monitors whether only one device transmits data at a time by an arbitration circuit when transmitting in a signal terminal group in which a plurality of signal terminal control devices and a redundant signal terminal maintenance device exist. By reporting the status information of the situation that cannot be transmitted evenly in case of abnormality at the high level, the maintenance device can detect the failure of the signal terminal in real time and promptly troubleshoot the reliability of the common line signal device. Has the effect of maximizing.

Claims (8)

A data transmission bus monitoring circuit in a signal terminal maintenance device of a common line signaling device of an electronic exchange, which monitors data transmission status in a signal terminal group having a plurality of signal terminal control devices and a device for performing the maintenance thereof; It is connected to the clock generation circuit 31, the signal terminal bus matching circuit 39, the input / output port circuit 30, the interrupt control circuit 33, and the internal data burr (IDB 0-7) to generate an interrupt in case of transmission sequence violation. Transmission sequence violation monitoring means 40, a plurality of signal terminal control devices 8, a redundant processor unit 1 in the signal terminal maintenance device, an interrupt control circuit 33, and an internal data bus IDB 0-. 7) redundant simultaneous transmission monitoring means 50 for monitoring whether two or more of the signal terminal control device and the processor unit occupy a data transmission signal in duplicate, the transmission sequence violation monitoring means 40, and the clock generation circuit. (31), an interrupt control circuit 33 and a long time transmission bus occupancy monitoring means connected to the internal data bus (IDB 0-7) to monitor whether there is a device occupying the transmission bus for a fixed time or more and generate an interrupt in existence The terminal consists of 60 Monitoring of data transmission buses of the signal exchange maintenance device of the electronic exchange characterized in that an abnormal state is detected when the signal terminal control device 8 and the signal terminal maintenance device 7 connected to the switch transmit a message to a higher level. Circuit. 2. The transmission sequence violation monitoring means (40) according to claim 1, wherein the transmission order violation monitoring means (40) includes an address latch circuit (41), a clock generator circuit (31), and the address latch connected to a clock generation circuit (31) and a signal terminal bus matching circuit (39). The flag latch circuit 42 connected to the circuit 41, the comparator 43 connected to the address latch circuit 44 and the down counter 45, the address latch circuit 41 and the flag latch circuit 42, and the comparator An input terminal is connected to the 43 and an output terminal is an interrupt generating circuit 44 connected to an interrupt control circuit 33, a down counter 45 connected to the comparator 43 and a sending counter latch circuit 47, and an input / output port circuit ( 30 is connected to the address latch circuit 41 and the interrupt generating circuit 44, and an output terminal is connected to an output address latch circuit 46 connected to the internal data bus IDB 0-7, and an input / output port circuit 30. And the interrupt generator 44 and the down counter 45. Stage is connected and the output is the internal data bus (IDB 0-7) sent counter latch signal terminal electronic switching device maintaining the data transmission bus monitoring circuit, characterized by consisting of a circuit 47 connected to the. The first shift register (411) of claim 2, wherein the address latch circuit (41) is connected to the clock generation circuit (31) and the signal terminal bus matching circuit (39) and latches the source address (A3). A second shift register 412, a clock generation circuit 31, and the second shift register 412, coupled to the generation circuit 31 and the first shift register 411, for latching the called destination address A2. A third shift register 413 connected to the first shift register 413 and a first shift register 411 connected to the first shift register 411 and outputting a source address A3 to a transmission address bus inside the supervisory circuit. A data transmission bus monitoring circuit of an electronic exchange signal terminal maintenance device, characterized in that it comprises a flip-flop circuit (414). 3. The address of the transmission bus occupancy apparatus according to claim 2, wherein the down counter (45) uses the data transmission occupancy signal (TXAST), the data clock signal (NCLK1 *), and the data synchronization signal (NSYNC *) on the signal terminal bus. Data transmission bus monitoring circuit of the electronic switch signal terminal maintenance device characterized in that it outputs. The comparator 43 according to claim 3 or 4, wherein the comparator 43 outputs a source address A3 output from the D flip-flop circuit 414 of the address latch circuit 410 and a transmission output from the down counter 45. A data transmission bus monitoring circuit of an electronic switch signal terminal device characterized in that an interrupt is generated by outputting a match signal (MATCHTX *) when the addresses are different from each other by comparing addresses. 3. The shift register of claim 2, wherein the interrupt generation circuit 440 includes a first NAND gate 441 connected to an output terminal of a third shift register 413 of the address latch circuit 410, and a shift register of the flag latch circuit 420. A second NAND gate 442 connected to an output terminal; an inverter 443a connected to an output terminal of the first NAND gate 441; an OR gate 444 connected to an output terminal of the inverter and the second NAND gate 442; The data input terminal D is connected to the output terminal of the OR gate, the inverter 443d connected to the clock generation circuit is connected to the clock input terminal CK, and the sub output terminal is connected to the clock input circuit CK.

Is connected to the D flip-flop 445 of the address latch circuit (CK terminal of 414), the data input terminal D is connected to the output terminal of the comparator 43, and the positive output terminal Q of the first D flip-flop is connected. 2D flip-flop 446 connected to the clock input terminal CK, a data input terminal D to the power supply terminal, and a clock input terminal CK to the positive output terminal Q of the 2D flip-flop 446. The positive output terminal Q is connected to the clock input terminal CK of the feed address latch circuit 461 and the feed counter latch circuit 471, and is connected to the negative output terminal.

Is the third D flip-flop 417 connected to the interrupt control circuit 33, and the second error signal RESET * and the reset signal RESET * from the interrupt control circuit are OR'ed together. An AND gate 448 for outputting to the reset input terminal R of the control unit so that a transmission address is extracted, and a transmission data latch signal TXLATCH and a transmission data error interrupt signal INTTXERR * are output. Data transmission bus monitoring circuit for the maintenance device of the signal exchange terminal of the electronic exchange. 2. The simultaneous transmission monitoring unit (50) according to claim 1, wherein an input terminal is connected to a maximum of 32 signal terminal control devices (8) and a redundant signal terminal maintenance processor (1) and an output terminal is an interrupt control circuit (33). A redundant simultaneous transmission detection circuit 52, which is composed of five PROMs, and an input terminal is connected to the signal terminal controller 8 and a redundant signal terminal maintenance processor unit 1, and an output terminal is connected to an internal data bus ( It is composed of redundant simultaneous sending address latch circuits 51 connected to IDB 0-7) so that the signal transmission bus occupied by each signal terminal control device and signal terminal maintenance device can be separately extended (34 TXEN * Data from the electronic exchange signal terminal maintenance device, characterized in that when two or more devices occupy the data transmission bus at the same time, it generates an interrupt to read the bus occupied state. Transmit bus monitoring circuit. The long time transmission bus occupancy signal generating circuit (62) according to claim 1, wherein the long time transmission bus occupancy monitoring means (60) is connected to a clock generation circuit (31) and an output terminal is connected to an interrupt control circuit (33). The input terminal is connected to the down counter 45 of the long time transmission bus occupied signal generation circuit 62 and the transmission sequence violation monitoring means 40, and the output terminal is connected to the internal data bus IDB 0-7. Maintaining an electronic exchange signal terminal which counts the time occupied by each device connected on the bus and occupies the transmission bus for more than a specified time, and generates an interrupt to read and identify the address of the corresponding transmission device. Data transmission bus monitoring circuit for maintenance equipment.

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