KR0176085B1 - Error detecting method of processor node and node network of parallel computer system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system configuration method for data parallel processing of a computer system. In particular, the present invention relates to a predetermined number of bus groups composed of a predetermined number of input / output buses and one-to-one connection to the input / output buses constituting the bus group. Data with the data storage means through a predetermined number of data storage means capable of storing and accessing data through an arbitrary bus group, and an I / O bus which is connected one-to-one to the bus group and constitutes the bus group. A predetermined number of processing units comprising a predetermined number of data input / output control means for controlling transmission and reception, and first and second processing nodes connected to separate serial communication lines for exchanging information for status diagnosis and performing the same function. Data connection between the node group and the processing node groups and data input / output control means. A parallel processing computer system comprising a predetermined number of node interconnection networks and an error detection method operating in the system, thereby simplifying the configuration of the system so as to reduce the configuration cost, and any of the resources constituting the system. In the event of a fault in the resource of the system, the system can be detected and repaired within the extent that the system does not stop and data loss does not occur.

Description

Error Detection Method of Processor Node and Node Connection Network in Parallel Processing Computer System

1 is a simplified block diagram of a conventional parallel processing computer system employing a processor duplication method.

2 is a simplified block diagram of a conventional parallel processing computer system employing a processor triple system.

3 is a simplified block diagram of a couple of parallel processing computer systems according to the present invention.

* Explanation of symbols for main parts of the drawings

PN1-PNN, PNa-PNc, 10A, 10B, 20A, 20B: processing node

IN: Network BF: Shared Buffer

M1,2: Memory IOP1,2: I / O Processor

IOB, 2: I / O bus DB1,2: Bus group

D1,2: disk ION1,2: I / O processor node

INN1,2: Node interconnection network SL: Serial communication line

SB1,2: System bus Ba, Bb: Buffer memory

NIF: Interfacing Circuit (Network Interface)

SIF: Serial Communication Connection Circuit (Serial Interface)

The present invention relates to a system configuration method for data parallel processing of a computer system. In particular, a computer node adopting a parallel data processing method detects a processor node in which an operation error or a defect occurs and separates it from the entire system. The present invention relates to an error detection method of a processor node and a node connection network in a parallel processing computer system for preventing a malfunction of a system and preventing a system from stopping.

In general, a parallel processing computer system is equipped with a plurality of processors, each processor performs a unique function or a single function to perform a parallel processing of data to perform a fast function, a very complex function example For example, there is an advantage that can implement a function such as artificial intelligence.

However, since a plurality of processors are generally connected, there is a disadvantage in that any one of a processor malfunction or inoperability may cause a loss of the entire system function.

In order to overcome the drawbacks described above, the conventional improvement schemes are proposed. First, a second scheme and a third scheme of dualizing processors performing respective functions in a parallel computer system have been proposed.

In the conventional method as described above, a plurality of processing nodes PN1 to PNN, and third and fourth processing nodes ON3 and 4, respectively, are illustrated in FIG. One processing node group is configured, and each processing node group is duplicated by configuring two processing nodes constituting the same to perform the same function.

In addition, the network IN connecting the processing nodes PN1 to PNN is connected to a distributed or shared buffer BF for storing information on the operation result or state of the processing nodes.

The parallel processing computer system according to the first scheme having the above configuration has the advantage that the configuration is simple and the installation cost is reduced, while the amount of state information stored in the shared buffer (BF) is increased or each processing is performed. When the time difference between check points for checking the status of nodes is shortened, the load of the network IN connecting each processing node increases, which causes a problem of reducing the efficiency of the system. Lose.

In addition, in contrast to the above-described case, when the time interval between checkpoints is widened, a problem arises in that the reliability of the entire system is low.

Unlike the first scheme described above, the second scheme in which the processing nodes constituting each processing node group is tripled is shown in FIG. 2, and a plurality of processing node groups have two input / output buses (IOB1). It is connected to the secondary memory (D) through, 2).

The processing node order is three processing nodes PNa to PNc performing the same function, first and second memories M1 and 2 connected to the processing nodes PNa to PNc, and the input / output bus IOB1, 2) the first and second input / output processors IOP1 and 2 are connected to the memories M1 and 2 through the second and second memories.

In addition, the first I / O processor IOP1 is connected to the first I / O bus IOB1, and the second I / O processor IOP2 is connected to the second I / O bus IOB2. The parallel processing computer system according to the second method configured as described above has an advantage of easily detecting a defect in the processing node group including the processing nodes PNa to PNc, but the cost of the system is increased. Is generated.

An object of the present invention for solving the above problems is to simplify the configuration of the system to reduce the configuration cost of the system, while processing errors or defects occurred in the computer system applying a parallel data processing method to the operation system The present invention provides a method for detecting errors in a parallel processing computer system to detect a group and isolate the system from the entire system so that a user can obtain a normal output without stopping a system for maintenance.

A feature of the present invention for achieving the above object is a parallel processing computer system having a plurality of processor nodes, comprising: a predetermined number of bus groups composed of a predetermined number of input / output buses, and an input / output bus constituting the bus group. A predetermined number of data storage means capable of storing and accessing data through an arbitrary bus group connected to each other one-to-one, and an I / O bus connected to the bus group one-to-one respectively to form the bus group. A predetermined number of data input / output control means for controlling data transmission / reception with data storage means, and first and second processing nodes connected with separate serial communication lines for exchanging information for status diagnosis and performing the same function. A predetermined number of processing node groups and data processing groups It may comprise a node interconnection network of a predetermined number for the data connection between the output control means.

An additional feature for achieving the above object is that a processing node constituting the processing node group includes a predetermined number of processors each performing a separate function, and an operating and status diagnosis program connected to a system bus connecting the processors. And a shared memory for storing data generated by the processors, an interfacing circuit having a predetermined number of channels and connected to one node interconnection network for each channel to perform a data connection function through the system bus; A serial communication connection circuit for transmitting and receiving data over a line and a buffer memory for storing information transmitted and received through the serial communication connection circuit.

Another aspect of the present invention for achieving the above object, in a parallel processing computer system having a plurality of processing node group consisting of two processing nodes in the error detection method of the processor node, a specific event such as interrupt The calculation result and the register value of the processor generated by each processing node occurring at the same time or at each processing node forming the node group at a predetermined point in time are stored in the buffer memory of the corresponding processing node through the serial communication connection circuit. The first step of the transmission, the operation result and the register value transmitted to the buffer memory from the partner processing node to read the operation result and register value transmitted through the first process, and the own process transmitted through the first process A second comparison with the operation result and the register value In the second step, when comparing data in the second step, it is determined that an error has occurred in its own node group, and each processing node in the corresponding node group stops its operation and any other processing node group. After performing the operation performed in the first process, that is, the operation from the comparison time immediately before it is determined to be in a normal state to the time when the error occurs, the execution result is stopped in the third process. The fourth process of inputting to each processing node in the node group, and each processing node in the node group stopped in the third process compares the normal operation result received through the fourth process with the operation result performed by each of them. Nodes that produce different results through the fifth process and the fifth process are considered to be faulty and alert the user to the occurrence of error. Claim 6 may comprise a process.

Another feature of the present invention for achieving the above object is a processor node in a parallel processing computer system having a plurality of processing node group consisting of two processing nodes and a dual connection network connecting each processor node group In the error detection method of the network, if an error occurs continuously during data transmission in the network that is being used among the dual network nodes, the network is considered to be out of order and the data is transmitted using another network. A first step of alerting an error occurrence state of the network; a second step of selecting an arbitrary node group when it is difficult to determine which of the node interconnection networks provided through the first step is in an error state; Processing to form the selected node family A third process in which the node transmits the same data to different connection networks, and each of the two processing nodes each generates data received through a connection network other than the connection network in which it has transmitted data through the third process. And a fourth process of comparing with the fourth process and a fifth process of determining that a connection network in which different data is received is a failure when the data compared through the fourth process is different from each other and warning a user of an error occurrence state.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment according to the present invention.

3 is a schematic block diagram of a parallel processing computer system according to the present invention, and includes two bus groups DB1 and 2 composed of two input / output buses and two connected to the bus groups DB1 and 2. Two auxiliary memory devices or disks D1 and 2, and two input / output processor nodes ION1 and 202 that control data transmission and reception with the disks D1 and 2, respectively, through the I / O buses constituting the bus groups DB1 and 2; 2) is connected to a serial communication line (SL) for the necessary information exchange and diagnosis between the two processing nodes (10A, 10B) (20A, 20B) performing the same function is configured to enable the diagnosis between the two It consists of two processing node groups and two node interconnection networks INN1,2 for data connection between processing nodes 10A, 10B, 20A, 20B and input / output processor nodes ION1,2.

The two processing node groups of the above configurations are referred to as a cluster in the present invention, and the parallel processing computer system according to the present invention is composed of a plurality of clusters, and the two interconnection networks INN1 and 2 are all connected to the cluster. Commonly connected.

In addition, the paired processing nodes are equipped with serial communication lines (SL) for the necessary information exchange and diagnosis, enabling load reduction and efficient diagnosis of node interconnection networks. It is made accessible through node and I / O bus.

Looking at the configuration of the processing nodes of the above configuration, a predetermined number of processors (Pa1, Pa2) (Pb1, Pb2) and a shared memory, a symmetric multi-processing system (Symmetric Multi) using a common system bus (SB1, 2) -Processor).

At this time, the processors (Pa1, Pa2) (Pb1, Pb2) and the shared memory are connected to the processors Pa1, 2 (Pb1, 2) in the processing nodes 10A, 10B, as shown in FIG. Communication purpose is to save the system operation and status diagnosis program and the data generated by the processors (Pa1, 2) (Pb1, 2) to the shared memory (Ma, Mb) through the connected system bus (SB1, 2).

In addition, a first node interconnection network INN1 and a first channel CH0 are connected, and a second channel CH1 is connected to a second node interconnection network INN2, thereby providing data through the common system bus SB1,2. Storage of information transmitted / received through a network interface (NIF) for connection, a serial interface (SIF) for communication with a paired processing node, and the serial communication connection circuit (SIF). Buffer memory Ba, Bb.

For communication purposes between the processors (Pa1, Pa2) (Pb1, Pb2) and the buffers (memory Ba, Bb), arithmetic results generated by the processors Pa1, 2 included in the processing node 10A. And transfer the register value of the processor to the buffer Bb of the partner processing node 10B via the serial communication connection circuit SIF and the serial communication line SL.

A preferred operation example of the parallel processing computer system according to the present invention configured as described above will be described.

Since the general operation of the system, that is, the normal operation is basically the same as the conventional system, it will be omitted. In the following description, an error detection process for each component will be described in detail.

Two processing nodes (for example, 10A and 10B) that form a group of processing nodes execute the same program twice, and specific nodes such as memory write / read, interrupt or I / O requests occur, The results performed in 10A and 10B are transmitted to the other party via the serial communication line SL (for example, stored in the buffer memory Bb in the first processing node 10B).

After the end of the process, each processing node continues to perform the next task, if the result generated by its processing node and the result received through the serial communication connection circuit (SIF) and stored in the buffer memory are different. Is generated, the processing node group stops the operation because the self or the counterpart has malfunctioned.

After that, other processing nodes in the cluster are allowed to re-execute the function, and after receiving the result of the re-execution from other processing nodes, the same nodes as those generated by the node are recognized as normal nodes. It is considered to be a malfunction.

Therefore, the data result stored in the buffer memory existing in any node itself is not generated by itself, but the data result generated by another node connected through the serial communication line (SL). From the point of view of the data present, a node different from the result received from another processing node is normal.

Therefore, the node that has stopped operating is compared with the data received from the processing node and the data of the buffer memory provided therein, and is operated again when different.

The duplex node interconnection network INN1,2 detects errors in data transmission using an error detection scheme such as parity, checksum or ECC, and if one network (for example, the first interconnection network) If such an error occurs continuously (in IN1), it is determined that the first interconnection network INN1 is a failure.

Stop using the first interconnection network (INN1) that is determined to be a fault for the above reasons, perform data transmission function using only the second interconnection network (INN2), and warn the user of the error occurrence status of the network. To make it possible.

However, if it is difficult to determine which of the provided node interconnection networks INN1 and 2 is in an error state, the serial communication line SL between the first processing node 10A and the second processing node 10B may be disconnected. Each processing node 10A, 10B compares the same data with data generated by itself, and determines that a connection network in which different data is received is a failure.

That is, the first processing node 10A transmits data to the first interconnection network INN1 through the first channel CH0 of the interfacing circuit NIF, and transmits data to the second interconnection network through the second channel CH1. The data received from INN2) is input and compared with the data transmitted through the first channel CH0.

In this case, when the data to be compared are the same, the second interconnection network INN2 is stable, and when it is determined that the data is different, the second interconnection network INN2 is in an error state.

On the other hand, the state of the first interconnection network INN1 is inspected by the second processing node 10B and is the same as the inspection process of the second interconnection network INN2 described above.

In addition, the input / output system allows two input / output processor nodes INN1 and 2 to be connected through the node interconnection network INN1 and 2, and is a shared disk method in which all processing nodes share the input / output system.

One input / output processor node basically provides two input / output buses IOB1 and 2 and is connected to input / output devices such as a magnetic disk or a data device through the input / output buses IOB1 and 2.

The connection of the disks D1 and 2 used as the input / output device is configured as shown in FIG. 3 through the input / output bus provided from the two input / output nodes to the disk device providing the dual port. It is configured to access using other I / O node or data path in case of a bus error.

In addition, disk mirroring also prevents data loss and recovers easily even if one disk fails.

If a faulty node occurs in the system, the user is notified of the failure. The faulty node is electrically disconnected from the system, the user can replace the board, and when a new normal board is installed, the system can be completely reconfigured to recover.

To this end, in the present invention, the board is designed to be removable in a state where power is supplied to the system.

When a defect occurs in any of the resources constituting the system while simplifying the configuration of the system so as to reduce the configuration cost by providing a parallel processing computer system and an error detection method operating in the system operating as described above. It is effective to prevent and repair faults within the range that the system does not stop and data loss does not occur.

Claims (2)

An error detection method of a processor node in a parallel processing computer system having a plurality of processing node groups consisting of two processing nodes, wherein a specific event such as an interrupt occurs or a node group is formed at an arbitrary point in time. A first step of transmitting operation results generated by an operation currently performed in each processing node and a register value of a processor to a buffer memory of a corresponding processing node of a corresponding node group through a serial communication line; A second step of receiving a register value of an operation result generated at a counterpart processing node and comparing it with its own data transmitted through the first step; A third step of determining that an error has occurred in its own node group when the data is compared in the second step, and each processing node in the corresponding node group stops its operation; A fourth step of causing another processing node group to re-perform the operation performed in the first step and then inputting the result to each processing node in the node group stopped in the third step; A fifth step in which each processing node in the node group stopped in the third step receives and compares a result of a normally performed operation received through the fourth step; And a sixth process of alerting the user of an error occurrence status as a node that has generated a different result through the fifth process is an error, and an error of the processor node and the node connection network in the parallel processing computer system. Detection method. In the parallel processing computer system having a plurality of processing node groups consisting of two processing nodes and connecting each processor node group, the error detection method of the processor node connection network in a parallel processing computer system is a dual node. A first step of determining that a corresponding network is a failure, performing a data transmission function using another connection network, and warning a user of an error occurrence status of the corresponding network, when an error continuously occurs during data transmission in a connection network being used in the connection network; A second step of selecting an arbitrary node group when it is difficult to determine which of the node interconnection networks provided through the first step is in an error state; A third step of transmitting the same data to different connection networks by two processing nodes constituting the node group selected in the above step; A fourth step in which each of the two processing nodes compares data received through a connection network other than the connection network through which the data is transmitted through the third process with data generated by the two processing nodes; And a fifth process of determining that a connection network to which different data has been received is broken when the data to be compared through the fourth process is different from each other and warning a user of an error state. Error detection method of node and node connection network.