KR100333484B1 - Fault tolerance control system with duplicated data channel by a method of concurrent writes - Google Patents

Abstract

The present invention provides a simultaneous write data channel of an active processor module performing a real-time service by duplexing a simultaneous write data channel maintaining two memory contents in a tightly coupled defect-tolerant communication control system configured in a redundant form using a simultaneous write method. The present invention relates to a redundancy apparatus that can recover even if a failure of a hardware component constituting the same occurs. The prior art associated with the present invention consists of only one simultaneous write data channel. In this case, hardware failure of the standby module, which is used as a redundancy module for the failure of an active processor module that performs real-time service work, can be overcome by replacing the module and other methods, but configuring a simultaneous write data channel of the active module. In the event of hardware component failure, the entire control system was down due to fault propagation caused by the inability to operate the data channel.

In order to solve this problem, the present invention configures a simultaneous write data channel in a redundant form, monitors each data channel for failure, and changes the simultaneous write data path to another data channel when a failure occurs in one data channel. By changing the operating mode of the module and the standby processor module, it is possible to maintain a failed processor module without bringing down the control system.

Description

Fault tolerance control system with duplicated data channel by a method of concurrent writes}

The present invention relates to a fault-tolerant control system to which the simultaneous write method is applied. Specifically, a redundant data channel and a failure detection function are provided to change a standby data channel into an active data channel when a failure occurs in each data channel. The present invention relates to a fault-tolerant control system employing a simultaneous write method having a redundant data channel that can maintain a system without disconnection.

All systems implemented by humans are always inherently susceptible to failure by designers, failures of electronic components and other causes. Such failures can cause serious problems if failures occur in fault-tolerant systems such as medical equipment, flight control systems, satellites, weapons systems, and electronic switchboards that do not allow for failure. Fault-tolerant system means a system-level non-stop system configured to operate in a predetermined order regardless of hardware failure or software error. Fault-tolerant systems are based on having redundancy modules that can back up system functionality in the event of a failure. The implementation of a fault-tolerant system depends on the number and type of redundancy added.

Electronic switchboards are systems that require high reliability and availability. For this purpose, redundant switches for critical functions are supported to support fault tolerance. Electronic switching systems can be maintained by the operator in the event of a failure, so they do not require the large amount of hardware redundancy required by medical equipment, flight control systems, satellites, and weapon systems. In general, a switching system is composed of one module performing a system function and one standby module capable of backing up the system function. This is called a duplication method.

The conventional electronic switching control system is configured in a redundant form using a simultaneous write method for maintaining memory coherence between two processor modules having a fault-tolerant function. In addition, in order to maintain memory coherence, a data channel reflecting memory contents is provided from an active processor module which performs a real-time service function to a standby processor module serving as a backup module.

1A and 1B illustrate an all-electronic switching control system having a join permission function using a conventional simultaneous write method.

FIG. 1A illustrates a redundancy control system using a simultaneous write method by extending a system bus, and FIG. 1B illustrates a redundant control system using a simultaneous write method by extending a memory bus.

In the prior art, such data channels are configured in a monolithic form. In the case of a single system configuration, if a failure of the electronic component constituting the data channel of the standby processor module occurs, the replacement of the standby processor module can be used to overcome the failure. In the event of a failure, there is no way to overcome the failure of the data channel. Therefore, data consistency between two processor modules cannot be maintained due to normal simultaneous writes. There is no way to control the entire system down is inevitable.

SUMMARY OF THE INVENTION An object of the present invention, which is designed to solve the above-mentioned problems of the prior art, is to configure two data channels for simultaneous write and to bypass the other data channel when a failure occurs in one data channel. The present invention provides a fault-tolerant control system employing a simultaneous write method with redundant data channels.

Another object of the present invention is to provide a fault-tolerant control system employing a simultaneous write method having a redundant data channel for detecting a failure of a data channel with hardware to enable fast failover.

1A and 1B are block diagrams of a fault-tolerant control system to which a conventional simultaneous write method is applied.

2A and 2B are block diagrams of a fault-tolerant control system applying a simultaneous write method having a redundant data channel according to an embodiment of the present invention.

3 is a detailed block diagram of a failure detecting apparatus;

4 is a detailed block diagram of a channel control apparatus for dual data channel control

Preferred embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

2A is a block diagram of a fault-tolerant control system applying a simultaneous write method having a redundant data channel according to an embodiment of the present invention, in which a system bus is extended to configure a redundant data channel.

As shown in the figure, the fault-tolerant control system of this embodiment consists of an active processor module and a standby processor module, wherein the active / standby processor module comprises: CPUs 10 and 11 which generally control the system as a whole; Input / output devices 20 and 21 for providing input and output of data to the system; Memory (30, 31) for storing a program, operation state information and data necessary for the operation of the system; An active data channel 40, 41 forming a data channel for simultaneous writing, said CPU 10, 11, input / output devices 20, 21, memories 30, 31 and data channels 40, 41; ) Is a fault-tolerant control system using a simultaneous write method of transmitting and receiving data through a system bus.

Failure detection and channel control for detecting a failure of the standby data channels 50 and 51 and the active / standby data channels 50 and 51 and controlling the channel when a failure occurs in the active data channels 40 and 41. Device 60, 61, and all of the data channels 40, 41, 50, 51 are interconnected via a system bus.

In such a configuration, the active data channel 40 of the active processor module functions similar to the data channel used in the prior art, and operates as a data channel for maintaining data consistency between the active and standby processor modules. The standby data channel 50 is a redundancy data channel to replace the standby data channel 50 when a failure of the active data channel is detected by the device for detecting a failure and the channel control device loses its function as a data channel.

When the failure detection and channel control devices 60 and 61 detect a failure of the data channels 40, 41, 50, and 51, the failure detection and channel control devices 60 and 61 control to perform simultaneous writing through other data channels.

Accordingly, when a failure occurs in the active data channel 40 of the active processor module, the failure detection and channel control device 60 detects this and performs channel control to the standby data channel 50 so that subsequent simultaneous writes are performed by the standby data channel ( 50).

The same is true for the standby processor module.

FIG. 2B is a block diagram of a fault-tolerant control system applying a simultaneous write method having a redundant data channel according to another embodiment of the present invention, in which a redundant data channel is extended by extending a memory and a memory controller.

As shown in the figure, the fault-tolerant control system of this embodiment is comprised of an active processor module and a standby processor module, wherein the active / standby processor each includes a CPU (110, 111) for overall control of the system; Input and output devices 120 and 121 for providing input and output of data to the system; Memory (130, 131) for storing a program, operation state information and data necessary for the operation of the system; Memory controllers 140 and 141 which control the active memory switches 150 and 151 during the simultaneous write operation to maintain data consistency; And active memory switches 150 and 151 controlled by the memory controller 140 to form a data channel, wherein the CPUs 110 and 111, the input / output devices 120 and 121, and the memory controllers 140 and 141. ) Transmits data through the intersystem bus, and the memory controllers 140 and 141, the active memory switches 150 and 151 and the memories 130 and 131 transmit a data through the mutual memory bus. In the applied fault tolerance control system, standby memory switches 160 and 161 and simultaneous active / standby memory switches 160 and 161 for simultaneous writing when a data channel is formed by the active memory switches 150 and 151 are generated. It is configured to include a failure detection and channel control device (170, 171) for detecting a failure of the data channel formed by the control channel and the standby memory switches (150, 151, 160, 161) It is constructed by interconnecting each other.

As in FIG. 2A, the data channel formed between the active memory switches 150 and 151 has a function similar to that of the data channel formed between the memory switches used in the prior art, and is used to maintain data consistency between the active and standby processor modules. Act as a channel In addition, the data channel formed between the standby memory switches 160 and 161 has failed due to a failure of the active memory switches 150 and 151 by the failure detection and channel control devices 170 and 171, and thus has lost its function as a data channel. If detected, it is a redundancy data channel to replace it.

In the above embodiments, the failure detection and channel control device detects and collects a failure of a data channel and reports it to the CPU, and determines an operation mode of two data channels during power-up and initial operation. It consists of a channel control function that controls switching and other operations.

Each data channel is not connected point-to-point, but each channel is connected to each other in a bus form. When connected in a point-to-point, a data channel failure of one processor module may not be used even if a failure does not occur with respect to the same data channel of the other processor module. That is, in the two processor modules, if one A data channel fails and the other B data channel fails, the entire data channel cannot be connected. In the present invention, each data channel is connected in the form of a bus to solve this problem. To connect in the form of a bus, the data channel is basically configured in the form of Wired-OR.

FIG. 3 relates to a failure detecting apparatus for performing a failure detecting function in the failure detecting and channel control apparatus of FIGS. 2A and 2B.

As shown in the figure, the failure detecting apparatus includes: a test pattern generator 210 generating a test pattern generated by a protocol prescribed between two processes for checking whether a failure occurs on a path of a data channel; A data channel controller 220 for controlling the data channel during the idle period of the data channel and passing the test pattern generated by the test pattern generator 210; A test pattern delay unit 230 for delaying a test pattern for a time required by the data channel; And a self-side pattern checker 232 for detecting a failure of electronic devices constituting its own data channel, and a data pattern received from the counterpart processor module by checking the data pattern received from the counterpart processor module. It consists of a pattern inspection unit 240 consisting of a data channel pattern inspection unit 242 for monitoring the presence of a failure.

Here, the test pattern generator 210 performs a function of generating a test pattern generated by a protocol prescribed between two processes for checking whether a failure occurs on a path of a data channel. The protocol used in the present invention uses the PN 127 code commonly used in communication devices. The PN127 code refers to a code generated by arranging a number from 0 to 127 in an infinite permutation. The PN127 code is used in the test pattern generator.

The test pattern according to the PN127 code generated by the test pattern generator 210 is transmitted to the data channel controller 220 and the test pattern delay unit 230. The data channel controller 220 controls the data channel during the idle period of the data channel to pass a test pattern for detecting whether the data channel is a failure.

The test pattern delay unit 230 delays the test pattern for a delay time occurring in a series of operations occurring in the data channel controller 220 to maintain data consistency from the active processor module to the standby processor module. . If the test pattern is examined without delay with the test pattern through the data channel, it is assumed that a failure has always occurred due to data inconsistency due to a pattern check of different delay times, and thus normal operation is impossible.

The test pattern delay unit 230 may be easily implemented using a general shift register. The test pattern is delayed for the time required by the data channel while passing through the test pattern delay unit 230. For example, if five clock delays occur in the data channel, the test pattern delay unit 230 also delays five clocks to maintain the same delay time. The delay pattern passed through the test pattern delay unit 230 and the channel output pattern through the data channel are transmitted to the self side pattern inspector 241 and the data channel pattern inspector 242, respectively. The self-side pattern checker 241 detects the occurrence of a failure of the electronic devices forming its data channel.

The channel output pattern and the delay pattern received by the own processor module are checked by the self-side pattern checker 241 with the same pattern. If the patterns are different from each other, the self-side pattern monitoring unit 241 enables the self-failure detection signal to notify the CPU that an abnormality has occurred in its data channel.

The data channel pattern checker 242 inspects a test pattern received from the counterpart processor module and monitors a failure on a data channel between two processor modules connected to the backboard. The data channel pattern checker 242 checks whether there is an identical pattern between another channel output pattern and another delay pattern of the counterpart board received through the backboard. If the patterns differ from each other, enable the data channel failure detection signal to notify the CPU that a failure has occurred on the data channel.

This data channel failure detection signal not only informs the own CPU but also the CPU of the counterpart processor module. If the self failure detection signal and the data channel failure detection signal are received at the same time, a failure occurs in its own data channel. If only the data channel failure detection signal is received, a failure occurs in the data channel of the other processor module. These channel failure detection signals are transmitted to the failure detection and channel control device of the channel control device so that data channel switching is performed.

The failure detection device is composed of two identical devices for monitoring two data channels, respectively, and is configured to monitor each data channel.

4 is a channel control apparatus for managing a data channel in a failure detection and channel control apparatus.

The channel control apparatus detects the presence or absence of a failure of the data channel in the above-described failure detecting apparatus and notifies it of the failure, and performs the function of managing the data channel according to the state. In addition, the channel controller performs a function of determining which of two data channels is set as an active channel for data consistency between two processor modules at initial power-up and booting.

The channel control apparatus for performing such a function includes, as shown in the drawing, a failure occurrence notification unit 310 for notifying the CPU and the channel controller 320 of the occurrence of a failure based on an input signal in the failure detection apparatus; A channel state collecting unit 330 for checking a state of the data channel and determining a state of the data channel in order to set each data channel as an active and standby data channel during initial power-up and operation; Including a channel controller 320 for controlling the data channel based on the signal input from the failure occurrence notification unit 310, the channel state collecting unit 330 and the channel switching / connection information of the internal register 340 of the system; It is composed.

The channel control apparatus having such a configuration receives a data channel failure detection signal and a self failure detection signal, which are data channel failure occurrence status signals received from the failure detection device, to notify the CPU of a failure of the data channel of the corresponding processor module.

When the data channel fault detection signal level is received as H and the self fault detection signal is detected as L, it recognizes that its data channel is now normal and that a failure has occurred in the data channel of the opposite processor module. On the contrary, if the signal level of the data channel failure detection is L and the signal level of the self failure detection is detected as H, the own data channel is normal, but the data channel of the opposite processor module is recognized as a failure.

Here, the data channel failure detection signal and the self failure detection signal are composed of A data channel failure detection, B data channel failure detection, A Ch self failure detection, and B Ch self failure detection, respectively, in order to recognize the state of the two data channels.

In addition, the failure occurrence notification unit 310 is a Self A Ch Err, Self B Ch Err, Other A Ch Err, Other B Ch Err in order to notify the channel controller 320 of the corresponding data channel having a failure according to the above process Enable the signal level of H as appropriate. The signals generated at this time are stored in the internal register 340 to notify the host management program of the channel status through the CPU.

In addition, when the failure occurrence notification unit 310 recognizes that a failure has occurred in the data channel through the above process, the failure signal level is enabled by H to indicate that a failure has occurred on the data channel currently connected between the two processor modules. The CPU 350 informs the CPU. The signal used at this time is an interrupt signal and the signal level is active high. The interrupt signal is generated by collecting all interrupt sources that may occur in the processor module in addition to the fault detection signal related to the data channel failure. This interrupt processing is the same as the interrupt processing method of the general processor module, the interrupt handler 350 used in the present invention also uses a commercial interrupt handler used in the general processor module.

The channel controller 320 manages and controls the state of the data channel according to the presence of a failure or the initial operation mode setting. The channel controller 320 notifies the CPU through the interrupt handler 350 when receiving the failure status signals of its own and counterpart channels received from the failure occurrence notification unit 310, and considers the CPU to receive the interrupt as a higher-level management program. As the corresponding bit to be transferred through the internal register 340 is set, it waits until the signal level of the signal channel switching becomes H. If you do not switch channels in this way, but only by hardware alone, there is a possibility of random switching of channels due to instantaneous instability of the hardware signals-noise, jitter, glitch, instantaneous power supply instability. While performing work for data consistency from the active processor module to the standby processor module through the data channel, the channel may be switched to cause a momentary failure in the standby processor module. In order to solve this problem in the present invention, the data channel is switched by the above procedure.

The channel state collecting unit 330 performs a function of checking a state of a data channel to set each data channel as an active and standby data channel during initial power-up and operation. The channel state collecting unit 330 receives Other A Ch On and Other B Ch On signals, which are status signals of each channel, received from the opposite processor module, and receives the A Ch Self failure detection and the B Ch Self received from the failure detection device. The failure detection signal is received to detect the state of each data channel to find a connectable channel.

The priority method used to find a connectable channel among two data channels at initial power-up. The priority method is a method of giving priority to each source in the order in which they can be executed. In the present invention, the A data channel always has priority over the B data channel. That is, if a failure does not occur in the A data channel, the A data channel is always connected to the counterpart data channel. The channel state collecting unit 330 uses Self A Ch On and Self B Ch On to inform which channel of its data channel to activate and wait. If the current A data channel is active, change the signal level of Self A Ch On to H. If you activate the B data channel, change the signal level of Self B Ch On to H. In addition, in order to activate its own data channel, the channel controller 320 enables the A Ch Con and B Ch Con signals of each channel connection signal.

The channel controller 320 receiving the A Ch Con and B Ch Con signals solves this problem because the channel controller 320 may affect the other processor module when the data channel is connected before the processor module is normalized and the data channel is connected. To do this, the data channel is not connected until the processor module receives a channel connection signal indicating that the processor module has normalized. When the signal level of channel connection is received as H and the A Ch Con signal level is received as H, the signal level is changed from A Ch On, the A data channel connection signal, to H. If the B Ch Con signal level is received as H, the B data is received. Change the signal level of B Ch On, the channel link signal, to H.

If the channel controller 320 receives A Ch Con and B Ch Con simultaneously from the channel operation mode determiner, this means enabling both data channels, which means that there is a problem in the channel determination process. In this case, the channel controller 320 notifies the failure occurrence notifying unit 310 that there is a problem in the channel determination process by changing the signal level of the channel determination failure signal to H. The failure occurrence notification unit 310 notifies this to the CPU through the interrupt processor 350 in the form of an interrupt through the failure detection signal.

In addition, the channel controller 320 transmits a channel determination failure signal to the internal register 340. The internal register 340 stores a cause and state of a failure of a channel and provides the CPU with relevant information. The internal register 340 stores a channel determination failure signal, a failure detection signal of each channel, and channel information. The channel information [1: 0] received from the channel state collecting unit 330 indicates a channel currently connected between two processor modules. Channel information [1] means its own data channel and channel information [0] means its counterpart data channel. In this case, when the bit value of the channel information [1: 0] is 0, it means an A data channel, and vice versa, it means a B data channel. For example, if the value of the channel information [1: 0] is 00, it indicates that the two processor modules are connected to the A data channel.

The present invention is to solve the problem of data channel disconnection caused by failure and failure of one data channel by using a redundant data channel. Wired-OR is used to solve the data channel disconnection even in the case of failure of different data channels. It was configured in the form of bus used. In addition, we devised a method to identify the failure and failure of the data channel, and devised a method to overcome it when a failure occurs. The present invention is not limited to the switching control system, but can be applied to a control system having all the fault-tolerant functions applying the simultaneous write method, and many other defect-tolerant control systems requiring high reliability and availability at low cost. Applicable to the field.

As described above, the present invention is a data channel of an active processor module which has been pointed out as a structural problem in a fault-tolerant control system applying a conventional simultaneous write method by constructing a fault-tolerant control system applying a simultaneous write method having a redundant data channel. The problem of data channel disconnection due to failures and failures can be solved. In addition, the present invention can solve the data channel disconnection phenomenon in the case of failure of different data channels of the active / standby processor module by configuring the redundant data channel in the form of a bus using Wired-OR.

In addition, since hardware detects the presence or absence of a data channel, it is possible to quickly overcome the failure.

The present invention is not limited to the switching control system, but can be applied to a control system having all the fault-tolerant functions applying the simultaneous write method, and also constitutes a fault-tolerant control system having an expensive fault-tolerant function at a low cost. It is possible to improve reliability at low cost to HA (High Availability) designed in consideration of high availability, and it is a control system that can be applied to communication terminal devices such as TA (Terminal Adapter) to guarantee high reliability. Implementation is possible.

In addition, it can be applied to and implemented in systems that can be operated without system down by granting fault-tolerance functions to PC servers and workstation servers that are currently used a lot. It will continue to be applicable to many systems that require fault-tolerant system functionality at low cost.

Although the technical spirit of the present invention has been described above with reference to the accompanying drawings, this is intended to describe exemplary embodiments of the present invention by way of example and not to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

Claims (10)

It consists of an active processor module and a standby processor module, the active / standby processor module is a CPU (10, 11) for overall control of the system, input and output devices (20, 21) for providing input and output of data to the system, Memory 30 and 31 for storing programs, operation state information and data necessary for the operation of the system, and active data channels 40 and 41 for forming data channels for simultaneous writing. 11), the input and output devices 20 and 21, the memory 30 and 31, and the data channels 40 and 41 are in a fault-tolerant control system applying a simultaneous write method of transmitting and receiving data through a system bus, Fault-tolerant control using a simultaneous write method having a redundant data channel, comprising standby data channels 50 and 51 for simultaneous writing when a defect occurs in the data channel formed by the active data channels 40 and 41. system. The method of claim 1, And the active / standby data channels (40, 41, 50, 51) are configured in the form of a bus using Wired-OR. The method of claim 1, Redundancy characterized in that it comprises a failure detection and channel control device (60, 61) for detecting a failure of the data channel formed by the active / standby data channel (40, 41, 50, 51), and control the channel Fault-tolerant control system adopting a simultaneous write method with a data channel. The method of claim 3, The fault detection and channel control device (60, 61), A test pattern generator 210 for generating a test pattern generated by a protocol regulated between two processes for checking whether a failure occurs in a path of a data channel; A data channel controller 220 for controlling the data channel during the idle period of the data channel and passing the test pattern generated by the test pattern generator 210; A test pattern delay unit 230 for delaying a test pattern for a time required by the data channel; And Self-side pattern check unit 232 for detecting the occurrence of failure of the electronic devices constituting its own data channel, and checks the data pattern received from the other processor module failure on the data channel between the two processor modules connected to the back board The pattern checker 240 is configured to include a data channel pattern checker 242 for monitoring the presence and absence of a duplicate data channel, characterized in that it comprises a fault detection device for detecting the presence or absence of a data channel failure. Fault Tolerance Control System. The method according to claim 3 or 4, The fault detection and channel control device (60, 61), A failure occurrence notifying unit 310 which notifies the CPU and the channel controller 320 of a failure occurrence based on the failure detection input signal; A channel state collecting unit 330 for checking a state of the data channel and determining a state of the data channel in order to set each data channel as an active and standby data channel during initial power-up and operation; And And a channel controller 320 for controlling a data channel based on a signal input from the failure occurrence notification unit 310 and a channel state collecting unit 330 and channel switching / connection information of an internal register of the system. And a channel control device for controlling a data channel. It consists of an active processor module and a standby processor module, the active / standby processor is a CPU (110, 111) for controlling the overall system, the input and output devices (120, 121) for providing data input and output to the system, and the system Memory 130 and 131 for storing programs, operation state information, and data necessary for the operation of the memory controller 140, and a memory controller 140 for controlling the active memory switches 150 and 151 during simultaneous writing to maintain data consistency. 141 and active memory switches 150 and 151 controlled by the memory controller 140 to form a data channel, the CPU 110 and 111, input / output devices 120 and 121 and a memory controller ( 140 and 141 transmit data through a mutual system bus, and the memory controllers 140 and 141, active memory switches 150 and 151, and memories 130 and 131 transmit data through a mutual memory bus. In applying the on-write scheme, fault-tolerant control system, Fault-tolerant control using a simultaneous write method having a redundant data channel, comprising: standby memory switches 160 and 161 for simultaneous writing when a defect occurs in a data channel formed through the active memory switches 150 and 151. system. The method of claim 6, The active / standby memory switches (150, 151, 160, 161) is configured in the form of a bus using a wired-OR, fault-tolerant control system applying a simultaneous write method having a redundant data channel. The method of claim 6, Simultaneous detection of a failure of a data channel formed through the active / standby memory switch (160, 161) and a failure detection and channel control device (170, 171) for controlling the channel at the same time Fault-tolerant control system with write method. The method of claim 8, The failure detection and channel control device (170, 171), A test pattern generator 210 for generating a test pattern generated by a protocol regulated between two processes for checking whether a failure occurs in a path of a data channel; A data channel controller 220 for controlling the data channel during the idle period of the data channel and passing the test pattern generated by the test pattern generator 210; A test pattern delay unit 230 for delaying a test pattern for a time required by the data channel; And Self-side pattern check unit 232 for detecting the occurrence of failure of the electronic devices constituting its own data channel, and checks the data pattern received from the other processor module failure on the data channel between the two processor modules connected to the back board The pattern checker 240 is configured to include a data channel pattern checker 242 for monitoring the presence and absence of a duplicate data channel, characterized in that it comprises a fault detection device for detecting the presence or absence of a data channel failure. Fault Tolerance Control System. The method according to claim 8 or 9, The failure detection and channel control device (170, 171), A failure occurrence notifying unit 310 which notifies the CPU and the channel controller 320 of a failure occurrence based on the failure detection input signal; A channel state collecting unit 330 for checking a state of the data channel and determining a state of the data channel in order to set each data channel as an active and standby data channel during initial power-up and operation; And And a channel controller 320 for controlling a data channel based on a signal input from the failure occurrence notification unit 310 and a channel state collecting unit 330 and channel switching / connection information of an internal register of the system. 18. A fault-tolerant control system employing a simultaneous write method with a redundant data channel, comprising a channel control device for controlling a data channel.