KR100523356B1 - A Clock Synchronization Apparatus with a Time Division - Google Patents

Abstract

The present invention relates to a clock synchronizing apparatus using a time division method for providing a clock synchronization function between two modules using a time division method in a fault-tolerant system configured in a redundant form of an active module and a standby module.

To this end, the present invention is a clock synchronization device by a time division method for providing clock synchronization in a control system having a fault-tolerant function consisting of redundancy of an active module and a standby module. An operation mode determining unit which switches to the standby mode when the other party is in the active mode and changes to the active mode when the other party is the standby mode; A clock multiplexer configured to output one of clocks transmitted from the two modules to a source clock according to an operation mode signal of the operation mode determiner; A clock difference generator for generating a divided clock for time division of the output source clock; A count start driver configured to generate a count start signal for determining a time point at which the source clock is time-divided using the division clock; A time division coefficient unit for time division of the source clock within one clock of the source clock and generating a time division period of the source clock by the count start signal; A time division determining unit configured to determine whether to time division and determine a degree of phase shift of the source clock by the time division period; And a clock phase shifter configured to generate a phase shift sync clock for the source clock using the time division period generated by the time division coefficient unit and the phase shift signal determined by the time division determiner.

According to the present invention, the parts are minimized to reduce the error occurrence rate, the digital logic is configured to reduce the malfunction caused by external environmental elements, and the failure recovery time can be reduced when a failure occurs. In addition, clock phase shift is possible, and the active / standby switching time can be reduced.

Description

A Clock Synchronization Apparatus with a Time Division}

The present invention relates to a clock synchronizing apparatus using a time division method, and more particularly, using a time division method for providing a clock synchronizing function between two modules using a time division method in a fault-tolerant system configured in a redundant form of an active module and a standby module. A clock synchronizer.

Today, there is an increasing demand for ultra-fast information processing throughout the industry, and the need for fault-tolerant systems that require high reliability and high availability is increasing rapidly. In the field of high-speed information and communication, it is very important to design the system to have high reliability that can operate regardless of a failure. As described above, a function of performing system operations in a predetermined order regardless of a failure that may occur in a system is called a fault tolerant function.

In general computer applications, when a failure occurs, in most cases it detects and suspends the system operation, performs the necessary recovery operation, and restarts the system. However, if this method is applied to an exchange control system, the endless call requests and call execution will be interrupted, causing extreme confusion for the users of the high-speed network, so that the exchange control system will continue without stopping any possible system operation even if it detects a failure. You must perform a failover operation while maintaining it.

The fault-tolerant system implemented in a redundant structure by applying a fault-tolerant concept may be used to inherit an active module that performs a function and a failure of the active module and no longer perform a system function. It consists of a standby module. In this case, the standby module is called redundancy, and the time for the system function inheritance is called the transfer time. Some of the communication protocols require a short transition time of around 50ms, so a redundant fault-tolerant system is a critical design element to provide less than that to meet these requirements. The key technique used for switching and synchronizing between two modules is clock synchronization, and if it consumes a lot of time for clock synchronization, it is impossible to satisfy the switching time required by the network. Therefore, minimizing clock synchronization and switching time becomes an important factor to ensure short switching time.

Conventional techniques related to clock synchronization are mostly VCO, PLL with analog device characteristics such as charge pump for accurate clock synchronization, and jitter attenuation circuit to solve jitter problem when changing clock source. It consists of a clock source selection circuit for clock source selection, an RF selection circuit for selecting a clock received through a jitter attenuator, an input reference clock selection circuit, and many other analog circuits. These conventional clock synchronizing devices have a problem in that the application of the clock synchronizing device is inadequate for a control system having a fault-tolerant function for performing a fault recovery operation while performing a real time service due to a high circuit failure rate and a long clock synchronizing time. . In addition, the application of analog devices rather than the concept of digital logic is complicated to overcome the failure, there is a problem that requires a long clock synchronization time by the PLL. In practice, the synchronizer clock circuit of an all-electronic exchange having such a structure requires a clock synchronizing time of about 30 minutes in many cases upon initial power-up.

In particular, in a system having a conventional fault-tolerant function, the failure rate due to the hardware and software design is high due to the complicated structure, and the failure rate is high, and the exchange cost is increased due to the development cost increase due to the use of many hardware components and the long development period. The application was inadequate for commercial applications with fault tolerance features that require real-time services such as control systems. In addition, analog devices have often been malfunctioned by external environmental factors such as ambient temperature and PCB materials rather than by logic.

Accordingly, there has been a need in the art for a clock synchronizer that minimizes clock synchronization time, uses minimal components, and simplifies the failure operation to lower the failure rate.

The present invention has been proposed to solve the above problems, in the implementation of a clock synchronization device that provides a synchronization function between the two modules in a system having a fault-tolerant function configured in a redundant form of the active module and the standby module, the input clock Time division by dividing by a certain ratio and then shifting the clock to the left and right along the time axis, eliminating analog characteristics, minimizing the parts used to reduce the failure rate, minimizing clock synchronization time An object of the present invention is to provide a clock synchronizer using a time division method that provides its own clock recovery function and clock phase shifting function.

In order to achieve the above object, the present invention provides a clock synchronization device using a time division method for providing clock synchronization in a control system having a fault-tolerant function consisting of redundancy of an active module and a standby module. An operation mode determination unit to switch to the standby mode when the counterpart is in the active mode, and to switch to the active mode when the counterpart is in the standby mode; A clock multiplexer configured to output one of clocks transmitted from the two modules to a source clock according to an operation mode signal of the operation mode determiner; A clock difference generator for generating a divided clock for time division of the output source clock; A count start driver configured to generate a count start signal for determining a time point at which the source clock is time-divided using the division clock; A time division coefficient unit for time division of the source clock within one clock of the source clock and generating a time division period of the source clock by the count start signal; A time division determining unit configured to determine whether to time division and determine a degree of phase shift of the source clock by the time division period; And a clock phase shifter for generating a phase shift sync clock for the source clock using the time division period generated by the time division coefficient unit and the phase shift signal determined by the time division determination unit.

Further, the clock synchronizing apparatus may further include a clock distributing unit distributing the phase shift synchronizing clocks output from the clock phase shifting unit to n system clocks having the same phase. Preferably, the clock distributor is comprised of a clock tree.

In addition, the clock multiplexer recognizes the active mode when the operation mode signal input from the operation mode determiner is 'high' and outputs its clock to the source clock. When the clock multiplexer is 'low', the clock multiplexer enters the standby mode. It recognizes and outputs the clock of the other party as the source clock.

The clock difference divider generates a divided clock having a frequency n times that of the source clock when the source clock is divided into n time division sections.

In addition, the counting start driver receives the clock synchronization re-execution signal according to a signal level or a source clock change in which the system initialization is not valid, and when the rising time of the source clock is sensed, the counting start driving the time division coefficient unit is performed. Generate a signal.

The time division coefficient unit time-divisions the source clock while forming an endless loop of one period of the source clock by a set value.

The present invention relates to an apparatus for providing a clock synchronization function between an active module and a standby module in a tightly coupled defect tolerance system configured in a redundant form, and more particularly, to a clock synchronization apparatus using a time division method.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail the present invention.

1 shows a schematic diagram of a fault-tolerant system composed of redundancy to which the present invention is applied. The fault-tolerant system shown in FIG. 1 is an example to which the present invention is applied, and the present invention can be applied to an exchange control system or the like requiring clock synchronization. As shown in FIG. 1, a fault-tolerant system is redundant with an active processor module 110 and a standby processor module 120, each processor module controlling the overall operation of the module and storing the control data and the main processor. Memory devices 111 and 121, input / output devices 112 and 122 for inputting and outputting data, and redundancy control devices 113 and 123 for redundancy. The redundancy control devices 113 and 123 include simultaneous write devices 114 and 124 for memory matching between the two processor modules 110 and 120, and clock synchronizers 115 and 125 for providing clock synchronization between each module. The defect tolerance system shown in the figure is configured in a redundant form by a simultaneous write method. Here, the simultaneous write is a method of maintaining data consistency between the two processor modules 110 and 120 by reflecting the memory write operation of the active processor module 110 to the memory of the standby processor module 120. When two active modules maintain data consistency by the simultaneous writing, the system processor of the active processor module 110 is transferred to the standby processor module 120 to overcome the failure of the active processor module 110. Restart The standby processor module 120 that inherits the system function re-initializes its own device, and then changes its duplex operation mode to an active mode so that the service can be continuously performed. The process of allowing the standby processor module 120 to succeed the system function and perform the disaster recovery process and then continuously perform the service is referred to as 'switching'. The transfer time of the ATM exchanger using this method is approximately 10 ms or less, which satisfies the 50 ms or less required by the above-described communication protocol, and thus can be applied to communication devices other than the exchange.

The most important function in the fault tolerance system structure shown in FIG. 1 is the clock synchronization function between two modules. In addition to this structure, clock synchronization is the most important requirement even in hot standby, in which two modules always perform the same operation. Conventional clock synchronization devices are not only time consuming to synchronize, but additional analog devices are more prone to failure and the method of detecting them is very complex. The present invention solves this problem by configuring each device with digital logic, and proposes a time division method capable of terminating the synchronization process after the clock switching at a switching time of 1 to 2 clocks-several to several tens ns or less. In addition, the time-division method devised in the present invention minimizes the circuit change due to the change of the apparatus by compensating the propagation delay time through the PCB pattern.

The clock synchronizer 115 generates a clock source, receives the generated clock source, generates a synchronized clock, and generates as many clocks as necessary for the processor module 110 by using the generated clock. To distribute. The processor module 110 basically provides a clock suitable for the processor and the main memory device 111 and the input / output device 112 including a plurality of peripheral controllers, and these clocks are duty required by the processor module 110. It provides a clock that meets duty cycle and electrical requirements. In the present invention, the clock generated by the processor module 110 is used without further implementing a function for generating such a clock. For this purpose, an existing clock generation circuit existing in the processor module 110 is used.

In addition, a control system having a fault-tolerant function is divided into an active processor module 110 and a standby processor module 120 according to whether a system function is performed. An operation for determining such an operation mode is called an operation mode negotiation. In the clock synchronizing device 115, two clock lines received from the two processor modules through the backboard (to compensate for the propagation delay time occurring in the clock line) from the two processor modules according to the operation mode determined by the operation mode negotiation Must have the same length and width) After generating the synchronous clock by differently selecting the clock source received, the synchronous clock is distributed.

The synchronous clock distribution is to generate as many clocks as necessary for the controllers and devices provided by the processor module 110 by using the generated synchronous clocks. In order to match the phase of the clock signals, the clock tree is divided and distributed. The clock synchronizer 115 using the time division method according to the present invention will be described in more detail with reference to FIG. 2.

2 is a block diagram illustrating a clock synchronization device in a fault-tolerant system to which the time division method according to the present invention is applied. Hereinafter, for convenience of description, the clock synchronizer 115 in the fault-tolerant system using the time division method according to the present invention will be referred to as a 'time division clock synchronizer'. As shown in FIG. 2, the time division clock synchronizer includes a clock multiplexer 210 (hereinafter referred to as Mux) and a processor 111 provided to select a clock source for synchronizing clocks between two processor modules 110 and 120. The operation mode determination unit 220 for controlling the clock Mux 210 according to the duplex operation mode by the control unit, and the time division determination unit 230 for determining whether to time-division and determining a phase shift time-division value of the 'source clock' based on the time division value. A clock phase shifter 240 for shifting a clock phase by a value determined by the time division determiner 230, and a clock difference generator for generating a clock for time division of a clock selected from the clock mux 210; 250), a time division counting unit 270 for time division of a clock within one clock of the source clock, and a time division counting unit 270 for generating a signal for counting accurately from the rise time of the source clock. The clock start unit 280 and the clock phase shifter 240 are provided with a clock distribution unit 260 that receives the phase shift clock and distributes to n system clocks.

The clock mux 210 receives both of its own clock and its relative clock, which are clocks of different phases, from the two process modules 110 and 120. When the binding allowance system implemented by redundancy starts, the states of the counterparts are checked from each other in the initial state, and when the counterpart is in the active mode, the user is transferred to the standby mode. That is, in the redundant fault-tolerant system, an active mode for performing a system function of its own state or a standby mode for system function backup using information determined by an operation negotiation process for determining whether the system function is performed. Decide on The information determined through this process is used as a selection signal of the clock Mux 210 for clock synchronization. In this case, the determined information is used as a selection signal of the clock Mux 210 by a control signal of the processor 111 (eg, an address, data, and bus control signal).

When the value received from the operation mode determiner 220 is 'H', the clock mux 110 outputs a 'own clock' as a source clock by considering it as an active mode and outputs the source clock from the operation mode determiner 220. When the received value is 'L', it is regarded as a standby mode and outputs a 'relative clock' as a source clock. The output source clock is input to the clock phase shifter 240 and the clock difference unit 250. First, the clock difference unit 250 receives the source clock as an input and makes a 'division clock' for time division. If, for example, to divide the source clock into four time division intervals, the divided clock has a frequency four times that of the source clock. The clock difference unit 250 may be simply implemented by using a commercial clock multiplier. In this case, since the set time division section is a section used for phase adjustment by the propagation delay described above, the time division section may be cut into a shorter section for precise control. In the present invention, a time division section is divided into 16 as an example, and a divided clock having a frequency of 16 times is generated.

The divided clock for generating the time division section of the source clock generated by the clock difference unit 250 is input to the time division coefficient unit 270 and the count start driver 280. The count start driver 280 determines a time division time point of the source clock. Meanwhile, the coefficient start driver 280 receives a signal for validating system initialization and a clock resynchronization signal. At this time, the coefficient start driver 280 receives a 'L' signal that is a signal level indicating that system initialization is not valid or receives a 'clock resynchronization' signal for performing a clock synchronization process according to the clock source change. When the rising time of the 'source clock' is sensed, a 'counting start' signal for driving the time division coefficient unit 270 is generated. The time division counter 270 which receives the calculation start signal output from the count start driver 280 time-divisions one cycle of the source clock while forming an infinite loop by a predetermined value. In the example of the present invention, since the source clock is time-divided into 16 sections, the time division coefficient unit 270 includes a 4-bit counter. The coefficient value generated by the time division coefficient unit 270 is input to the clock phase shifter 240 as a 'time division period' value.

Meanwhile, the time division determiner 230 performs a function for determining the degree of phase shift of the source clock using the 'time division period' value determined by the time division coefficient unit 270. The 'phase shift' signal output from the time division determiner 230 is configured as a bus for displaying the number of time divisions, and is configured as 4 bits in the present invention. When the time division determiner 230 receives the 'initialization' signal, the clock phase shifter 240 outputs the value of the 'phase shift' signal to '0' so that the clock phase shifter 240 converts the 'source clock' to the 'phase shift synchronous clock'. By outputting 'to avoid phase shift. The time division determining unit 230 also determines the output using the 'control signal' by the processor 111. The clock phase shifter 240 decodes the 'time division period' and the 'phase shift' signals received from the time division coefficient unit 270 and the time division determination unit 230 and has a same time division time point. To generate a clock signal having a 50:50 duty cycle. The clock generated at this time is a 'phase shift synchronization clock' and is a synchronization clock between two processor modules 110 and 120 that compensates for propagation delay time caused by various causes. The 'phase shift synchronous clock' output from the clock phase shifter 240 is input to the clock divider 260 formed of a clock tree, and the 'phase shift synchronized clock' is input to the clock divider 260. The phase shift synchronizing clock is generated as n system clocks having the same phase with each other through the clock tree.

3 is a timing diagram of a clock synchronizing apparatus according to a time division method according to the present invention. 3 shows, as an example, a timing diagram when the number of time division slots to be phase shifted in the time division clock synchronizing apparatus according to the present invention is two. At this time, since the final output terminal of the clock phase shifter 240 is a distributed flat fiber (DFF) to generate a clock stable clock, even if the number of time division slots to be moved is two, the 'phase shift' value is '1'. Should be set to '. If there is no phase shift, the 'phase shift' value is set to 'F'. As shown in FIG. 3, in the example of the present invention, the 'division clock' has a frequency 16 times that of the 'source clock' in order to make the 'source clock' into 16 time division sections. That is, in FIG. 3, the divided clock is 16 cycles with respect to one cycle of the source clock. When the value of 'phase shift' is 1, the source clock is output as a phase shift clock and phase shifted.

4 is a diagram illustrating an internal configuration of the clock tree of the clock divider in the clock synchronizing apparatus according to the time division method according to the present invention. As shown in FIG. 4, when configuring the clock tree of the clock distributor 260, the number of signals that one clock drive 261 can drive is preferably 8 to solve the pan-out problem. Restrict to dogs.

Although the detailed description and drawings of the present invention disclose a clock synchronizing apparatus in a fault-tolerant system configured with redundancy, the time division clock synchronizing apparatus of the present invention can be applied to various fields to which clock synchronizing is applied. The above-described defect tolerance system is merely a preferable example for explaining the present invention and does not limit the scope of the present invention. In addition, since the other examples described in the above detailed description are for explaining the present invention, those skilled in the art will readily understand that the above-described examples may be substituted, changed or modified.

Accordingly, the scope of the present invention should be determined by the appended claims rather than by the foregoing description.

Application of the clock synchronizing apparatus using the time division method according to the present invention has the following effects.

First, the error rate can be reduced by minimizing the parts used in hardware and software design.

Second, since it can be configured with digital logic, it can reduce malfunctions caused by external environmental factors such as ambient temperature and PCB materials, and reduce the recovery time of failures compared to conventional clock synchronizers composed of analog devices. have.

Third, clock phase shift is possible.

Fourth, when a failure occurs in the active processor module, the transfer time for switching the standby processor module to the active mode can be reduced.

The above detailed description and contents disclosed in the drawings are not intended to limit the present invention, and it is apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit of the present invention. will be.

1 is a configuration diagram of a fault-tolerant system composed of redundancy to which the present invention is applied.

2 is a block diagram of a clock synchronizing apparatus using a time division method according to the present invention.

3 is a timing diagram of a clock synchronizing apparatus according to a time division method according to the present invention.

4 is a diagram illustrating an internal configuration of the clock tree of the clock divider in the clock synchronizing apparatus according to the time division method according to the present invention.

 Explanation of symbols on the main parts of the drawings

110: active processor module 120: standby processor module

111,121: processor and main memory device 112,122: I / O device

113,123 Redundancy control device 114,124 Synchronous writing device

210: clock multiplexer (MUX) 115,125: clock synchronization unit

220: operation mode determination unit 230: time division determination unit

240: clock phase shifter 250: clock difference allocation

260: clock divider 270: time division counter

280: counting start driver 261: clock driver

Claims (7)

A clock synchronizer by a time division method for providing clock synchronization in a control system having a fault-tolerant function consisting of redundancy of an active module and a standby module, An operation mode determination unit which mutually checks each other at system initialization, and when the other party is in the active mode, switches to the standby mode, and when the other party is in the standby mode, the module switches to the active mode; A clock multiplexer configured to output one of clocks transmitted from the two modules to a source clock according to an operation mode signal of the operation mode determiner; A clock difference generator for generating a divided clock for time division of the output source clock; A count start driver configured to generate a count start signal for determining a time point at which the source clock is time-divided using the division clock; A time division coefficient unit for time division of the source clock within one clock of the source clock and generating a time division period of the source clock by the count start signal; A time division determining unit configured to determine whether to time division and determine a degree of phase shift of the source clock by the time division period; And And a clock phase shifter for generating a phase shift sync clock for the source clock using the time division period generated by the time division coefficient unit and the phase shift signal determined by the time division determination unit. Synchronizer. The apparatus of claim 1, wherein the clock synchronizer comprises: And a clock distributor which distributes the phase shift synchronizing clocks output from the clock phase shifter to n system clocks having the same phase. The method of claim 2, wherein the clock distribution unit, A clock synchronization device using a time division method, characterized in that the clock tree (clock tree). The method of claim 1, wherein the clock multiplexer, If the operation mode signal input from the operation mode determiner is 'high', it recognizes the active mode and outputs its clock as the source clock. If the operation mode signal is 'low', it recognizes the clock of the counterpart as the standby mode. Clock synchronizing apparatus using a time division method characterized in that the output to the source clock. The method of claim 1, wherein the clock difference divider, And dividing the source clock into n time division sections, and generating a divided clock having a frequency n times that of the source clock. The method of claim 1, wherein the count start drive unit, Receiving a clock synchronization re-execution signal according to a signal level or a source clock change that the system initialization is not valid, and when the rising time of the source clock is sensed, generating the count start signal for driving the time division coefficient unit A clock synchronizer using a time division method. The method of claim 1, wherein the time division coefficient unit, And time-dividing the source clock while forming an endless loop of one period of the source clock by a predetermined value.