JPH05134945A - Bus interface mechanism - Google Patents

Abstract

PURPOSE:To continue the operation of a bus interface mechanism in a highly reliable state of a bus by dividing the data on plural buses into the groups of a certain scale respectively and invalidating only the bus of the group where a bus interface error is detected. CONSTITUTION:The input bus selection control circuits 6 and 10 are added with the AND circuits respectively and validate the bus interface error signals of other units which are inputted with the error group signals only when the bus interface errors of other units inputted through a signal line 3 are identical with the interface errors of the groups whose selection are going to be instructed by the input bus selector circuits 4 and 8. In other words, the circuit 6 validates only the bus interface errors of other units of a group 1 and the circuit 10 validates only the bus interface errors of other units of a group 2 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface mechanism having a plurality of buses in a non-stop type information processing device.

[0002]

2. Description of the Related Art A conventional bus interface mechanism has a bus A120, a bus B121, and a bus error detection circuit 124, which are dual buses that perform the same operation as shown in FIG.
Signal line 122 for transmitting the interface error of the bus detected by the other unit to another unit, input bus selection circuit 123 for selecting which input of bus A120 or bus B121 is used, and bus of bus A120 and bus B121. Of the bus error detection circuit 124 for detecting the interface error of the other unit, and the bus selected by the input bus selection circuit 123 according to the error detected by the bus error detection circuit 124 and the bus interface error of another unit transmitted through the signal line 122. It has an input bus selection control circuit 125. Next, the operation will be described with reference to FIGS. 10, 2 and 11. Here, FIG. 10 is a block diagram showing the configuration of the embodiment of the prior art, and FIG. 2 is a diagram showing an example of the bus error detection circuit 124. Similarly, FIG. 11 is a diagram showing an example of the input bus selection control circuit 125.

The bus A120 and the bus B121 are duplicated buses and operate exactly the same. This bus A120
Then, the input of the bus B121 is checked in the bus error detection circuit 124 to see if a bus interface error has occurred. Bus A1 for this check
20 and the data sent to the bus B121 are given a parity. The parity check of the bus A120 is performed by the parity check circuit 11, the parity check of the bus B121 is performed by the parity check circuit 13, and 1 is output when a parity error is detected. The comparison circuit 1 checks the comparison of the input data of the bus A120 and the bus B121.
When the comparison error is detected, 1 is output. Further, the AND circuits 14 and 15 perform AND between the parity check circuits 11 and 13 and the comparison circuit 12, and the bus interface error is detected from the result. That is, the input of the bus in which both the parity error and the comparison error are detected is recognized as the bus interface error. The reason for detecting both parity error and comparison error is that the comparison error alone cannot determine which bus caused the interface error, and the parity error alone caused the error when multiple bits caused the error. This is because there is a risk that an error cannot be detected when the number of bits is even. The AND circuit 14 outputs a bus A error signal indicating that an interface error has occurred on the bus A120, and the AND circuit 15 outputs a bus B error signal indicating that an interface error has occurred on the bus B121.

The bus A error signal and the bus B error signal are output to the input bus selection control circuit 125 and also sent to the signal line 122 for transmission to other units.

In the input bus selection control circuit 125, the bus A
The error signal, the bus B error signal, the bus A error signal of another unit input through the signal line 122, the bus B error signal, and the OR circuit 130 and the OR circuit 13 respectively.
Take an OR with 1. The outputs of the OR circuit 130 and the OR circuit 131 are input to the bus A error F / F 132 and the bus B error F / F 133, respectively. Bus A error F / F132
Once the bus B error F / F 133 is set, the output of itself becomes a hold signal, and the set state is maintained. In the NOR circuit 134, the OR circuit 130
Is output and a bus A error F / F 132 output is NORed, and a bus A selection signal for selecting the bus A 120 of the bus inputs is output. In the NOR circuit 135, the OR circuit 131 is used.
And the output of the bus B error F / F 133 are NORed, and a bus B selection signal for selecting the bus B 121 of the bus inputs is output. In other words, when a bus interface error is detected in the self unit or another unit, the cycle in which the interface error is detected and after that cycle, the bus selection signal in which the interface error is detected is not output.

The input bus selection circuit 123 selects which bus input is to be used according to the output of the input bus selection control circuit 125. When the interface error is detected on the bus B121 and only the bus A selection signal is output, the bus output of the bus A120 is selected, and when the interface error is detected on the bus A120 and only the bus B selection signal is output, the bus output is selected. Select the bus output of B121.
When no interface error of both the bus A120 and the bus B121 is detected, both the selection signals of the bus A selection signal and the bus B selection signal are output, and the input bus selection circuit 123 outputs the bus A120 and the bus B121. Both buses are selected, resulting in bus A120 and bus B
Although the inputs of 121 are ORed, there is no problem because the inputs of both buses have the same data.

As described above, in the prior art, once an interface error is detected on one of the duplicated buses that perform the same operation, the entire bus on the side where the interface error is detected is invalidated, and an interface error is detected. It was working only on the undetected side of the bus.

[0008]

The above-mentioned conventional bus interface mechanism, when an interface error is detected on either one of the duplex buses, invalidates the entire bus on the side where the interface error is detected, and It was operating only on the bus on which no error was detected. Therefore, even if the cause of the interface error is only a 1-bit fault on the bus, the entire bus must be invalidated. Further, when one of the duplex buses fails and only the other bus operates, it is difficult to replace the failed bus while the system is operating, and therefore non-stop is required. In some systems, the system had to be kept operating with insufficient bus configuration.

An object of the present invention is to provide a bus interface mechanism capable of preventing a decrease in system reliability when a failure occurs in a certain bus in a system having a plurality of buses which perform the same operation and which has improved reliability. To provide.

[0010]

A bus interface mechanism according to claim 1 of the present invention is a bus interface mechanism in an information processing apparatus having a plurality of buses performing the same operation, wherein signals of each bus of the plurality of buses are provided. Is divided into a plurality of groups, each unit connected to the plurality of buses, a bus error detection circuit having an error detection circuit for each group of the plurality of buses, and a bus detected by the bus error detection circuit. A bus error sending circuit for sending an interface error to another unit, a signal line for sending an output of the bus error sending circuit to another unit, and an input bus selection circuit for selecting a bus to be used among the plurality of buses. , But the interface error of the output of the bus error detection circuit and the bus of another unit sent through the signal line It said input bus selection circuit Te has an input bus selection control circuit for controlling the use of the input of which bus of the plurality of buses.

A bus interface mechanism according to a second aspect of the present invention is a bus interface mechanism in an information processing apparatus having a plurality of buses that perform the same operation, wherein signals of each bus of the plurality of buses are divided into a plurality of groups. However, when a bus interface error is detected in a certain group of a certain bus, a spare bus provided in advance as a substitute for the bus of the bus group in which the error is detected and each unit connected to the plurality of buses are ,
A bus error detection circuit having an error detection circuit for each group of the plurality of buses and each of the spare buses; and a bus error transmission circuit for transmitting the interface error of the bus detected by the bus error detection circuit to another unit,
A signal line for sending the output of the bus error sending circuit to another unit; an input bus selection circuit for selecting a bus to be used from among the plurality of buses and the spare bus; and a bus error detection circuit Input bus selection control for controlling which input of the plurality of buses and the spare bus is used by the input bus selection circuit according to an interface error of the output and the bus of another unit sent through the signal line A circuit, and a bus output switching circuit that switches the output to the group of the bus in which the interface error is detected to the spare bus when the bus error detection circuit detects an interface error in the group including the plurality of buses. Have.

[0012]

When data of a plurality of buses are divided into a plurality of groups and a bus interface error occurs in a certain bus group, only the bus group in which the interface error has occurred is invalidated and the bus in which the interface error occurs It does not affect the data of other groups and keeps operating with high reliability.

[0013]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment corresponding to claim 1 of the present invention. The bus interface mechanism of FIG. 1 performs the same operation and divides the bus data into two groups, that is, a bus A1 and a bus B2 which are duplicated buses, and an interface error of the bus transmitted by the bus error transmission circuit 7. A signal line 3 for transmitting to another unit and a bus A1 for each of two divided groups
And an input bus selection circuit 4 and 8 for selecting which input to use, and a bus error detection circuit 5 and 9 for detecting a bus interface error in units of two divided groups. The bus selected by the input bus selection circuits 4 and 10 is selected according to the error of one group of the bus data detected by the error detection circuits 5 and 9 and the interface error of the bus of each group of the other units transmitted through the signal line 3. According to the interface errors of the input bus selection control circuits 6 and 10 to control and the bus error detection circuits 5 and 9, which group of which bus has the interface error of the bus is transmitted to another unit through the signal line 3. It has a bus error sending circuit 7 for sending.

Here, the input bus selection circuit 4, the input bus selection circuit 8, the bus error detection circuit 5, the bus error detection circuit 9, the input bus selection control circuit 6, and the input bus selection control circuit 1
0 is an equivalent circuit. The bus error detection circuits 5 and 9 are equivalent to the bus error detection circuit 124 of the embodiment of the prior art shown in FIG. 10, and operate in the same manner.

Next, referring to FIGS. 1, 2, 3, and 4,
The operation of the embodiment corresponding to claim 1 of the present invention will be described.
2 is a diagram showing an example of the bus error detection circuits 5 and 9, FIG. 3 is a diagram showing an example of the input bus selection control circuits 6 and 10, and FIG. 4 is a diagram showing an example of the bus error transmission circuit 7. Is.

The buses A1 and B2 are duplicated buses, and the data on the buses are divided into two groups, and the parity for checking the interface error is given to each group. As a result, one of the two groups is set as group 1 and the other is set as group 2. The group 1 of the input data of the buses A1 and B2 is input to the bus error detection circuit 5, and the group 2 is input to the bus error detection circuit 9 to check whether a bus interface error has occurred. The bus error detection circuits 5 and 9 are the bus error detection circuit 1
The same operation as 24 is performed. Bus error detection circuit 5 is bus A
A group 1 bus A error signal indicating that an interface error has occurred in group 1 of 1 and a group 1 bus B error signal indicating that an interface error has occurred in group 1 of bus B2 are transmitted, and similarly, a bus error is detected. The circuit 9 sends out a group 2 bus A error signal indicating that an interface error has occurred in the group 2 of the bus A1 and a group 2 bus B error signal indicating that an error has occurred in the group 2 of the bus B2.

The bus error sending circuit 7 detects and sends to which group of which bus an error has occurred according to the error signals of the bus error detecting circuits 5 and 9. OR
The circuit 31 ORs the group 1 bus A error signal and the group 1 bus B error signal to obtain the bus A 1 or the bus B.
A group 1 error signal indicating that an interface error has occurred in group 1 of 2 is output. OR circuit 3
A group 2 ORs the group 1 bus B error signal and the group 2 bus B error signal to output a bus B error signal indicating that an interface error has occurred in the group 1 or group 2 of the bus B2. The OR circuit 33 ORs the group 1 bus A error signal and the group 2 bus B error signal and outputs a bus A error signal indicating that an interface error has occurred in the group 1 or group 2 of the bus A1. The OR circuit 34 ORs the group 2 bus A error signal and the group 2 bus B error signal and outputs a group 2 error signal indicating that an interface error has occurred in the group 2 of the bus A1 or the bus B2. Each output is output to the signal line 3 and transmitted to another unit through the signal line 3.

The input bus selection control circuits 6 and 10 have almost the same circuits as the input bus selection circuit 123 of the conventional example shown in FIG. 10, but with an AND circuit 27 and an AND circuit 28 added, the signal line 3 is added. Only when the interface error of the bus of the other unit input through the interface error is the interface error of the group whose selection is instructed by the input bus selection circuits 4 and 8, the interface of the bus of the other unit input by the error group signal is input. The error signal is valid. That is, in the input bus selection control circuit 6, only the interface error of the bus of the other unit of the group 1 becomes valid, and the input bus selection control circuit 10
Then, only the interface error of the bus of the other unit of group 2 is valid.

The input bus selection circuits 4 and 8 have almost the same functions as the input bus selection circuit of the conventional example shown in FIG. 10, and the input bus selection control circuits 6 and 10 output the bus selection signals according to the input bus selection signals. The selection circuit 4 is the bus A1 of group 1.
Input or the input of the bus B2 is selected, and the input bus selection circuit 8 selects which of the input of the bus A1 and the input of the bus B2 of the group 2 is used.

FIG. 5 is a block diagram showing the configuration of an embodiment corresponding to claim 2 of the present invention. The bus interface mechanism of FIG. 5 performs the same operation, and when an interface error is detected in a bus A41 and a bus B42 which are duplicated buses divided into two groups of data of the bus, and an interface error is detected in a certain bus group. Of the detected bus group instead of the bus of the detected bus group, a signal line 44 for transmitting an interface error of the bus transmitted by the bus error transmission circuit 49 to another unit, and two An input bus selection circuit 4 for selecting which input of the bus A41, the bus B42, and the spare bus 43 is used for each group divided into
5 and 51, and bus error detection circuits 46 and 52 that similarly detect interface errors of the bus A41, the bus B42, and the spare bus 43 in units of two divided groups,
According to the interface error of one group of the bus data detected by the bus error detection circuits 46 and 52 and the interface error of each group of the other unit transmitted through the signal line 44 and the bus of the spare bus 43, the input bus selection circuit 45, According to the interface error of the bus detected by the selection control circuits 47, 53 and the bus error detection circuits 46, 52, the input bus controlling the bus selected by 51 determines which group of which bus has the interface error of the bus. A bus error sending circuit 49 for sending to another unit through the signal line 44, and an output to the group of the bus in which the interface error is detected when the interface error is detected in a certain group of the bus A41 or the bus B42 is output to the spare bus 43. Turn off to output Sort bus output switching circuit 48, 50
have.

Further, each function of the embodiment corresponding to claim 2 of FIG. 5 has the same function as the function of the same name of the embodiment corresponding to claim 1 of FIG. 1, and each function of FIG. Is added to each function of FIG. 1 to use the spare bus 43 instead of the bus of the bus group in which the interface error is detected.

Next, the operation of the embodiment corresponding to claim 2 of the present invention will be described with reference to FIGS. 5, 6, 7, 8 and 9. 6 is a diagram showing an example of the bus error detection circuits 46 and 52, FIG. 7 is a diagram showing an example of the input bus selection control circuits 47 and 53, and FIG. 8 is a diagram showing an example of the bus error transmission circuit 49. And FIG. 9 shows the input bus selection circuits 45, 5
It is a figure which shows an example of 1.

The buses A41 and B42 are duplicated buses, and the data on the buses are divided into two groups, and the parity for checking the interface error is given to each group. Here, one of the two groups is referred to as group 1, and the other is referred to as group 2. The input data of the group 1 of the bus A41, the bus B42, and the spare bus 43 is the bus error detection circuit 4
6 and similarly, group 2 is input to the bus error detection circuit 52, and it is checked whether a bus interface error has occurred. The method of checking the interface error of the bus is the same as the conventional technique. The parity check circuits 61 and 63 and the comparison circuit 62 check the interface error between the buses A41 and B42, and the AND circuit 67 outputs a bus A error signal indicating that the interface error has occurred on the bus A41. From 68, a bus B error signal indicating that an interface error has occurred on the bus B42 is output. However, the outputs of the NOT circuits 71 and 72 are input to the AND circuits 67 and 68, respectively.
The OT circuit 71 inputs the output signal of the bus B error F / F 89, inverts the input to the AND circuit 67, and outputs NOT.
The circuit 72 inputs the output signal of the bus A error F / F 88 and inverts the input to the AND circuit 68.
The bus A error signal of the D circuit 67 is invalidated from the next cycle when the interface error is detected on the bus B 42, and the bus B error signal of the output of the AND circuit 68 is the bus A.
It is invalidated from the next cycle in which an error is detected at 41. This is because when an error is detected in the bus A41 or the bus B42, the error of the bus on the side where no error occurs and the spare bus 43 is detected from the next cycle. This is because it is necessary to invalidate the bus error output signal on the side where no error has occurred. The bus A4 is included in the bus AB selection circuit 60.
1 and data of bus B42 are input, and bus A error F /
Select the input of bus A41 by the output signal of F88,
The output signal of the error F / F 89 selects the output of the bus B42. That is, it is controlled to select the bus on the side where the interface error has not occurred. The parity check circuits 64, 66 and the comparison circuit 65 check the interface error between the bus selected by the bus AB selection circuit 60 and the spare bus 43, and the AND circuit 69 detects the interface error on both the bus A41 and the bus B42. The bus AB error signal indicating that it has occurred is output, and the standby bus error signal indicating that an interface error has occurred on the standby bus 43 is output from the AND circuit 70. Contrary to the bus A error output signal and the bus B error output signal, these two output signals are the output signals of the bus A error F / F 88 and the bus B output from the OR circuit 73.
It is made valid by ORing the output signals of the error F / F 89. That is, it is invalid unless an error is detected in either the bus A41 or the bus B42. In this way, bus interface errors are detected. The bus error detection circuit 46 detects an interface error of the bus of the group 1 of the bus A41 and the bus B42, and the spare bus 43 is also used instead of the bus of the group 1 of either the bus A41 or the bus B42. When an interface error is detected. The bus error detection circuit 52 performs the same operation as the bus error detection circuit 46 on the buses of group 2.

The bus error sending circuit 49 detects which group of which bus has an error in accordance with each error signal output from the bus error detecting circuits 46 and 52, and sends it to another unit through the signal line 44. OR
In the circuit 100, all the error signals of the buses of group 1 are ORed to indicate that an interface error has occurred in the bus of group 1 of either bus.
Output an error signal. The OR circuit 101 is group 1
The OR circuit 102 takes the OR of the bus A error signals of 2 and the OR circuit 102 takes the OR of the bus B error signals of groups 1 and 2.
The circuit 103 outputs O of the bus AB error signals of groups 1 and 2.
Take R. After this, the OR circuit 106 causes the OR circuit 101
And the output of the OR circuit 102 are ORed, and a bus A error signal indicating that an interface error has occurred on the bus A 41 is output.
At 42, a bus B error signal indicating that an interface error has occurred is output. The OR circuit 104 ORs the spare bus error signals of groups 1 and 2 and outputs a spare bus error signal indicating that an interface error has occurred in the spare bus error 43. The OR circuit 105 takes the OR of all the error signals of group 2 and outputs a group 2 error signal indicating that an error has occurred in any of the bus groups.

The input bus selection control circuits 47 and 53 receive the bus according to the interface error of the bus of the other unit transmitted through the signal line 44 and the interface error signal of the bus of each group detected by the bus error detection circuits 47 and 52. A selection signal, bus B selection signal, bus AB selection signal, spare bus selection signal, bus A error F / F
The output signal and the bus B error F / F output signal are output. A
The interface error signal of the bus of another unit input from the signal line 44 by the ND circuits 80, 81 and 82 is validated by the input bus selection control circuit 47 only when the interface error of the group 1 occurs, and the input bus selection control circuit 53 is provided. Then, it is enabled only when there is an interface error of group 2. OR circuits 84, 8
Reference numerals 5, 86 and 87 take the OR of the interface error of the bus of the other unit and the interface error of the bus detected by the bus error detection circuit 46 or 52 of the own unit. However, the bus AB error signal is the bus A41 and the bus B.
Since both 42 are signals indicating that an error has occurred, an AND of the other unit bus A error signal and the other unit bus B error signal is taken as an output after being taken by the AND circuit 83, and is ORed. Bus A error F / F88, bus B
The error F / F 89, the bus AB error F / F 90, and the spare bus error F / F 91 are OR circuits 84, 85, 8 respectively.
When the outputs of 6, 87 are input and once set, the output of itself becomes a hold signal, and the set state is maintained. However, the bus AB error F / F 90 and the spare bus error F / F 91 are not set unless either the bus A error F / F 88 or the bus B error F / F 89 is set.
8 and the output signal of the bus B error F / F 89 are ORed O
The output of the R circuit 92 becomes the set signal. This is because the bus AB error signal and the spare bus error signal output from the bus error detection circuits 46 and 52 are the bus A41 or the bus B4.
This is because it becomes valid only after the cycle after the interface error is detected in either of the two. Further, this set signal is weaker than the hold signal, that is, the contents of the F / F once set remain held. NOR
The circuit 95 takes the NOR of the output signal of the OR circuit 84 and the bus A error F / F 88, and outputs the bus A selection signal instructing the input bus selection circuits 45 and 51 to select the bus A 41. That is, after the cycle in which the interface error is detected on the bus A41, the input bus selection circuits 45 and 51 are controlled so as not to select the input of the bus A41 by the bus A selection signal. Similarly, the NOR circuit 96 outputs a bus B selection signal, and the NOR circuit 93 outputs a bus AB selection signal. The NOR circuit 94 outputs a signal indicating that no interface error is detected to the spare bus 43, and this output and the output of the OR circuit 92 are AND circuit 9
AND in 7 to output the spare bus selection signal. That is, an interface error is detected in either the bus A41 or the bus B42, and the spare bus is used from the next cycle in which the interface error is detected. Therefore, no interface error is detected in the spare bus 43 and the bus A error F / F88 or Bus B error F / F89
Input bus selection circuit 4 only when is set
The spare bus selection signal is controlled so that the spare bus is selected at 5 and 51.

The input bus selection circuit 45 selects the input of the bus designated by the input bus selection control circuit 47 for the data of group 1, and the input bus selection circuit 51 controls the input bus selection for the data of group 2. Select the input of the bus indicated by circuit 53. In the selection circuit 110, the bus A4 and the bus B selection signal cause the bus A4
1 or the input of the bus B42 is selected. Selection circuit 11
In 1, the bus AB selection signal and the spare bus selection signal
The input of the spare bus 43 or the output of the selection circuit 110 is selected.

The bus output switching circuit 48 outputs the bus output of group 1 to the bus A41 and the bus B42, and sets either the bus A error F / F88 or the bus B error F / F89 of the input bus selection control circuit 47. And the bus A error F / of the input bus selection control circuit 53
The bus output of group 1 is output to the spare bus 43 only when neither F88 nor bus B error F / F89 is set. Similarly, the bus output switching circuit 50 controls the output of the group 2 bus output to the bus A41, the bus B42, and the spare bus 43.

[0029]

As described above, according to the present invention, data of a plurality of buses is divided into a certain size and grouped,
When a bus interface error is detected, by disabling only the bus in the group in which the interface error was detected, a 1-bit fault on the bus causes
Allows groups other than the failing group to continue operating in a reliable bus state without disabling the entire failing bus.

Further, by using a spare bus provided in advance in place of the faulty bus, the operation can be continued without degrading the reliability in a bus state which is completely the same as before the fault occurred. You can

As described above, there is an effect that a highly reliable system can be maintained even when a failure occurs in a bus for which online maintenance is difficult.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment corresponding to claim 1 of the present invention.

FIG. 2 is a diagram showing an example of a bus error detection circuit according to claim 1 of the present invention and a conventional example.

FIG. 3 is a diagram showing an example of an input bus selection control circuit according to claim 1 of the present invention.

FIG. 4 is a diagram showing an example of a bus error sending circuit according to claim 1 of the present invention.

FIG. 5 is a block diagram showing a configuration of an embodiment corresponding to claim 2 of the present invention.

FIG. 6 is a diagram showing an example of a bus error detection circuit according to claim 2 of the present invention.

FIG. 7 is a diagram showing an example of an input bus selection control circuit according to claim 2 of the present invention.

FIG. 8 is a diagram showing an example of a bus error sending circuit according to claim 2 of the present invention.

FIG. 9 is a diagram showing an example of an input bus selection circuit according to claim 2 of the present invention.

FIG. 10 is a block diagram showing a configuration of an example of a conventional technique.

FIG. 11 is a diagram showing an example of a conventional input bus selection control circuit.

[Explanation of symbols]

1 bus A 2 bus B 3 signal line 4,8 input bus selection circuit 5,9 bus error detection circuit 6,10 input bus selection control circuit 7 bus error transmission circuit 11,13 parity check circuit 12 comparison circuit 14,15 AND circuit 21, 22 OR circuit 23 Bus A error F / F 24 Bus B error F / F 25, 26 NOR circuit 27, 28 AND circuit 31, 32, 33, 34 OR circuit 41 Bus A 42 Bus B 43 Spare bus 44 Signal line 45,51 Input bus selection circuit 46,52 Bus error detection circuit 47,53 Input bus selection control circuit 48,50 Bus output switching circuit 49 Bus error transmission circuit 60 Bus AB selection circuit 61,63,64,66 Parity check circuit 62 , 65 Comparison circuit 67, 68, 69, 70 AND circuit 71, 72 NOT circuit 73, 8 , 85, 86, 87 OR circuit 80, 81, 82, 83 AND circuit 88 Bus A error F / F 89 Bus B error F / F 90 Bus AB error F / F 91 Reserve bus error F / F 92 OR circuit 93, 94, 95, 96 NOR circuit 97 AND circuit 100, 101, 102, 103, 104, 105, 1
06,107 OR circuit 110,111 selection circuit

Claims (2)

[Claims] 1. A bus interface mechanism in an information processing apparatus comprising a plurality of buses that perform the same operation, wherein signals of each bus of the plurality of buses are divided into a plurality of groups, and the signals are connected to the plurality of buses. A unit, a bus error detection circuit having an error detection circuit for each of the plurality of groups, a bus error transmission circuit for transmitting the interface error of the bus detected by the bus error detection circuit to another unit, the bus error transmission circuit Signal line for sending the output of the above to another unit, an input bus selection circuit for selecting a bus to be used among the plurality of buses, an output of the bus error detection circuit and another unit sent through the signal line Input bus selection circuit uses an input of any one of the plurality of buses according to a bus interface error of Bus interface mechanism, characterized in that it comprises an input bus selector control circuit for controlling. 2. A bus interface mechanism in an information processing apparatus having a plurality of buses performing the same operation, wherein signals of each bus of the plurality of buses are divided into a plurality of groups, and a bus interface in a certain group of a certain bus. When an error is detected, a spare bus which is provided in advance as a substitute for the bus of the group of the bus in which the error is detected, and each unit connected to the plurality of buses are provided for each group of the plurality of buses and the spare. A bus error detection circuit having an error detection circuit on each of the buses, a bus error transmission circuit for transmitting the interface error of the bus detected by the bus error detection circuit to another unit, and an output of the bus error transmission circuit to another unit. Select the signal line for sending and the bus to be used among the plurality of buses and the spare bus. An input bus selection circuit, which outputs the bus error detection circuit, and which of the plurality of buses and the spare bus is selected by the input bus selection circuit according to an interface error of the bus of another unit sent through the signal line. An input bus selection control circuit for controlling whether to use the input of the above, and when the bus error detection circuit detects an interface error in a group of the plurality of buses, an output to the group of the bus in which the interface error is detected is output. A bus interface mechanism comprising a bus output switching circuit for switching to output to a spare bus.