KR100438068B1 - Frequency and Phase Locked Loop system of digital repeater and receiver - Google Patents

Abstract

An FPLL system of a digital repeater and a receiver according to the present invention comprises: a digital step attenuator for constant attenuation of an intermediate frequency signal having a pilot signal; A channel filter for filtering the attenuated intermediate frequency signal to remove adjacent channel components; An IQ demodulator for amplifying the output intermediate frequency signal of the channel filter, multiplying the local signal of the voltage controlled oscillator, and demodulating the final I, Q channel signal to output it; A frequency and phase synchronizer for comparing phases of the demodulated I and Q channel signals and controlling a DC level of the voltage controlled oscillator according to an output voltage level corresponding to the phase difference; An offset controller which controls a DC offset value of the frequency and phase synchronizer; And a controller and an SNR indicator for controlling the respective units to control the DC offset control and the signal-to-noise ratio.

According to the present invention, the control voltage of the oscillator is varied by controlling the attenuation degree of the intermediate frequency signal having the carrier at the first stage and compensating the DC offset of the phase detection signal of the circuit for frequency and phase synchronization. This allows precise automatic gain control and DC offset adjustment in the entire FPLL system, as well as the removal of adjacent channel components using channel filters.

Description

FPL system of digital repeater and receiver {Frequency and Phase Locked Loop system of digital repeater and receiver}

The present invention relates to a frequency and phase locked loop (FPLL) circuit of a digital repeater and a receiver, and more particularly, to an FPLL system of a digital repeater and a receiver capable of automatic gain control and DC offset adjustment.

The FPLL circuit of the conventional digital repeater and receiver is shown in FIG.

A first mixer (I Mixer) outputting an I channel signal by multiplying a signal (Signal * Pilot) in which an intermediate frequency band signal (Signal) and a pilot signal (Pilot) are combined with an output signal of the voltage controlled oscillator (VCO) 109. 101, a first low pass filter (LPF) 102 through which only a predetermined low frequency band of the I channel signal is passed, and a signal obtained by combining a signal of the intermediate frequency band and a pilot signal with a voltage controlled oscillator 109. A second mixer (Q mixer) 103 for outputting a Q channel signal by multiplying with an output signal of the second mixer, and a second low pass filter 104 for passing only a predetermined low frequency band of the Q channel signals of the second mixer 103. An AFC filter (AFC LPF) 105 for changing its phase according to the frequency of the I channel signal of the first low pass filter, and a hard limiter for amplifying and limiting the output signal of the AFC filter 105 by a predetermined gain. (Hard Limiter) 106, the output signal of the hard limiter 106 and the second low A third control unit 107 for multiplying and outputting an output signal of a pass filter, and a loop control signal for passing only a predetermined low frequency band signal among the output signals of the third mixer and allowing the selected carrier to be corrected to a desired frequency And a loop filter 108 provided to the voltage controlled oscillator (VCO) 109.

The FPLL circuit of the digital repeater and the receiver will be described with reference to the accompanying drawings as follows.

The first mixer and the second mixer 101 and 103 are inputted with a signal Signal * Pilot (Wo) in which the actual signal of the intermediate frequency IF and the pilot signal are combined. Then, the first mixer 101 multiplies the local signal (Wc + 0 °) of the voltage controlled oscillator 109 by the input signal (Wo) to output the sum and difference I channel signals (Wo + Wc, Wo-Wc). The second mixer 103 multiplies the local signal (Wc + 90 °) of the voltage controlled oscillator 109 by the input signal (Wo) and adds the sum and difference of the Q channel signals (Wo + Wc-90 and Wo-Wc). -90) is output. Here, a signal in which the phase of the local signal applied to the second mixer 103 is delayed by exactly 90 ° in phase from the local signal applied to the first mixer 101 by the voltage controlled oscillator 109 is input.

The first low pass filter 102 passes only a predetermined low frequency band (Wo-Wc) to remove only components of the sum of the I channel signals, and the second low pass filter 104 removes only the components of the sum of the Q channel signals. In order to pass only a predetermined low frequency band (Wo-Wc-90).

The output of the first low pass filter 102 is input to the AD converter for timing recovery and to the AFC filter 105. The AFC filter 105 has a phase and frequency characteristic as shown in FIG. 2 and has a magnitude of a beat frequency corresponding to a difference between a carrier signal frequency that is a pilot among local signals and an intermediate frequency input signal, that is, a frequency of an I channel signal. Only the phase is changed according to the output.

The output signal whose phase of the same frequency is changed by the AFC filter 105 according to the value of the bit frequency is zero-crossing detector in the hard limiter 106. A signal larger than zero is +1, 0. A smaller signal will output a -1 output with a rectangular wave.

The output of the hard limiter 106 and the output of the second low pass filter 104 are multiplied by a third mixer 107, which is the very low frequency of the hard limiter 104, i.e. The signal shape is a square wave, and the signal spectrum is multiplied by two signals in which the frequency signal, which is a high frequency component, the bit frequency of the second low pass filter 104, and the baseband Q signal in a complex form are combined.

The output signal form of the third mixer 107 is represented in various forms according to the value of the bit frequency, as in the f1 signal shown in (a) (b) and (c) of FIG. 3. As the output signal is input to a loop filter 108 functioning as an AFC filter, the loop filter 108 controls the DC level of the voltage controlled oscillator (VCO) 109 so that the carrier wave is corrected to a desired frequency.

That is, the voltage controlled oscillator 109 is controlled in accordance with the DC level of f2 shown in (a) (b) (c) of FIG. 3, and the output frequency of the voltage controlled oscillator 109 is equal to the carrier signal of the input intermediate frequency signal. By feeding back the entire loop circuit until it has the same frequency and phase, eventually carrier recovery is successfully performed.

However, there is no channel filter in the related art, and thus, adjacent channels cannot be blocked effectively, and only the I channel signal is output and the Q channel signal is not output. The locking path for the voltage-controlled oscillator and the actual output signal path are the same, making it difficult to adjust the output level required for the timing recovery circuit located behind the FPLL circuit.

In addition, the conventional FPLL circuit does not have an overall automatic gain control (AGC) function, it is difficult to adjust the DC offset voltage for locking in the circuit, there is a problem that must be adjusted manually.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and controls by varying the attenuation degree of an intermediate frequency signal having a carrier at an input terminal, and compensates for the DC offset of a phase detection signal of a circuit for frequency and phase synchronization. The purpose of the present invention is to provide a FPLL system of a digital repeater and a receiver which enables precise automatic gain control and DC offset adjustment in an entire FPLL system by varying the control voltage of the voltage controlled oscillator.

Another feature is to provide an FPLL system of a digital repeater and receiver that allows the use of channel filters to remove adjacent channel components.

It is another object of the present invention to provide a FPLL system of a digital repeater and a receiver capable of outputting both an I channel signal and a Q channel signal demodulated by an IQ demodulator.

1 is a configuration diagram of a FPLL circuit of a conventional digital repeater and a receiver.

2 is a graph showing a frequency band phase relationship in the conventional AFC LPF.

3 is an input and output waveform diagram of a conventional loop filter.

4 is a block diagram illustrating a FPLL system of a digital repeater and a receiver according to an exemplary embodiment of the present invention.

5 is a block diagram of a digital step attenuator in the present invention.

<Explanation of symbols for the main parts of the drawings>

101,103,108,232,242 ... mixer 102,104,234,238 ... LPF

105,241 ... AFC LPF 106,242 ... Hard Limiter

108,244 ... loop filter 109,246 ... voltage controlled oscillator

210 ... Digital Step Attenuator 220 ... Channel Filter

230 ... I / Q demodulator 231 ... Mid frequency amplifier

232 1st amplifier 235,239,261,262 ... buffer

237 ... 2nd amplifier 240 ... feedback

243 Phase detectors 245252 Operational amplifiers

247 Phase Shifter 251 Digital Registers

250 ... offset control 270 ... controller and SNR indicator

In order to achieve the above object, the FPLL system of the digital repeater and receiver according to the present invention,

A digital step attenuator for constant attenuation of the intermediate frequency signal having a pilot signal;

A channel filter for filtering the attenuated intermediate frequency signal to remove adjacent channel components;

An IQ demodulator for amplifying the output intermediate frequency signal of the channel filter, multiplying the local signal of the voltage controlled oscillator, and demodulating the final I, Q channel signal to output it;

A frequency and phase synchronizer for comparing phases of the demodulated I and Q channel signals and controlling a DC level of the voltage controlled oscillator according to an output voltage level corresponding to the phase difference;

An offset controller which controls a DC offset value of the frequency and phase synchronizer;

And a controller and an SNR indicator for controlling the respective units to control the DC offset control and the signal-to-noise ratio.

Preferably, the digital step attenuator includes a digital register whose internal resistance value is increased or decreased by a control signal (CLK, Up / Down) of a controller and an SNR indicator, and an output for an input signal according to a change in the resistance value of the digital register. It characterized in that it comprises a hybrid coupler for varying the degree of attenuation of the signal.

Preferably, the IQ demodulator includes an intermediate frequency amplifier for amplifying the output signal of the channel filter, a first mixer for outputting an I channel signal by multiplying the output signal of the phase shifted first local signal and the intermediate frequency amplifier, and an I channel. A first low pass filter for passing only a predetermined low frequency band of the I channel signal of the first amplifying part, a first amplifier for amplifying a signal, a first buffer for buffering an I channel signal passed through the first low pass filter, and And a second mixer for outputting a Q channel signal by multiplying the phase shifted second local signal by the output signal of the intermediate frequency amplifier, a second amplifier for amplifying the Q channel signal, and a predetermined low frequency band among the amplified Q channel signals. And a second buffer configured to buffer the output of the second low pass filter and to output the second low pass filter.

Preferably, the frequency and phase synchronizer includes an AFC filter (AFC LPF) for changing a phase according to the frequency of an output I-channel signal of a first buffer, and a hard limiter for amplifying and limiting an output signal of an AFC filter by a predetermined gain. Limiter), a phase detector for detecting and outputting a phase difference between the output of the hard limiter and the output Q channel signal of the second buffer, a loop filter for outputting a DC voltage according to the output bit frequency of the phase detector, An operational amplifier for stabilizing an output, a voltage controlled oscillator for outputting an oscillation frequency corresponding to the output voltage of the operational amplifier, a first local signal and a second local signal having a 90-phase difference according to the oscillation frequency of the voltage controlled oscillator Characterized in that it comprises a phase shifter for outputting.

The offset control unit may include a digital register for changing an internal resistance value by a control signal of the controller and the SNR indicator, and an operational amplifier for controlling a phase detector DC offset of the frequency and phase synchronizer according to a change in the resistance value of the digital register. It is characterized by including.

Hereinafter, with reference to the accompanying drawings as follows.

4 is a configuration diagram of a FPLL system of a digital repeater and a receiver according to an exemplary embodiment of the present invention, and FIG. 5 is a configuration diagram of a digital step attenuator according to the present invention.

Referring to FIG. 4, a digital step attenuator 210 for attenuating a predetermined intermediate frequency signal, a channel filter 220 for filtering the attenuated intermediate frequency signal to remove adjacent channel components, and an output intermediate frequency of the channel filter. An IQ demodulator 230 for amplifying and demodulating the signal and converting the signal into I and Q channel signals, and multiplying the demodulated I and Q channel signals to loop the same frequency and phase as the carrier signal of the input intermediate frequency signal according to the bit frequency. The DC level coming from the output of the filter 244 is a frequency and phase synchronizer 240 for controlling the voltage controlled oscillator 246, an offset controller 250 for controlling a DC offset value of the frequency and phase synchronizer, and I Buffers 261 and 262 for outputting channel signals and Q channel signals, and controllers and SNR indicators 270 for controlling the DC offset control and the signal-to-noise ratio by controlling the units.

Herein, the digital step attenuator 210 is composed of a digital register 211 and a hybrid coupler 212 as shown in FIG. 5, and controls the signals of the controller and the SNR indicator 270 (CLK, Up / Down). The degree of attenuation of the output signal relative to the input signal varies.

The IQ demodulator 230 multiplies the output signal of the channel filter 220 by the intermediate frequency amplifier 231 and the output signal of the I channel signal by multiplying the output signal of the intermediate frequency amplifier by the phase shifted first local signal. A first mixer 232, a first amplifier 233 for amplifying the I-channel signal, a first low pass filter 234 for passing only a predetermined low frequency band of the I-channel signal of the first amplifier, and a first A first buffer 235 for buffering the I-channel signal passing through the low pass filter, a second mixer 236 for outputting a Q-channel signal by multiplying the phase shifted second local signal and the output signal of the intermediate frequency amplifier, A second amplifier 237 for amplifying the Q channel signal, a second low pass filter 238 for passing only a predetermined low frequency band of the amplified Q channel signal, and buffering the output of the second low pass filter It consists of a second buffer 239 to output.

The frequency and phase synchronizer 240 detects a phase difference between an AFC filter (AFC LPF) 241, a hard limiter 242, an output of the hard limiter, and an output Q channel signal of the second buffer. An output phase detector 243, a loop filter 244, a first operational amplifier (OP-AMP) 245, a voltage controlled oscillator (VCXO) 246, and a phase shifter 247 are configured.

The offset control unit 250 is composed of a digital register 251 and a second operational amplifier 252.

The FPLL system of the digital repeater and the receiver according to the present invention as described above will be described with reference to the accompanying drawings.

When a signal of an intermediate frequency band (Signal * Pilot) in which the pilot signals are combined is input to the FPLL circuit, the initial attenuation value by the controller and the SNR indicator 270 controls the digital step attenuator 210 so that the initial attenuation value is determined. .

While the input intermediate frequency signal Signal * Pilot passes through the digital step attenuator 210, the FPLL circuit is appropriately attenuated by the required amount, and the adjacent channel component is lost through the channel filter 220. The input intermediate frequency signal is converted into a differential signal (+,-) while passing through the channel filter 220, and the signal is input to the intermediate frequency amplifier 231 of the IQ demodulator 230. In this case, the channel filter 220 generally suppresses a desired adjacent channel and outputs only an assigned channel, and a band capable of relatively reducing a loss of a passband and a distortion of a high frequency component compared to the same adjacent channel characteristic. It functions as a band pass filter (BPF).

The IQ demodulator 230 includes an intermediate frequency amplifier 231, first and second mixers 232 and 236, first and second amplifiers 233 and 237, first and second low pass filters 234 and 238, and first and second The second buffers 235 and 239 and the signals amplified by the IF AMP 231 are simultaneously fed to the first mixer 232 and the second mixer 236. Is entered.

The first mixer 232 is multiplied by the first local signal (0 °) passing through the phase shifter 247 for phase shifting the signal of the voltage controlled oscillator 246 by 90 degrees to generate the sum and difference I channel signal, A predetermined level is amplified by the first amplifier (I AMP) 233, and after passing only a predetermined low frequency band so that the signal of the sum component is removed by the first low pass filter 234, the first buffer 235 is Is output via

The second mixer 236 outputs the second local signal (90 °) passing through the phase shifter 247, that is, the local signal (90 °) delayed by 90 degrees with respect to the first local signal and the output signal of the intermediate frequency amplifier. The multiplier generates and outputs a Q channel signal having a difference and a sum component, and the output Q channel signal of the second mixer 236 is amplified by a second level (Q AMP) 237 by a predetermined level and the second low pass filter. Only the low pass frequency is passed by 238 to output only the Q channel signal having a difference component, and the output Q channel signal of the second low pass filter 238 is output through the second buffer (Q buffer) 239. do.

The frequency and phase synchronizer 240 includes an AFC filter 241, a hard limiter 242, a phase detector 243, a loop filter 244, a first operational amplifier 245, a voltage controlled oscillator 246, The AFC filter 241 has a phase and frequency characteristic as shown in FIG. 2, and the phase shifter 247 includes only a phase according to the magnitude of a bit frequency corresponding to a difference between a pilot signal frequency among a local signal and an intermediate frequency input signal. The output will be changed. The output signal whose phase of the same frequency is changed according to the value of the bit frequency passes through the hard limiter 242. The hard limiter 242 is a zero crossing detector, and a signal larger than 0 is +1, and a signal smaller than 0 is-. We set it to 1 and make the output square wave.

On the other hand, the phase detector 243 compares the phase of the output I channel signal of the hard limiter 242 and the output Q channel signal of the second buffer 239 for locking and outputs a signal corresponding to the phase difference, The loop filter 244 outputs the phase difference signal at a DC level.

The first operational amplifier 245 stabilizes the output DC level of the loop filter 244 and then controls the control voltage of the voltage controlled oscillator 246. According to the control voltage, the phase of the local signal output from the voltage controlled oscillator 246 is shifted by 90 degrees by the phase shifter 247 to output a first local signal and a second local signal having a phase orthogonal.

At this time, the offset control unit 250 is composed of a digital register 251, the second operational amplifier 252, and controls the output DC offset of the phase detector 243 under the control of the controller and the SNR indicator 270, The controller and SNR indicator 270 controls the resistance value of the digital register 251 with an up / down signal (Up / Down), and provides the clock CLK as much as desired, thereby providing Change the output resistance value.

The second operational amplifier 252 changes the voltage value due to the change in the resistance value of the digital register 251 and controls the DC offset of the phase detector 243.

To this end, the controller and the SNR indicator 270 first calculate the SNR value from the input I and Q signals. In the case of VSB (vestigial sideband), the calculation of the signal-to-noise ratio (SNR) value can be calculated by the following equation.

I _j is the jth ideal symbol value, Is the difference between the jth ideal symbol value and the actual received value, and N is the total number of received data.

Here, when the calculated S / N value is lower than the desired value, the controller and the SNR indicator 270 first increase or decrease the resistance value of the digital register 211 which is a component of the digital step attenuator 210. By controlling the Up / Down and providing a clock (CLK) corresponding to the desired resistance value, thereby changing the output resistance value of the digital resistor 211 and the changed resistance value is the hybrid coupler 212. The amount of attenuation of the output signal relative to the input signal is determined by determining the amount of coupler with the resistor R and the zener diode ZD for the intermediate frequency signal Input. In this way, the attenuation amount can be determined very precisely, and the optimum attenuation amount can be determined.

In addition, the controller and the SNR indicator 270 control the output DC offset of the phase detector 243, which is not increased even when the digital step attenuator 210 has a signal-to-noise ratio (SNR) value. By increasing or decreasing the resistance value of the digital register 251 of the offset control unit 250 by controlling the up / down signal Up / Down and providing the clock CLK as much as desired, The DC resistance of the phase detector 243 is controlled after changing the voltage value of the second operational amplifier 252 by changing the output resistance value of 251. This makes it possible to automatically maintain the optimum SNR in any case.

In addition, the controller and the SNR indicator 270 may output an output I channel signal of the first buffer 235 and an output Q channel signal of the second buffer 239 input to the third buffer 261 and the fourth buffer 262, respectively. Are controlled so that the final I / Q channel signal is output.

As described above, according to the FPLL system of the digital repeater and the receiver according to the present invention, the precise DC offset using the digital step attenuator is adjusted with the implementation of the precise automatic gain control using the 90 degree hybrid coupler and the digital step attenuator. In addition, the FPLL circuit has the effect of independently controlling the signal required for locking and the output level actually passed to the next stage.

In addition, by using the channel filter, when the FPLL circuit is used as a receiver, the effect of the adjacent channel can be eliminated. Also, the I, Q channel signal mode can be used as the output signal when only the conventional I channel signal is output. .

In addition, by controlling the DC offset of the phase detector together with the control of the degree of attenuation of the input signal, the signal-to-noise ratio can be improved by 10 dB or more.

Claims (6)

A digital step attenuator for constant attenuation of the intermediate frequency signal having a pilot signal; A channel filter for filtering the attenuated intermediate frequency signal to remove adjacent channel components; An IQ demodulator for amplifying the output intermediate frequency signal of the channel filter, multiplying the local signal of the voltage controlled oscillator, and demodulating the final I, Q channel signal to output it; A frequency and phase synchronizer for comparing phases of the demodulated I and Q channel signals and controlling a DC level of the voltage controlled oscillator according to an output voltage level corresponding to the phase difference; An offset controller which controls a DC offset value of the frequency and phase synchronizer; And a controller and an SNR indicator for controlling the respective units to control the DC offset control and the signal-to-noise ratio. The method of claim 1, The digital step attenuator includes a digital register whose internal resistance value is increased or decreased by a control signal (CLK, Up / Down) of a controller and an SNR indicator, and an attenuation of an output signal with respect to an input signal according to a change in the resistance value of the digital register. An FPLL system of a digital repeater and receiver comprising a hybrid coupler of varying degrees. The method of claim 1, The IQ demodulator multiplies the intermediate frequency amplifier for amplifying the output signal of the channel filter, the first mixer for outputting the I channel signal by multiplying the output signal of the phase shifted first local signal and the intermediate frequency amplifier, and amplifies the I channel signal. A first low pass filter for passing only a predetermined low frequency band among the I channel signals of the first amplifier, the first amplifier, a first buffer for buffering the I channel signal passed through the first low pass filter, and a phase shifted signal A second mixer for multiplying the second local signal by the output signal of the intermediate frequency amplifier and outputting a Q channel signal, a second amplifier for amplifying the Q channel signal, and a second low frequency band of the amplified Q channel signal; And a second buffer for buffering the output of the second low pass filter and outputting the second low pass filter. The method of claim 1, The frequency and phase synchronizer includes an AFC filter (AFC LPF) for changing the phase according to the frequency of the output I-channel signal of the first buffer, a hard limiter (Hard Limiter) for amplifying and limiting the output signal of the AFC filter by a predetermined gain; A phase detector for detecting and outputting a phase difference between the output of the hard limiter and the output Q channel signal of the second buffer, a loop filter for outputting a DC voltage according to the output bit frequency of the phase detector, and stabilizing the output of the loop filter. An op amp, a voltage controlled oscillator for outputting an oscillation frequency corresponding to the output voltage of the operational amplifier, and a first local signal and a second local signal having a 90-phase difference according to the oscillation frequency of the voltage controlled oscillator. A FPLL system of a digital repeater and receiver comprising a phase shifter. The method of claim 1, The offset control unit includes a digital register for changing an internal resistance value by a control signal of the controller and an SNR indicator, and an operational amplifier for controlling a DC offset of a phase detector of the frequency and phase synchronizer according to a change in the resistance value of the digital register. FPLL system of the digital repeater and receiver. The method of claim 1, The controller and the SNR indicator control the third buffer and the fourth buffer for buffering the I channel signal of the first buffer and the Q channel signal of the second buffer so that the final I / Q channel signal is output. And FPLL system of the receiver.