KR0153604B1 - Frequency and phase automatic regulation circuit and method of receiver - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs.

Wireless receiver.

2. The technical problem that the invention is trying to solve.

In the circuit for controlling the frequency and phase error using the pilot signal, a plurality of means for detecting the frequency error is provided to selectively output the error detection signal according to the amount of the frequency error to control the error.

3. Summary of the solution of the invention.

A circuit for automatically adjusting frequency and phase errors in a wireless receiver includes means for changing a received signal to an intermediate frequency by a control signal, first filter means for inputting the intermediate frequency to filter a pilot band signal; Means for generating a one-channel signal and a Q-channel signal by inputting the output of said first filter means, means for generating a first detection signal by differentiating said I-channel signal, and low-pass filtering said I-channel signal. 2 means for generating a detection signal, means for inputting said detection signal to detect an amount of error in frequency, for generating a selection signal in comparison with a set reference value, and receiving outputs of said first and second detection means; Means for selecting an output of a detection means corresponding to the selection signal, mixing the Q channel signal with an output signal as an error detection signal, and converting the error detection signal into a control voltage; The oscillation by the conversion and control voltage generating frequencies for removing the frequency error and consists of means for outputting to said intermediate frequency converting means for error control signal.

4. Important uses of the invention.

The radio receiver automatically distinguishes between large and small frequency errors and automatically controls the frequency and phase errors of the received signal.

Description

Frequency and phase automatic adjustment circuit and method of receiver.

1 is a diagram showing the configuration of a circuit for adjusting frequency and phase in a conventional receiver.

2 is a diagram showing a configuration of a circuit for automatically adjusting frequency and phase in a receiving apparatus according to the present invention.

FIG. 3 is a diagram showing the configuration of the lock detector in FIG. 2. FIG.

The present invention relates to a frequency and phase adjustment circuit and method of an apparatus for receiving a radio signal, and more particularly to a circuit and a method capable of automatically adjusting the frequency and phase by detecting a pilot signal.

In general, a device that receives a radio signal modulated by a residual side band modulation method, a double side band modulation method, and a single side band modulation method detects a pilot signal. To adjust the frequency and phase of the received signal. A representative example of such a reception device may be HD television.

In modern times, the GA (Grand Alliance) Committee has adopted and proposed VSB modulation as the modulation method of HDTV system. The VSB modulation method is used as a modulation method for analog video signals in conventional TV broadcasting, and is used for modulation of digital signals in HDTV of GA. Early Digital Spectrum Compatible (DSC)-In HDTV, 2-VSB and 4-VSB using 2 and 4 levels were selected as modulation methods, but 8-VSB and 8-VSB using 8 levels and high speed cable mode (high 16-VSB using 16 levels in the speed cable mode was selected as the modulation method.

In order to demodulate the VSB signal, the GA committee has proposed a schematic structure of a television receiver. The proposed television receiver has the following characteristics. First, unlike the demodulator of other digitally modulated signals, the VSB receiver detects data using only I-channel signals and performs sampling by symbol rate. Therefore, it is simpler to implement than QAM, which is used for VSB receiver Q (Quadrature) channel simultaneously. Since data is processed in silvolate, detection is possible even if the processing speed is relatively low compared to fractional rate receiver. The advantage is that it is possible. And GA HDTV receiver uses synchronous detection (coherent detection). The synchronous detection method has the advantage that it can be detected at a lower error rate at the same signal-to-noise ratio than the asynchronous detection method, but the structure of the receiver is complicated by the carrier recovery circuit. Therefore, accurate structure identification and optimization of the carrier recovery circuit is an essential problem. Therefore, the phase detection of the transmission signal for synchronous detection in the HDTV receiver of the GA committee consists of two phases using the frequency and phase locked loop (FPLL) and phase tracking loop (PTL) circuits. The FPLL recovers the carrier component by using the pilot signal included in the VSB signal of the GA committee. This FPLL can be easily implemented as a conventional PLL and frequency error detection event.

1 is a configuration diagram of a receiver for detecting a pilot signal and controlling a frequency and a phase, and shows a configuration of a carrier recovery circuit proposed by Zenith in the United States. Referring to FIG. 1, the tuner 111 receives a signal transmitted in a selected channel band and down-converts it to an intermediate frequency signal (hereinafter, referred to as IF). The filter 112 is a band pass filter for the received signal. The filter 112 filters and outputs a video signal and an audio signal band signal from the tuner 111. The filter 112 may use a SAW filter. The amplifier 113 amplifies and outputs the weak signal level output from the filter 112.

The oscillator 114 generates a predetermined oscillation frequency for demodulating the intermediate frequency output from the amplifier 113. The phase shifter 115 shifts the phase of the oscillation frequency output from the oscillator 114 by 90 ° and outputs it. The multiplier 116 mixes the intermediate frequency output from the amplifier 113 and the 90 ° phase shifted oscillation frequency output from the phase shifter 115 to output a demodulated signal. The demodulation signal output from the multiplier 116 becomes an I-channel signal, which is supplied to and processed by a signal processing means at a later stage. The multiplier 117 mixes the output of the amplifier 113 and the output of the oscillator 114 and outputs the Q channel signal. The first low pass filter 118 low-passes the I-channel signal which is the demodulation signal. A limiter 119 limits the signal output from the first low pass filter 118 to a predetermined size. The multiplier 120 mixes and outputs the Q channel signal output from the multiplier 117 and the processing signal of the I channel output from the limiter 119. At this time, the final signal output from the multiplier 120 has a value corresponding to the frequency and phase error, and this signal acts as an oscillation control signal for carrier recovery. The configuration as described above is a configuration of a frequency phase locked circuit (FPLL).

The second low pass filter 121 converts the control signal into a DC voltage by inputting a control signal output from the multiplier 120. The second low pass filter 121 may be a loop filter. The voltage controlled oscillator 122 is oscillated in accordance with the output of the second low pass filter 121 and is input to the control frequency of the tuner 111. The control frequency is a frequency generated to eliminate the frequency error.

Referring to the operation of the carrier recovery circuit having the configuration as shown in FIG. 1, when a frequency offset exists, the I-channel signal output to the multiplier 116 becomes a cosine waveform and is output from the multiplier 117. The Q channel signal becomes a sine waveform. The I-channel signal becomes a sinusoidal waveform when it passes through the first low pass filter 118 and the limiter 119. In this case, when the multiplier 120 multiplies the output of the Q channel signal and the limiter 119, the multiplier 120 appears as a DC signal. Therefore, the FPLL generates a DC signal corresponding to the offset amount of the frequency.

The DC signal according to the frequency offset is converted into a control voltage for removing a frequency error in the second low pass filter 121 which is a loop filter, and the voltage controlled oscillator 122 is oscillated by the control voltage and input to the tuner 111. In general, the VCO is in the tuner, so in this case, no VCO is required, and the output of the LPF2 is input to the tuner to control the oscillation frequency. When the above process is repeated and the frequency offset is removed, the output of the limiter 119 is fixed to 1 or -1 and only the Q channel signal is input to switch to the simple PLL mode to remove the residual phase error.

The carrier recovery circuit having the structure as described above performs an operation of removing a frequency error during an initial operation, and when the removal of the frequency error is completed, the carrier recovery circuit automatically switches to the PLL mode to perform an operation of removing a phase error.

However, in the carrier recovery circuit as shown in FIG. 1, the detection limit of the removable frequency error is limited by the first low pass filter 118. That is, when the frequency error of the received signal is large, the cosine wave having the frequency of the frequency error is lost through the first low pass filter 118. Therefore, when the error of the frequency is large, there is a problem in that it is not possible to accurately detect the n wave number and thus the frequency error cannot be removed. In addition, the carrier recovery circuit having the configuration as shown in FIG. 1 detects a pilot signal and removes an error of frequency and phase, and detects the pilot signal to remove an error of frequency and phase, wherein the pilot signal is the filter. If out of the bandwidth of 112, there was a problem that the carrier can not be recovered.

Accordingly, an object of the present invention is to provide a circuit and a method capable of stably recovering an error of a frequency and a phase of a received signal by extending an amount of frequency offset in a wireless receiver.

Another object of the present invention is to set a pilot frequency to a center frequency in a wireless receiver, and to provide a narrow band filter having a bandwidth of a desired frequency offset amount to stably detect a pilot signal, and to receive a signal using the detected pilot signal. To provide a circuit and method that can recover the error of the frequency and phase.

It is still another object of the present invention to provide a circuit and a method for detecting an offset amount of a frequency in a wireless receiver and automatically adjusting a frequency and a phase by selecting a carrier recovery circuit corresponding to the detected offset amount.

In order to achieve the objects of the present invention, a circuit for automatically adjusting errors of frequency and phase in a wireless receiver includes means for converting a received signal into an intermediate frequency by a control signal, and inputting the intermediate frequency to a pilot band. A first filter means for filtering out a signal of?, Means for inputting an output of the first filter means for generating an I channel signal and a Q channel signal, means for differentiating the I channel signal for generating a first detection signal; Means for low-pass filtering the I-channel signal to generate a second detection signal, means for detecting an error amount of frequency by inputting the detection signal, and generating a selection signal by comparing with a set reference value; Receives the output of the means and the second detection means, selects the output of the detection means corresponding to the selection signal and mixes with the Q channel signal to output the error detection signal. And means for converting the error detection signal into a control voltage and oscillating by the control voltage to generate a frequency for removing the frequency error and outputting the frequency to the intermediate frequency converting means as an error control signal. .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The term IF used below denotes an intermediate frequency of the signal band. PBS represents the first band signal filtered by the first filter 220 to detect the pilot signal at the intermediate frequency IF. SBS represents a second band signal filtered by the second filter 212 to detect a video signal and an audio signal at the intermediate frequency IF. EDS2 represents a second error detection signal obtained by low-pass filtering the I-channel signal of the first band signal. The LDS indicates a selection control signal for analyzing the second error detection signal and selecting the first error detection signal or the second error detection signal according to the amount of frequency error. EDS indicates a first error detection signal or a second error detection signal selected by the selection control signal. ECS represents an oscillated signal for adjusting the frequency error by the error detection signal. The DMS is a demodulation signal output from the multiplier 217 and represents an I channel signal of the second band signal.

2 shows a configuration of a circuit for automatically adjusting frequency and error in an apparatus for receiving a radio signal according to the present invention.

Referring to FIG. 2, the tuner 211 is connected between the antenna and the node N1 to receive a radio signal and to receive an error control signal ECS. The tuner 211 removes errors in frequency and phase of the signal received by the error control signal ECS, and down-converts the received signal to generate an intermediate frequency IF. The first filter 220 is connected to the node N1, inputs the intermediate frequency IF, filters the band of the pilot signal, and outputs the first band signal PBS. The first filter 220 uses a pilot frequency as a center frequency and a bandwidth as wide as a desired frequency offset. The first amplifier 221 amplifies the first band signal PBS and outputs the amplified signal to the node N3.

Oscillator 222 generates a predetermined oscillation frequency. A phase shifter makes the phase of the oscillation frequency more than 90 degrees. The multiplier 224 is connected between the nodes N3 and N4, and outputs the I-channel signal of the second band signal by mixing the output of the oscillator 222 and the second band signal PBS. The I-channel signal of the second band is cos Becomes The multiplier 225 mixes the output of the phase shifter 223 and the second band signal PBS to output the Q channel signal of the second band signal. The Q channel signal of the second band is sin Becomes A differentiator 226 is connected to the node N4 to differentially output the I channel signal of the second band signal PBS. The multiplier 227 inputs the output of the differentiator 227 and -1 to output the two input signals. The multiplier 227 inverts the phase of the signal outputting the differentiator 226. The signal output from the multiplier 227 is Becomes Limiter 228 limits the output of multiplier 227 to a predetermined size or less. The differentiator 226, multiplier 227 and limiter 228 serve as means for generating the first error detection signal EDS1. A first low pass filter 229 is connected to the node N4 and inputs an I channel signal of the first band signal PBS to low pass filter. The signal output from the first low pass filter 230 is sin Becomes The limiter 230 inputs the output of the first low pass filter 229 and filters the filter below a predetermined size. The first low pass filter 229 and the limiter 230 are means for generating the second error detection signal EDS2. The multiplexer 231 inputs the first error detection signal EDS1 and the second error detection signal EDS2 output from the limiters 228 and 230 to the first input terminal and the second input terminal, respectively, and the corresponding input signal is selected by the selection control signal LDS. Select to output the error detection signal EDS. The multiplier 233 mixes the Q channel signal of the first band signal PBS and the error detection signal EDS and outputs the DC signal corresponding to the frequency error.

The configuration as described above constitutes a frequency and phase locked loop (FPLL) according to the present invention.

The lock detector 232 is connected to the node N5 and inputs a second error detection signal EDS2 output from the limiter 230. The lock detector 232 analyzes the second error detection signal EDS2 and generates a selection control signal for selecting the first error detection signal EDS1 or the second error detection signal EDS2 according to the amount of the frequency error. 3 shows the configuration of the lock detector 232. As shown in FIG. Referring to FIG. 3, a zero-crossing detector 241 detects zero crossing of the second error detection signal EDS2 and generates a pulse signal. The counter 242 is a timer for setting the frequency error measurement period. The delay unit 243 performs a function of delaying the output of the counter 242 by a predetermined amount. The counter 244 counts and stores the output of the zero crossing detector 241 and is initialized by the output of the delayer 243. The register 245 loads and stores the output of the counter 244 by the output of the counter 242. The comparator 246 has a predetermined reference value, compares the output of the register 245 with the reference value, and outputs the resultant signal as the selection control signal LDS. In this case, when the output of the register 245 is greater than the reference value, one signal for selecting and outputting the first error detection signal EDS1 is output. .

The second low pass filter 234 inputs a DC signal output to the multiplier 233 and converts the DC signal into a control voltage. The second low pass filter 234 is a loop filter and is generated as a voltage for controlling a frequency error corresponding to the error detection signal EDS. The voltage controlled oscillator 235 inputs the output of the second low pass filter 234, generates an oscillation frequency according to the input control voltage, and outputs the oscillation frequency to the tuner 21 to control frequency and phase errors.

The second filter 212 connected to the node N1 filters the intermediate frequency IF output to the node N1 into a signal band and outputs a second band signal SBS. The second band signal SBS is a band including an audio signal and a video signal. The second filter 212 may use a SAW filter. The second amplifier 213 amplifies and outputs the second band signal SBS.

The voltage controlled oscillator 214 generates an oscillation frequency according to the received control voltage. Phase shifter 215 phase shifts the output of voltage controlled oscillator 214 by 90 degrees. A multiplier 217 is connected to the node N2, and mixes the output of the second band signal SBS and the voltage controlled oscillator 214 to generate an I-channel signal of a second band. The I-channel signal of the second band becomes a demodulation signal DMS. The multiplier 216 is connected to the node N2, and mixes the output of the second band signal SBS and the output of the phase shifter 215 to generate a Q-channel signal of a second band. The multiplexer 218 inputs 0 as a first input terminal, an output of the multiplier 216 as a second input terminal, and inputs the selection control signal LDS as a selection terminal. The multiplexer 218 selects and outputs the multiplier 216 or 0 according to the selection control signal LDS. The low pass filter 219 low-passes the output of the multiplexer 218 and applies it to the voltage controlled oscillator 214 as a control voltage. The configuration as described above is a configuration of the phase locked loop PLL.

Referring to the present invention based on the above configuration, the tuner 211 frequency-converts the received signal to the intermediate frequency IF and outputs it to the node N1. Then, the first filter 220 connected to the node N1 filters the intermediate frequency IF into a pilot frequency band and outputs a first band signal PBS. The first filter 220 sets a pilot signal as a center frequency and sets a bandwidth to a desired band according to the offset amount to be removed. The bandwidth of the first filter 220 may be set as a narrowband band pass filter having a 2MHz centering on the pilot signal. The first band signal PBS output from the first filter 220 is amplified by the first amplifier 221 and then applied to the node N3.

The process of automatically adjusting frequency and phase error by the FPLL circuit using the first band signal PBS of the detected pilot band will be described. First, the oscillator 222 generates a predetermined oscillation frequency. The phase shifter 223 outputs the phase of the oscillator 222 by 90 °. The multiplier 224 then mixes the first band signal PBS of the node N3 and the output of the oscillator 222 to generate an I-channel signal of a pilot signal band. The I-channel signal of the pilot band is cos Becomes The multiplier 225 mixes the output of the first band signal PBS and the output of the phase shifter 223 to generate a Q channel signal of a pilot signal band. The Q channel signal of the pilot signal band is sin Becomes

The I-channel signal of the pilot signal band output from the multiplier 224 is applied to the node N4. I channel signal cos of the node N4 Is differentiated at differentiator 226 and then phase-inverted at multiplier 227. Appears. The signal inverted in phase in the multiplier 227 is limited to a certain magnitude in the repeater 228 and then appears as a first error detection signal .EDS1. Here, the derivative of the I-channel signal generates a large signal proportional to the amount of frequency error. Therefore, the greater the frequency error, Since the power of a tone having a frequency of N is increased, the first error detection signal EDS1 output through the limiter 228 is a frequency error value. A square wave with the frequency of. Therefore, the first error detection signal EDS1 is generated when the frequency error is large, and when the frequency error is small, the first error detection signal EDS1 is buried in a noise or the like, making it difficult to detect.

In addition, the I-channel signal cos of the pilot signal band output from the multiplier 224 Is low-pass filtered by the first low pass filter 229 Appears. The signal output from the first low pass filter 229 is limited to a predetermined size at the limiter 230 and is represented by the second error detection signal EDS2. In this case, when the frequency error is greater than a predetermined value, the second error detection signal EDS2 is attenuated by the first low pass filter 229, and thus, the second error detection signal EDS2 is difficult to detect. Accordingly, it can be seen that the second error detection signal EDS2 is output as a signal in which zero crossing is frequently generated when the frequency error is large, and a signal in which zero crossing is small when the frequency error is small.

The first error detection signal EDS1 and the second error detection signal EDS2 generated as described above are input to the first input terminal and the second input terminal of the multiplexer 231, respectively. The multiplexer 231 selectively outputs an input signal by the selection control signal LDS output from the lock detector 232. In this case, the first error detection signal EDS1 is advantageously used when the frequency error is large, and conversely, the second error detection signal EDS2 is advantageously used when the frequency error is small. Therefore, it is preferable to select the first error detection signal EDS1 when the frequency error is large and to select the second error detection signal EDS2 when the frequency error is small. Therefore, the lock detector 232 analyzes the value of the error detection signal and selects and outputs the first error detection signal EDS1 when the frequency error is large, and selectively outputs the second error detection signal EDS2 when the frequency error is small. Signal EDS should be generated.

Referring to FIG. 3, the operation of the lock detector 232 will be described. The zero crossing detector 241 inputs the second error detection signal EDS2. At this time, it can be seen that the second error detection signal EDS2 is a signal in which zero crossing occurs frequently when the frequency error is large and zero crossing occurs little when the frequency error is small as described above. The zero crossing detector 241 detects time points at which the second error detection signal EDS2 is zero crossed and outputs them to the counter 244. The counter 244 then counts the number of zero crossings of the second error detection signal EDS2. At this time, the counter 242 performs a function of generating a predetermined periodic signal for selectively outputting the error detection signal EDS. Accordingly, while the counter 242 does not generate an output signal, the counter 244 counts and stores the zero crossing signal detected by the zero crossing detector 244. Thereafter, when the count end signal is generated by the counter 242, the register 245 loads and stores the zero crossing count of the second error detection signal EDS2 accumulated in the counter 244. The counter 244 is initialized by the count end signal of the counter 242 generated by the delay 243 to prepare for counting the number of zero crossings generated in the next period. Accordingly, it can be seen that the delayer 243 performs a function of compensating for the time when the register 245 can load the output of the counter 244. The output of the register 245 is applied to the comparison input terminal of the comparator 246. In this case, the comparator 246 inputs a predetermined reference value to the reference input terminal. Here, the reference value is set to a value that can be in a frequency and phase simultaneous state even when zero crossing of the second error detection signal EDS2 occurs during a set period. Accordingly, the comparator 246 compares the output of the register 245 with the reference value and compares the reference value with the zero crossing number of the second error detection signal EDS2 to generate a frequency when the zero crossing number of the second error detection signal EDS2 is greater than or equal to the reference value. The second logic selection control signal LDS of the second logic detection signal EDS, which indicates that the error is large and the zero error number of the second error detection signal EDS2 is less than the reference value, indicates that the frequency error is small. Outputs

The selection control signal LDS generated as described above is output to the selection terminal of the multiplexer 231. Accordingly, the multiplexer 231 selects and outputs the first error detection signal EDS1, which is received at the first input terminal by the first logic selection control signal LDS generated when the frequency error is large, as the error detection signal EDS, and when the frequency error is small. The second error detection signal EDS2 received by the second input terminal by the generated second selection control signal LDS is output as an error detection signal EDS. The multiplier 233 then mixes the Q-band signal of the pilot band and the error detection signal EDS to generate a DC signal corresponding to the frequency error.

As described above, the DC signal outputting the multiplier 233 has a magnitude corresponding to the frequency error, and the DC signal is generated as the oscillation signal ECS for removing the frequency error by the second low pass filter 234 and the voltage controlled oscillator 225. Is applied to tuner 211. Therefore, the tuner 211 automatically adjusts the frequency and phase error by the oscillation signal ECS.

In addition, the bandwidth of the second filter 212 connected to the node N1 is set to a bandwidth for filtering video and audio signals. Therefore, the center frequency IF output to the node N1 is filtered by the second filter 212 into the signal band and output as the second band signal SBS, and the second amplifier 213 amplifies and outputs the second band signal SBS. In this case, the first band signal PBS and the second band signal SBS have different delay times according to the filter characteristics of the first filter 32 and the second filter 37. Therefore, there is a delay difference between the carrier recovery path and the main path of the signal. The PLL is used to compensate for the phase error caused by the delay difference between the two passes.

Referring to the operation of the PLL, the voltage controlled oscillator 214 generates an oscillation frequency that varies according to the oscillation control voltage generated by the low pass filter 219. The phase shifter 215 shifts the output of the voltage controlled oscillator 214 by 90 °. The multiplier 217 mixes the output of the voltage controlled oscillator 214 and the second band signal SBS to generate an I-channel signal of a signal band. The I-channel signal of the signal band is a demodulation signal DMS, which is input to and processed by a signal processing unit at a later stage. The multiplier 216 mixes the output of the second band signal SBS and the phase shifter 215 to generate a Q-channel signal of a signal band.

At this time, the multiplexer 218 inputs the output of the multiplier 218 as a second input terminal and 0 as a first input terminal, and the selection terminal is connected to the selection control signal LDS. Therefore, the multiplexer 218 selects and outputs 0 when the selection control signal is output in the first logic, and selects and outputs the Q channel signal of the signal band when output in the second logic. In other words, it can be seen that when the frequency error is large, 0 is selected and outputted, so that the PLL is free runnig, and when the frequency error is small, the phase synchronization operation is activated by the Q channel signal of the signal band. Accordingly, it can be seen that the demodulation signal DMS is automatically controlled according to the amount of the frequency error.

As described above, in a wireless receiver for controlling misalignment of frequency and phase by using a pilot signal, a plurality of means for generating an error detection signal according to the magnitude of the frequency error are provided and corresponding to the amount of error of the detected frequency. There is an advantage that the frequency and phase can be automatically adjusted by selecting the error detection signal.

Claims (5)

A carrier recovery circuit of a radio receiver, comprising: means for converting a received signal into an intermediate frequency by a control signal, first filter means for inputting the intermediate frequency to filter out a pilot band signal, and the first filter means Means for generating an I-channel signal and a Q-channel signal by inputting an output of the signal, means for generating a first detection signal by differentiating the I-channel signal, and generating a second detection signal by low-pass filtering the I-channel signal. Means, inputting the detection signal to detect an error amount of a frequency, generating a selection signal by comparison with a set reference value, receiving outputs of the first detection means and the second detection means, Means for selecting an output of a corresponding detection means, mixing the Q channel signal with an output of an error detection signal, and converting the error detection signal into a control voltage and It is the oscillation frequency and phase automatic control circuit, characterized in that the means for outputting is configured as an error control signal to the intermediate frequency conversion means to generate the frequency to eliminate the frequency error. 2. The apparatus of claim 1, wherein the means for generating a selection signal comprises: means for inputting the second detection signal to detect and store a zero crossing; and loading the zero crossing detection frequency at a predetermined period, and comparing with a predetermined reference value to zero. And means for generating a selection signal for selecting the first detection signal when the number of times of crossing detection is greater than an additive reference value. A carrier recovery circuit of a radio receiver, comprising: means for converting a received signal into an intermediate frequency by a control signal, first filter means for inputting the intermediate frequency to filter a first band signal of a pilot signal, and the first signal; Means for generating an I-channel signal and a Q-channel signal by inputting the output of the first filter means, means for generating the first detection signal by differentiating the I-channel signal, and low-pass filtering the I-channel signal for the second detection signal. Means for generating a signal; detecting the amount of error in frequency by inputting the detection signal; generating a selection signal by comparison with a set reference value; receiving outputs of the first detection means and the second detection means; Means for selecting an output of the detection means corresponding to the selection signal, mixing the Q channel signal and outputting it as an error detection signal, and converting the error detection signal to a control voltage and before controlling. A second filter for generating a frequency for removing the frequency error by oscillation by pressure and outputting the frequency control signal to the intermediate frequency converting means as an error control signal, and filtering the second band signal of the signal band by inputting the intermediate frequency. Means, inputting the output of the second filter means to generate an I-channel signal and a Q-channel signal, receiving the Q-channel signal and zero data, and selecting a signal input by the selection signal to select an I-channel A frequency and phase automatic adjustment circuit comprising a phase ceramic loop means for generating a signal. 4. The apparatus according to claim 3, wherein the means for generating a selection signal comprises means for inputting the second detection signal to detect and store zero crossing, and load the zero crossing detection frequency at a predetermined period, and compare it with a predetermined reference value to zero. And means for generating a selection signal for selecting the first detection signal when the number of times of crossing detection is greater than an additive reference value. A method for recovering a carrier of a wireless receiver, the method comprising: converting a received signal into an intermediate frequency, filtering a band of a pilot signal at the intermediate frequency, and generating an I-channel signal and a Q-channel signal from the pilot band signal. And generating a first error detection signal by differentiating the I-channel time signal, generating a second error detection signal by low-pass filtering, and analyzing the error detection signal to detect an error amount of frequency, and setting a reference value. Generating a selection signal in comparison with the control signal; and selecting a detection signal corresponding to the first error detection signal and the second error detection signal according to the selection signal, and mixing the detected signal with the Q channel signal to output an error detection signal; And an error agent for removing the frequency error generated during the intermediate frequency change process after converting the error detection signal into a control voltage. Generated by the intermediate frequency changing process repeated the course of how the frequency and phase, characterized by automatic control constituted by any of the signals.