JPH1041992A - Quasi-synchronization detection demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate both an error component of an orthogonal modulator side and an orthogonal demodulator side by compensating an error in a DC offset and a gain of a base band signal subject to orthogonal detection and applying DC offset error compensation and gain error compensation to a signal subject to carrier synchronization. SOLUTION: The demodulator is provided with a compensation circuit 30 applying DC offset error compensation and gain error compensation to an output signal from a phase compensation circuit 3. Then base band signals of I and Q channels converted into digital signals after orthogonal detection are given to a digital adder IF and a digital multiplier 2F of a compensation circuit 20, in which DC offset error compensation and gain error compensation are conducted and the phase compensation circuit 3 conducts carrier synchronization. Furthermore, a digital adder 1B and a digital multiplier 2B of the compensation circuit 30 conduct DC offset error compensation and gain error compensation for each channel. Then the demodulation signal whose inter-code interference is eliminated by an equalizer 4 is given to a discrimination circuit 5, from which an identification signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for wireless communication using a quadrature modulated signal. The present invention relates to compensation of an error component in a quadrature demodulator that demodulates a digitally modulated signal using digital signal processing.

[0002]

2. Description of the Related Art A conventional quasi-coherent detection type demodulator is shown in FIG.
This will be described with reference to FIG. FIG. 10 is a block diagram of a conventional quasi-coherent detection type demodulator. The digital quadrature modulation signal is subjected to quadrature detection, converted into a digital signal, and input to an input terminal in as an I channel and a Q channel signal. DC offset error compensation (AOC) is performed in the digital adder 1, gain error compensation (AGC) is performed in the digital multiplier 2, carrier synchronization is performed in the phase compensation circuit 3, and intersymbol interference is reduced via the equalizer 4. The removed demodulated signal is obtained. Further, the demodulated signal is input to the determination circuit 5, and an identification signal is obtained at the output terminal out. Here, in the phase compensating circuit 3, the amplitudes sequentially output according to the phase information signal output from the carrier reproducing circuit 9 by the waveform ROMs 8-1 and 8-2 storing the amplitude information corresponding to the phase of the orthogonal carrier signal. Using the value, I ′ = I · cos θ + Q · sin θ (1-1) By performing the operation of Q ′ = Q · cos θ−I · sin θ (1-2), the signal phase is rotated to perform carrier phase compensation. Do.

On the other hand, drift and gain error components are:
A demodulated signal is used to increase detection accuracy, and detection is performed by taking a difference from the identification signal. At this time, since the phases of the demodulated signal and the input signal are different, the demodulated signal and the identification signal are reproduced carrier wave (waveform RO) delayed by the delay circuit 10 by the output delay time of the phase compensation circuit 3 and the equalizer 4.
Using the output signal from M), the demodulated signal and the input signal are inversely transformed by the phase inverse compensation circuit 11 so as to have the same phase.

[0004]

In the synchronous detection system in which carrier synchronization is performed in the intermediate frequency (IF) band, since the phase compensation of the signal is not performed in the base band, the detection of the offset component and the gain error component for each channel is performed. Compensation can be made. However, in a quasi-synchronous detection type demodulator, carrier synchronization is generally performed by rotating the phase of a baseband signal with respect to a frequency error component included in a signal subjected to quadrature detection using a fixed oscillator. Therefore, the error component included in the demodulated signal is different from the error component included in the input signal, and the DC offset error component and the gain error component after the phase compensation are as follows.

The DC offset error components (β _I , β _Q ) and gain error components (α _I , α _Q ) on the quadrature modulator side and the DC offset error components (β _RI , β _RQ ) and gain error components on the quadrature demodulator side The orthogonally detected signal including the components (α _RI , α _RQ ) is given by the following equation. Ich: alpha _{RI [(α I D I + β I} ) cos (Δωt) - (α Q D Q + β Q) sin (Δωt) ] _{+ β RI ·· (2-1) Qch} : α RQ [(α _I D _I + Β _I ) sin (Δωt) + (α _Q D _Q + β _Q ) cos (Δωt)] + β _RQ (2-2) where Δω is a frequency offset and DI and DQ are I
ch and Qch data signals.

In the equations (2-1) and (2-2), there is no gain error component (α _I = α _Q = α _RI = α _RQ = 1).
Is given by the following equation. Ich: (D _I + β _I ) + β _RI cos (Δωt) + β _RQ sin (Δωt) (3-1) Qch: (D _Q + β _Q ) −β _RI sin (Δωt) + β _RQ cos ( Δωt) (3-2) As can be seen from equations (3-1) and (3-2), the DC offset error component generated on the quadrature modulator side is fixed to each channel after phase compensation. The DC offset error component generated in the analog processing circuit on the quadrature demodulator side becomes an error component that rotates around the identification signal point after phase compensation. Conversely, an error on the side of the quadrature modulator becomes a rotational component in a stage preceding the phase compensation circuit 3. In order to compensate for these two different error components, the fixed component and the rotational component must be separately compensated. Therefore, in the compensating circuit 28 as shown in the prior art, it is possible to apply only under the condition that the error component on the quadrature modulator side can be ignored, but under the condition that the error component on the quadrature modulator side cannot be ignored. It is difficult to simultaneously compensate for the error on the quadrature modulator side and the error on the quadrature demodulator side.

In the equations (2-1) and (2-2),
Condition without DC offset error component (β _I = β _Q = β _RI
= Β _RQ = 0) is given by the following equation. _{Ich: α I α Rav D I} - α Rd _{[α I D I cos (2Δωt)} -α Q D Q sin (2Δωt) ] _{···· (4-1) Qch: α Q} α Rav D Q + α Rd _{[α Q D Q cos (2Δωt)} + α I D I sin (2Δωt) ] _{···· (4-2) α Rav = (} α RI + α RQ) / 2, α Rd = (α RQ -α RI) / 2 As can be seen from the equations (4-1) and (4-2), regarding the gain error component, after the phase compensation, the difference between the gain error components between the channels on the quadrature demodulator side rotates according to the frequency offset. . Conversely, at the stage before the phase compensation circuit 3, the difference between the amplitude error components on the quadrature modulator side becomes the rotation component. In this case as well, similarly, it is difficult for the compensation circuit 28 shown in the related art to simultaneously compensate the quadrature modulator side error and the quadrature demodulator side error.

The present invention has been made in such a background, and provides a quasi-synchronous detection and demodulation device capable of compensating for both an error component on the quadrature modulator side and an error component on the quadrature demodulator side. With the goal. SUMMARY OF THE INVENTION It is an object of the present invention to provide a quasi-synchronous detection and demodulation device that can obtain a demodulated signal and an identification signal with small errors.

[0009]

In the present invention, the above problem is solved by disposing a compensating circuit before and after a phase compensating circuit for compensating the phase of a quadrature detection signal. The DC offset error component and the gain error component generated on the modulator side are compensated by detecting them from the demodulated signal and the identification signal or the demodulated signal and the identification signal, which are subjected to antiphase compensation, and are generated on the quadrature modulator side in the post-stage compensation circuit. The problem is solved by performing compensation by detecting a DC offset error component and a gain error component from a demodulated signal and an identification signal.

Also, as shown in the equations (4-1) and (4-2), the gain error component is a rotating error component in which the difference between the channels of the gain error component generated on the quadrature demodulator side becomes a rotating error component. The compensation circuit compensates for the difference between the channel of the DC offset error component generated on the quadrature demodulator side and the gain error component generated on the quadrature demodulator side. The above problem can also be solved by using means for compensating for the offset error component, the gain error component, and the average value of the gain error component generated on the quadrature demodulator side.

Further, when a quadrature modulated signal is subjected to quadrature detection using digital signal processing, a difference between channels of a gain error component generated on the quadrature demodulator side can be ignored.
The DC offset error component also has the same value. For this reason, the compensating circuit in the preceding stage compensates for the DC offset error component generated in the quadrature demodulator side by giving control counts to both channels, and the compensating circuit in the subsequent stage composes the quadrature modulator side and the quadrature demodulator side. The above problem can also be solved by compensating for the gain error component generated in step (1) and the DC offset component generated on the quadrature modulator side.

That is, the present invention relates to a quasi-synchronous detection type demodulation device, wherein an input terminal to which quadrature-detected I-channel and Q-channel baseband signals are respectively inputted;
The quasi-synchronous detection type demodulator includes a first compensation circuit for compensating for a DC offset error and a gain error of the signal, and a phase compensation circuit for performing carrier synchronization of the signal. A feature of the present invention resides in that a second compensation circuit for compensating for a DC offset error and a gain error of an output signal of the phase compensation circuit is provided.

Alternatively, input terminals to which I- and Q-channel baseband signals subjected to quadrature detection are respectively inputted, a first compensation circuit for compensating for a DC offset error of the signals, and carrier synchronization of the signals. A quasi-synchronous detection type demodulator comprising a phase compensating circuit and a second compensating circuit for performing DC offset error compensation and gain error compensation of an output signal of the phase compensating circuit. It is in the prepared place. At this time, it is desirable to provide a means for performing gain error compensation on one of the channels so that the gain errors of the I channel and the Q channel are relatively equal for each channel.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

[0015]

【Example】

(First Embodiment) The structure of the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an overall configuration diagram of an embodiment of the present invention. FIG. 2 is a block diagram of the first embodiment of the present invention.

As shown in FIG. 1, the I-channel and Q-channel data signals are input to a quadrature modulator 40, quadrature-modulated, and transmitted via a transmitting device 42 and an antenna ANT1. Antenna ANT2 and receiving device 44
Are input to a quadrature demodulator 49 and become a baseband signal subjected to quadrature detection by a quadrature detector 46 driven by a local oscillator 48.
The baseband signal subjected to the quadrature detection is input to the quasi-synchronous detection / demodulation device 50 of the present invention, and the I-channel and Q-channel data signals are reproduced. The value of n in the I-channel and Q-channel data signals is 4QAM (Quadrature Amplitude Modulation) if n = 1, n = 2
If so, 16 QAM, and if n = 4, 256 QAM.

That is, the present invention relates to a quasi-synchronous detection type demodulator 50, as shown in FIG. 2, which has input terminals in to which I-channel and Q-channel baseband signals subjected to quadrature detection are inputted, respectively. First compensation circuit 20 for performing DC offset error compensation and gain error compensation of a signal
And a quasi-synchronous detection and demodulation device 50 including a phase compensation circuit 3 for performing carrier synchronization of the signal.

Here, the feature of the present invention resides in that a second compensation circuit 30 for compensating for a DC offset error and a gain error of the output signal of the phase compensation circuit 3 is provided.

The compensation circuit 20 includes a digital adder 1F for compensating for a DC offset error of the quadrature modulation signal, a digital multiplier 2F for compensating for a gain error of the quadrature modulation signal, a loop filter 6F, and an error detection circuit 7F. The compensation circuit 30 includes a digital adder 1B for compensating for a DC offset error of the quadrature modulated signal after carrier synchronization, a digital multiplier 2B for compensating for a gain error of the quadrature modulated signal after carrier synchronization, a loop filter 6B, and an error detection circuit 7B. It has. Thus, in the first embodiment of the present invention, the compensation of the error component on the side of the quadrature demodulator 49 is performed by the compensation circuit 20, and the compensation of the error component on the side of the quadrature modulator 40 is performed by the compensation circuit 3.
Performed with 0.

The operation of the first embodiment of the present invention will be described.
In the first embodiment of the present invention, the quadrature modulated signal received by the receiving device 44 is
The I-channel and Q-channel signals converted to digital signals after quadrature detection are input, and DC offset error compensation is performed using a digital adder 1F.
After performing gain error compensation for each channel using the digital multiplier 2F, carrier synchronization is performed in the phase compensation circuit 3, and then DC offset error compensation is further performed using the digital adder 1B.
Using B, gain error compensation is performed for each channel. Then, a demodulated signal from which intersymbol interference has been removed is obtained via the equalizer 4. Further, the demodulated signal is input to the determination circuit 5, and the identification signal is output to the output terminal out. here,
Carrier regeneration is performed by the same calculation as in the conventional example. The demodulated signal and the identification signal are directly input to the compensation circuit 30. Further, the compensation circuit 20 receives as input the demodulated signal and the identification signal obtained by performing the phase rotation operation in the phase inverse compensation circuit 11 opposite to that of the phase compensation circuit 3.

Error detection circuit 7 used in the first embodiment of the present invention
F and 7B will be described with reference to FIG. FIG. 3 shows error detection circuits 7F and 7B used in the first embodiment of the present invention.
FIG. 3 is a block diagram of the configuration of FIG. Error detection circuit 7F shown in FIG.
And 7B have ZF (Zero-forc
ing) method is shown below. In FIG. 3, the error signal component of each channel is obtained by taking the difference between the input demodulated signal and the identification signal. The DC offset error compensation is performed by using the polarity of the error signal component as a DC offset error signal and providing control coefficients obtained by integrating the DC offset error signal in the loop filters 6F and 6B to the digital adders 1F and 1B. Will be On the other hand, a gain error signal for gain error compensation is detected by an exclusive OR (I-sign and I-error, Q-sign and Q-error) of the polarity of the error signal component and the polarity of the identification signal. The gain error compensation is performed by inputting control coefficients obtained by integrating gain error signals using loop filters 6F and 6B to digital multipliers 2F and 2B.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram of the second embodiment of the present invention. In the device according to the second embodiment of the present invention, in order to increase the stability of the control system, the gain error compensation at the preceding stage of the phase compensation circuit 3 is to absorb the error component difference between channels that appears as a rotation component after quadrature demodulation. And the digital multiplier 2F is arranged only in one of the channels.

The average value of the gain error component on the quadrature demodulator 49 side in each channel is added to the error component on the quadrature modulator 40 side, so that it can be interpreted as the same component. Therefore, in the first embodiment of the present invention, the compensation circuit 2
If both the compensation circuit 30 and the compensation circuit 30 attempt to compensate for the gain error component on the side of the quadrature demodulator 49, the control may be unstable due to restrictions on the circuit configuration such as the delay time of the loop. From the above equations (4-1) and (4-2), if there is no rotating component, the compensation can be made only by the gain error compensation after the phase compensation.

That is, the apparatus of the second embodiment of the present invention includes an I-channel and a Q-channel obtained by converting a quadrature modulated signal received by the receiver 44 into a digital signal which has been quadrature detected by a local oscillator 48 having a fixed frequency. A signal is input, DC offset error compensation is performed for each channel using a digital adder 1F, and gain error compensation is performed using a digital multiplier 2F arranged only for one channel. , The DC offset error compensation is further performed using the digital adder 1B, and the gain error compensation is performed for each channel using the digital multiplier 2B. Then, a demodulated signal from which intersymbol interference has been removed is obtained via the equalizer 4. Further, the demodulated signal is input to the determination circuit 5, and the identification signal is output to the output terminal out. Here, carrier regeneration is performed by the same calculation as in the conventional example.

The demodulated signal and the identification signal are directly input to the compensating circuit 30. The error detecting circuit 7B shown in FIG. 3 in the first embodiment of the present invention is used, and the latter compensating circuit described in the first embodiment of the present invention. The same compensation operation as in 30 is performed.

The pre-compensation circuit 22 used in the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of the error detection circuit 12F of the pre-compensation circuit 22 used in the second embodiment of the present invention. The demodulated signal and the identification signal that have been subjected to the phase rotation operation opposite to that of the phase compensation circuit 3 in the phase compensation circuit 11 are input to the compensation circuit 22 in the preceding stage.

The error detection circuit 12F shows an example in which the ZF method is used as a control algorithm. The error signal component of each channel is obtained by taking the difference between the input demodulated signal and the identification signal. The DC offset error compensation is performed by using the polarity of the error signal component as a DC offset error signal, and giving a control coefficient obtained by integrating the DC offset error signal in the loop filter 6F to the digital adder 1F. On the other hand, the gain error compensation here is performed to absorb the difference between the amplitude error components between the channels. Therefore, in the error signal detection process, the gain error signal of each channel obtained by the exclusive OR (I-sign and I-error, Q-sign and Q-error) of the polarity of the error signal component and the polarity of the identification signal. Ask for. Then, a control coefficient obtained by integrating the output signal from the error detection circuit 12F using the loop filter 6F is input to the digital multiplier 2F.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram of the device according to the third embodiment of the present invention. The third embodiment of the present invention is a configuration in which quadrature detection is realized by digital signal processing, and a gain error compensation is arranged only in a stage subsequent to the phase compensation circuit 3. Also, regarding the DC offset error compensation, since there is no difference in the DC offset error component between the channels, they are controlled with the same coefficient.

The reason for this is that when quadrature detection is performed by digital processing, there is no difference between the channels with respect to the gain error component (in Equations (4-1) and (4-2), the second term is eliminated, and Only one term), the rotating component no longer exists, and there is only a fixed component. Therefore, only by arranging the gain error compensation after the phase compensation, the quadrature modulator 40
And the component on the side of the quadrature demodulator 49 can be simultaneously compensated.

The device according to the third embodiment of the present invention includes a receiving device 44.
After the quadrature modulated signal received by is converted into a digital signal, I-channel and Q-channel signals subjected to quadrature detection by digital signal processing are input, and DC offset error compensation is performed for each channel using a digital adder 1F. After that, carrier synchronization is performed in the phase compensation circuit 3, and then DC offset error compensation is further performed using the digital adder 1B, and gain error compensation is performed for each channel using the digital multiplier 2B. Then, a demodulated signal from which intersymbol interference has been removed is obtained via the equalizer 4. Further, the demodulated signal is input to the determination circuit 5 and an identification signal is output to an output terminal out. Here, carrier regeneration is performed by the same calculation as in the conventional example.

The demodulated signal and the identification signal are directly input to the compensating circuit 30 at the subsequent stage, and are used in the first embodiment of the present invention.
The same compensation operation as the compensation circuit 30 in the latter stage of the first embodiment of the present invention is performed using the error detection circuit 7B.

The error detection circuit 13F of the pre-compensation circuit 24 used in the third embodiment of the present invention will be described with reference to FIG.
FIG. 7 is a block diagram of the error detection circuit 13F used in the third embodiment of the present invention. The demodulated signal and the identification signal obtained by performing the phase rotation operation opposite to that of the phase compensation circuit 3 in the phase inverse compensation circuit 11 are input to the compensation circuit 24 in the preceding stage, and the compensation operation is performed using the error detection circuit 13F in FIG. Done.
An example in which the ZF method is used as a control algorithm will be described.

In the error detection circuit 13F, the error signal component is obtained by taking the difference between the input demodulated signal and the identification signal. Further, at this time, in a signal orthogonally detected using digital signal processing, when orthogonal detection is performed by analog signal processing, a difference between channels of a DC offset error generated due to variations in circuit characteristics and the like can be ignored. . Therefore, the DC offset error compensation here is performed by obtaining a DC offset error signal by adding error signal components obtained for each channel, and integrating a control coefficient obtained by integrating this signal using a loop filter 6F. At the same time to the digital adders 1F of both channels. On the other hand, the gain error compensation ignores the difference between channels of the amplitude error caused by variations in circuit characteristics and the like when quadrature detection is performed by analog signal processing in a signal that has been quadrature detected using digital signal processing. Therefore, the control in the preceding stage is not performed.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram of a device according to the fourth embodiment of the present invention. The device of the fourth embodiment of the present invention is obtained by simplifying the configuration of the device of the third embodiment of the present invention shown in FIG. Here, the circuit scale is reduced by omitting the phase reverse compensation circuit 11. The signal processing from the input of the signal until the demodulated signal and the identification signal are obtained is the same as in the third embodiment of the present invention.

The demodulated signal and the identification signal are directly input to the compensating circuit 30 in the latter stage of the fourth embodiment of the present invention, and the error detecting circuit 7B of the first embodiment of the present invention is used. A compensation operation is performed.

The pre-compensation circuit 26 of the fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram of an error detection circuit 14F used in the fourth embodiment of the present invention. The demodulation signal and the identification signal are directly input to the compensation circuit 26 at the preceding stage, and the carrier reproduction circuit 9
Is also input, and the compensation operation is performed using the error detection circuit 14F shown in FIG.
An example in which the ZF method is used as an algorithm will be described.

In FIG. 9, the error signal component of each channel is obtained by calculating the difference between the input demodulated signal and the identification signal. At this time, the DC offset error polarity is converted as shown in Table 1 according to the phase rotation amount in the phase compensation circuit 3.

[0038]

[Table 1] Therefore, by selecting the error signal (I-error, Q-error) and the polarity inversion signal [1] using the carrier phase control information signal, the DC offset error signal corrected for the phase rotation is obtained. It has gained.

[0039]

[Outside 1] (Summary of Embodiment) As described above, the compensation circuits 20, 22, 24, 26 and 30 are provided before and after the phase compensation circuit 3, respectively.
The quasi-synchronous detection demodulator capable of compensating for both the error component generated on the quadrature modulator side and the error component generated on the quadrature demodulator side can be realized by arranging. For this reason,
In the conventional example, it is possible to reduce the deterioration of the error rate characteristic caused by the error component on the side of the quadrature modulator not being sufficiently compensated.

In general, when a large number of control loops are formed as in the present invention, there is a problem that control becomes unstable. Also in this configuration, when the frequency offset amount is small, it is considered that the control becomes unstable because almost the same control is performed in the former stage and the latter stage. However, the compensation circuits 20, 2
Since 2, 24, 26 and 30 are controls proportional to the frequency offset amount, the control circuit output from the carrier recovery circuit 9 is used to control the pre-stage or post-stage compensation circuit 2.
ON / OF of control of 0, 22, 24, 26 and 30
F. Since the control coefficient can be easily held, this problem can be easily avoided by performing this control according to the frequency offset amount. Further, since this configuration is realized by all digital circuits, these controls can be easily realized. For the above reasons, in the present invention, stable error compensation is possible even when a large number of control loops are formed.

[0041]

As described above, according to the present invention,
A quasi-synchronous detection demodulator capable of compensating for both the error component on the quadrature modulator side and the error component on the quadrature demodulator side can be realized. Therefore, a demodulated signal and an identification signal with few errors can be obtained.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of the first embodiment of the present invention.

FIG. 3 is a block diagram of an error detection circuit of a pre-compensation circuit used in the first embodiment of the present invention.

FIG. 4 is a block diagram of a device according to a second embodiment of the present invention.

FIG. 5 is a block diagram of an error detection circuit of a pre-compensation circuit used in a second embodiment of the present invention.

FIG. 6 is a block diagram of a device according to a third embodiment of the present invention.

FIG. 7 is a block diagram of an error detection circuit of a pre-compensation circuit used in a third embodiment of the present invention.

FIG. 8 is a block diagram of a device according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram of an error detection circuit of a pre-compensation circuit used in a fourth embodiment of the present invention.

FIG. 10 is a block diagram of a conventional quasi-synchronous detection and demodulation device.

[Explanation of symbols]

1, 1F, 1B, 133 Digital adder 2, 2F, 2B Digital multiplier 3 Phase compensation circuit 4 Equalizer 5 Judgment circuit 6, 6F, 6B Loop filter 7, 7F, 7B, 12F, 13F, 14F Error detection circuit 8-1 Waveform ROM (sin function) 8-2 Waveform ROM (cos function) 9 Carrier reproduction circuit 10 Delay circuit 11 Phase reverse compensation circuit 20, 22, 24, 26, 28, 30 Compensation circuit 40 Quadrature modulator 42 Transmitting device 44 Receiving device 46 Quadrature detector 48 Local oscillator 49 Quadrature demodulator 50 Quasi-synchronous detection demodulator 71, 121, 124, 131 Digital subtractor 72, 122, 132 Polarity circuits 73, 123, Exclusive OR circuit ANT1, ANT2 Antenna in Input terminal out Output terminal

Claims (3)

[Claims] An input terminal to which quadrature-detected I-channel and Q-channel baseband signals are respectively input, a first compensation circuit for performing DC offset error compensation and gain error compensation of the signal, A quasi-synchronous detection type demodulator including a phase compensation circuit for performing carrier synchronization, comprising a second compensation circuit for performing DC offset error compensation and gain error compensation of an output signal of the phase compensation circuit. Quasi-synchronous detection and demodulation device. 2. An input terminal to which quadrature-detected I-channel and Q-channel baseband signals are respectively inputted, a first compensation circuit for compensating a DC offset error of the signals, and a carrier synchronization of the signals. A quasi-synchronous detection type demodulator comprising: a phase compensation circuit; and a second compensation circuit for performing DC offset error compensation and gain error compensation of an output signal of the phase compensation circuit. apparatus. 3. The quasi-synchronous detection and demodulation device according to claim 2, further comprising means for performing gain error compensation on one of the I and Q channels so that the gain error of each channel is relatively equal.