JP4292667B2 - Receiving apparatus and method thereof - Google Patents

Description

【００４５】
図３は、複素乗算回路３０の構成図である。
図３に示すように、複素乗算回路３０は、乗算回路６０，６１，６２，６３および加算回路６４，６５を有する。
複素乗算回路３０では、図１に示す補間回路２９からのＱ信号Ｓ２９が、乗算回路６０および６１に入力される。
また、図１に示す補間回路２８からのＩ信号Ｓ２８が、乗算回路６２および６３に入力される。
また、信号変換回路３６からのＳＩＮ特性の信号Ｓ３６が、乗算回路６１および６３に出力される。
また、信号変換回路３７からのＣＯＳ特性の信号Ｓ３７が、乗算回路６０および６２に出力される。
【００４６】
そして、乗算回路６０において、Ｑ信号Ｓ２９と信号Ｓ３７との乗算が行われ、当該乗算結果の信号Ｓ６０が加算回路６５に出力される。
また、乗算回路６１において、Ｑ信号Ｓ２９と信号Ｓ３６との乗算が行われ、当該乗算結果の信号Ｓ６１が加算回路６４に出力される。
また、乗算回路６２において、Ｉ信号Ｓ２８と信号Ｓ３７との乗算が行われ、当該乗算結果の信号Ｓ６２が加算回路６４に出力される。
また、乗算回路６３において、Ｉ信号Ｓ２０と信号Ｓ４３との乗算が行われ、当該乗算結果の信号Ｓ６３が加算回路６５に出力される。
【００４７】
そして、加算回路６５において、信号Ｓ６０から信号Ｓ６３が減算され、その減算結果がＱ信号Ｓ３０ｂとなる。
また、加算回路６４において、信号Ｓ６１と信号Ｓ６２とが加算され、その加算結果がＩ信号Ｓ３０ａとなる。
【００４８】
ロールオフフィルタ回路３１は、Ｉ信号Ｓ３０ａに符号間干渉を低減するためのフィルタ処理を行ってＩ信号Ｓ３１を生成し、これを位相検出回路３３、軟判定回路４５、シンボルタイミング再生回路４６およびＡＧＣ回路４７に出力する。
ロールオフフィルタ回路３２は、Ｑ信号Ｓ３０ｂに符号間干渉を低減するためのフィルタ処理を行ってＱ信号Ｓ３２を生成し、これを位相検出回路３３、軟判定回路４５、シンボル再生回路４６およびＡＧＣ回路４７に出力する。
なお、本実施形態では、ロールオフフィルタ回路３１，３２をコスタスループ５５内に構成した場合を例示したが、これらを補間回路２８，２９の直後に設置してもよい。
【００４９】
位相検出回路３３は、Ｉ信号Ｓ３１およびＱ信号Ｓ３２によって決まる位相を検出し、当該位相を示す位相信号Ｓ３３をループフィルタ回路３４に出力する。
【００５０】
ループフィルタ回路３４は、位相信号Ｓ３３の高域成分を除去して位相信号Ｓ３４を生成し、これを数値制御発振回路３５に出力する。
【００５１】
数値制御発振回路３５は、オーバーフローを禁止しない累積加算回路であり、位相信号Ｓ３４の値に応じてそのダイナミックレンジまでの加算動作を行って発振状態となり、位相信号Ｓ３４の値に応じた発振周波数を持つ信号Ｓ３５を生成し、これを信号変換回路３６，３７に出力する。すなわち、数値制御発振回路３５は、アナログ回路における電圧制御発振回路（ＶＣＯ）と同じ動作をデジタルで行う。
図４は、数値制御発振回路３５の構成図である。
図４に示すように、数値制御発振回路３５は、加算回路７０、ラッチ回路７１および増幅回路７２を有する。
数値制御発振回路３５では、加算回路７０において、図１に示すループフィルタ回路３４から入力した８ビットの信号Ｓ３４と、ラッチ回路７１から出力される１６ビットの信号Ｓ７１とが加算されて１６ビットの信号Ｓ７０が生成される。信号Ｓ７０は、ラッチ回路７１に出力される。
ラッチ回路７１では、信号Ｓ７０が１システムクロックサイクルだけ遅延され、信号Ｓ７１として加算回路７０および増幅回路７２に出力される。
増幅回路７２では、１６ビットの信号Ｓ７１が、２^-8倍に増幅されて、８ビットの信号Ｓ３５が生成される。
信号Ｓ３５は、信号変換回路４３および４４に出力される。
【００５２】
図５は、数値制御発振回路３５の動作を説明するための図であり、ラッチ回路７１から出力される信号Ｓ７１の値の変化を示している。
図５に示すように、ラッチ回路７１では、信号Ｓ７０がオーバーフローすると、信号Ｓ７１の値を０にする。また、信号Ｓ７０の値に応じて、すなわち信号Ｓ４１の値に応じて、信号Ｓ７１の傾きが大きくなり、周期が変化する。具体的には、信号Ｓ４１の値が大きい程、信号Ｓ７１の周期は短く、すなわち周波数が高くなる。数値制御発振回路３５によれば、システムクロック信号の周波数の１／２までの周波数の信号Ｓ３５を生成できる。数値制御発振回路３５の周波数の分解能は、（システムクロック信号の周波数）×２^-16 になる。
【００５３】
信号変換回路３６は、図４に示すようにＳＩＮ特性を持つ８ビットの分解能の信号を格納したＲＯＭを有し、数値制御発振回路３５からの信号Ｓ３５に応じてＲＯＭから読み出したＳＩＮ特性の信号Ｓ３６を複素乗算回路３０に出力する。
信号変換回路３７は、図４に示すようにＣＯＳ特性を持つ８ビットの分解能の信号を格納したＲＯＭを有し、数値制御発振回路３５からの信号Ｓ３５に応じてＲＯＭから読み出したＣＯＳ特性の信号Ｓ３７を複素乗算回路３０に出力する。
【００５４】
ここで、複素乗算回路３０、ロールオフフィルタ回路３１，３２、位相検出回路３３、ループフィルタ回路３４、数値制御発振回路３５および信号変換回路３６，３７によってコスタスループ(Costas Loop) 回路５５が構成される。
【００５５】
軟判定回路４５は、ロールオフフィルタ回路３１からのＩ信号Ｓ３１と、ロールオフフィルタ回路３２からのＱ信号Ｓ３２とを軟判定し、その結果を後段の誤り訂正回路に出力する。そして、誤り訂正後に、Ｉ信号およびＱ信号を用いて再生信号が生成される。
【００５６】
シンボルタイミング再生回路４６は、ロールオフフィルタ回路３１，３２からのＩ信号Ｓ３１およびＱ信号Ｓ３２のシンボルタイミングを検出し、その結果に応じたシンボルタイミング信号Ｓ４６を補間回路２８，２９に出力する。
【００５７】
ＡＧＣ回路４７は、Ａ／Ｄ変換回路２０，２１の後段の回路において安定した適切な振幅を用いて処理が行えるように、Ｉ信号Ｓ３１およびＱ信号Ｓ３２の振幅値を用いて、アナログ増幅回路１５，１６の増幅率を制御するためのデジタルの増幅率制御信号Ｓ４７を例えば８ビットの分解能で生成し、これをＰＷＭ信号生成回路４８に出力する。
ＡＧＣ回路４７は、例えば、前述した従来の受信装置１００で説明した図１３に示す構成と同じ構成を有している。
【００５８】
ＰＷＭ信号生成回路４８は、デジタルの増幅率制御信号Ｓ４７を、アナログ信号を得るためのＰＷＭ信号である増幅率制御信号Ｓ４８に変換し、これをローパスフィルタ４９に出力する。
ローパスフィルタ４９は、増幅率制御信号Ｓ４８の高域成分を除去して、アナログの増幅率制御信号Ｓ４９を生成し、これをアナログ増幅回路１５および１６に出力する。
【００５９】
ＡＧＣ回路５０は、図１に示すＡＧＣ回路４７からの増幅率制御信号Ｓ４７の時間的な変化分を積分して増幅率αを示す増幅率制御信号Ｓ５０を生成し、これをデジタル増幅回路２３および２４に出力する。
図６は、ＡＧＣ回路５０の構成図である。
図６に示すように、遅延回路９０、加算回路９１，９２、遅延回路９３および増幅回路９４を有する。
ＡＧＣ回路５０では、図１に示すＡＧＣ回路４７からの増幅率制御信号Ｓ４７が遅延回路９０および加算回路９１に出力される。
次に、遅延回路９０および加算回路９１によって、増幅率制御信号Ｓ４７の時間変化分が検出され、当該検出された時間変化分を示す信号Ｓ９１が加算回路９２に出力される。
次に、加算回路９２および遅延回路９３によって、信号Ｓ９１が積分され、その結果である信号Ｓ９３が増幅回路９４に出力される。
次に、信号Ｓ９３が、増幅回路９４によって増幅されて増幅率制御信号Ｓ５０が生成される。
【００６０】
以下、受信装置１の動作を説明する。
衛星中継器を介して受信した受信信号Ｓ１０の同相成分が、同相検波回路１２において、局部発振信号Ｓ１１を用いて検波され、ベースバンドのＩ信号Ｓ１２が生成される。
また、それと並行して、受信信号Ｓ１０の直交成分が、直交検波回路１４において、局部発振信号Ｓ１１と９０度位相差を持つ局部発生信号Ｓ１３を用いて検波され、ベースバンドのＱ信号Ｓ１４が生成される。
【００６１】
アナログ増幅回路１５における増幅率制御信号Ｓ４９に基づいた増幅処理によって、Ｉ信号Ｓ１２からＩ信号Ｓ１５が生成される。
ＬＰＦ回路１８におけるＬＰＦ処理およびＡ／Ｄ変換回路２０におけるＡ／Ｄ変換処理を経て、Ｉ信号Ｓ１５からＩ信号Ｓ２０が生成される。
次に、図２（Ａ）に示すデジタル増幅回路２３において、ＡＧＣ回路５０からの増幅率制御信号Ｓ５０に基づいて、Ｉ信号Ｓ２０からＩ信号Ｓ２３が生成される。
次に、補間回路２８において、軟判定回路４５が適切なタイミングでシンボルの判定を行えるように、シンボルタイミング再生回路４６からのシンボルタイミング信号Ｓ４６に基づいてＩ信号Ｓ２３の補間処理が行われてＩ信号Ｓ２８が生成される。
【００６２】
また、上述したＩ信号の処理と並行して以下に示すＱ信号の処理が行われる。
すなわち、アナログ増幅回路１６における増幅率制御信号Ｓ４９に基づいた増幅処理によって、Ｑ信号Ｓ１４からＱ信号Ｓ１６が生成される。
ＬＰＦ回路１９におけるＬＰＦ処理およびＡ／Ｄ変換回路２１におけるＡ／Ｄ変換処理を経て、Ｑ信号Ｓ１６からＱ信号Ｓ２１が生成される。
次に、図２（Ｂ）に示すデジタル増幅回路２４において、ＡＧＣ回路５０からの増幅率制御信号Ｓ５０に基づいて、Ｑ信号Ｓ２１からＱ信号Ｓ２４が生成される。
次に、補間回路２９において、軟判定回路４５が適切なタイミングでシンボルの判定を行えるように、シンボルタイミング再生回路４６からのシンボルタイミング信号Ｓ４６に基づいてＱ信号Ｓ２４の補間処理が行われてＱ信号Ｓ２９が生成される。
【００６３】
そして、コスタスループ回路５５において、Ｉ信号Ｓ２８およひＱ信号Ｓ２９の周波数引き込み処理および位相同期処理が行われる。
その過程で、ロールオフフィルタ回路３１，３２からのＩ信号Ｓ３１およびＱ信号Ｓ３２がＡＧＣ回路４７に出力される。
ＡＧＣ回路４７では、図１３に示す構成によって、Ａ／Ｄ変換回路２０，２１の後段の回路において安定した適切な振幅を用いた処理を行えるように、Ｉ信号Ｓ３１およびＱ信号Ｓ３２の振幅値を用いて、増幅回路１５，１６の増幅率を制御するためのデジタルの増幅率制御信号Ｓ４７が例えば８ビットの分解能で生成される。
デジタルの増幅率制御信号Ｓ４７は、ＰＷＭ信号生成回路４８において、アナログ信号を得るためのＰＷＭ信号である増幅率制御信号Ｓ４８に変換され、ローパスフィルタ４９に出力される。
増幅率制御信号Ｓ４８は、ローパスフィルタ４９において高域成分が除去されると、アナログの増幅率制御信号Ｓ４９となり、増幅回路１５および１６に出力される。
【００６４】
また、図６に示すＡＧＣ回路５０において、増幅率制御信号Ｓ４７の時間変化分が積分されて、増幅率αを示す増幅率制御信号Ｓ５０が生成され、増幅率制御信号Ｓ５０がデジタル増幅回路２３，２４に出力される。
【００６５】
以上説明したように、受信装置１によれば、従来から行われているＡＧＣ回路４７によるアナログ増幅回路１５，１６の増幅率の制御に加えて、ＡＧＣ回路４７が生成した増幅率制御信号Ｓ４７を用いたＡＧＣ回路５０によるデジタル増幅回路２３，２４の増幅率制御を行う。
ここで、ＡＧＣ回路５０において、増幅率制御信号Ｓ４７の時間変化を積分することでＡＧＣ回路４７の分解能以下の変化量を持つ増幅率制御信号Ｓ５０を得て、増幅率制御信号Ｓ５０を用いてデジタル増幅回路２３，２４の増幅率を制御する。これによって、図１３に示すＡＧＣ回路４７において信号Ｓ１５２と参照用振幅信号Ｓ１６０とが実際に完全に一致しないことによる増幅率制御信号Ｓ４７に継続して生じる微小な振幅の振動を抑制することができる。その結果、受信装置１２１によれば、復調時の受信信号のシンボルデータの振幅を最適化でき、受信装置１の特性を前述した従来の受信装置１００に比べて改善できる。
【００６６】
すなわち、受信装置１では、ＡＧＣ回路５０およびデジタル増幅回路２３，２４は、ＡＧＣ回路４７およびアナログ増幅回路１５，１６によって補正しきれない部分を補助的に補正する役割を果たす。
【００６７】
第２実施形態
図７は、本実施形態の受信装置１２１の構成図である。
図７に示すように、受信装置１２１は、例えば、入力端子１０、局部発振回路１１、同相検波回路１２、移相回路１３、直交検波回路１４、アナログ増幅回路１５，１６、ＬＰＦ回路１８，１９、Ａ／Ｄ変換回路２０，２１、発振回路２２、デジタル増幅回路２３，２４、補正回路２８，２９、複素乗算回路３０、ロールオフフィルタ回路３１，３２、位相検出回路３３、ループフィルタ回路３４、数値制御発振回路３５、信号変換回路３６，３７、軟判定回路４５、シンボルタイミング再生回路４６およびＡＧＣ(Auto Gain Control) 回路４７、ＰＷＭ信号生成回路４８、ローパスフィルタ４９およびＩＱ振幅誤差補正回路５１を有する。
【００６８】
図７に示す受信装置１２１は、請求項８に記載の受信装置に対応している。
また、図７に示す構成要素と請求項８の構成要素との対応は以下に示すようになる。同相検波回路１２および１４が本発明の分離回路に対応し、アナログ増幅回路１５が本発明のアナログ増幅回路に対応し、Ａ／Ｄ変換回路２０，２１が本発明のＡ／Ｄ変換回路に対応し、デジタル増幅回路２４が本発明の第１のデジタル増幅回路に対応し、デジタル増幅回路２３が本発明の第２のデジタル増幅回路に対応し、ＡＧＣ回路４７が本発明の第１の増幅制御回路に対応し、ＩＱ振幅誤差補正回路５１が本発明の第２の増幅制御回路に対応している。
【００６９】
図７において、図１と同じ符号を付した構成要素は、前述した第１実施形態で説明した同じ符号の構成要素と同じである。
すなわち、受信装置１２１は、図１に示す受信装置１からＡＧＣ回路５０を除いて、代わりにＩＱ振幅誤差補正回路５１および符号判定回路１２０を加えた構成をしている。
【００７０】
以下、ＩＱ振幅誤差補正回路５１について説明する。
図８は、図７に示すＩＱ振幅誤差補正回路５１の構成図である。
図８に示すように、ＩＱ振幅誤差補正回路５１は、絶対値生成回路１１０，１１１、減算回路１１２、加算回路１１３、遅延回路１１４および増幅回路１１５を有する。
ＩＱ振幅誤差補正回路５１では、図７に示すロールオフフィルタ回路３１からのＩ信号Ｓ３１が絶対値生成回路１１０に入力される。
絶対値生成回路１１０において、Ｉ信号Ｓ３１の絶対値を示す信号Ｓ１１０が生成され、これが減算回路１１２に出力される。
また、図８に示すロールオフフィルタ回路３２からのＱ信号Ｓ３２が絶対値生成回路１１１に入力される。
絶対値生成回路１１１において、Ｑ信号Ｓ３２の絶対値を示す信号Ｓ１１１が生成され、これが減算回路１１２に出力される。
【００７１】
次に、減算回路１１２において、信号Ｓ１１０から信号Ｓ１１１が減算され、その減算結果である信号Ｓ１１２が加算回路１１３に出力される。
次に、加算回路１１３および遅延回路１１４によって、信号Ｓ１１２が積分され、その積分結果である信号Ｓ１１４が増幅回路１１５に出力される。
次に、増幅回路１１５において、信号Ｓ１１４が増幅されて増幅率βを示す増幅率制御信号Ｓ５１が生成される。
ここで、増幅率αは、例えば、「０≦α≦１」を満たしている。
増幅率制御信号Ｓ５１は、ＩＱ振幅誤差補正回路５１から図７に示すデジタル増幅回路２３および符号判定回路１２０に出力される。
符号判定回路１２０では、増幅率制御信号Ｓ５１の符号が反転され、例えば、増幅率−βを示す増幅率制御信号Ｓ１２０がデジタル増幅回路２３に出力される。
【００７２】
デジタル増幅回路２３，２４は、前述した第１実施形態の場合と同じ構成を有しているが、増幅率制御信号Ｓ５０ではなく、それぞれ増幅率−βを示す増幅率制御信号Ｓ１２０および増幅率βを示す増幅率制御信号Ｓ５１に基づいて、Ａ／Ｄ変換回路２０および２１からのＩ信号Ｓ２０およびＱ信号Ｓ２１を（１−β）倍および（１＋β）倍に増幅してＩ信号Ｓ２３およびＱ信号Ｓ２４を生成する。
【００７３】
図９（Ａ）は、本実施形態のデジタル増幅回路２３の作用を説明するための図である。
本実施形態のデジタル増幅回路２３では、図７に示すＡ／Ｄ変換回路２０からのＩ信号Ｓ２０が、乗算回路８０および加算回路８１に出力される。
乗算回路８０において、Ｉ信号Ｓ２０と、増幅率−βを示す増幅率制御信号Ｓ１２０とが乗算され、その乗算結果である信号Ｓ８０が加算回路８１に出力される。
加算回路８１では、Ｉ信号Ｓ２０と信号Ｓ８０とが加算され、その加算結果であるＩ信号Ｓ２３が図７に示す補間回路２８に出力される。
本実施形態のデジタル増幅回路２３は、Ｉ信号Ｓ２０を（１−β）倍に増幅してＩ信号Ｓ２３を生成する。
【００７４】
図９（Ｂ）は、本実施形態のデジタル増幅回路２４の作用を説明するための図である。
本実施形態のデジタル増幅回路２４では、図７に示すＡ／Ｄ変換回路２１からのＱ信号Ｓ２１が、乗算回路８２および加算回路８３に出力される。
乗算回路８２において、Ｑ信号Ｓ２１と、増幅率βを示す増幅率制御信号Ｓ５１とが乗算され、その乗算結果である信号Ｓ８２が加算回路８３に出力される。加算回路８３では、Ｑ信号Ｓ２１と信号Ｓ８２とが加算され、その加算結果であるＱ信号Ｓ２４が図７に示す補間回路２９に出力される。
本実施形態のデジタル増幅回路２４は、Ｑ信号Ｓ２１を（１＋β）倍に増幅してＱ信号Ｓ２４を生成する。
【００７５】
受信装置１２１の作用を説明する。
受信装置１２１では、衛星中継器を介して受信した受信信号Ｓ１０が上述した第１実施形態の受信装置１と同様の処理を経て、Ａ／Ｄ変換回路２０および２１からデジタル増幅回路２３および２４に、Ｉ信号Ｓ２０およびＱ信号Ｓ２１が出力される。
また、後段のロールオフフィルタ回路３１および３２からのＩ信号Ｓ３１およびＱ信号Ｓ３２がＩＱ振幅誤差補正回路５１に入力され、図８に示すＩＱ振幅誤差補正回路５１において、Ｉ信号Ｓ３１の振幅とＱ信号Ｓ３２の振幅との差分を積分した値に応じた増幅率制御信号Ｓ５１が生成される。
増幅率制御信号Ｓ５１は、デジタル増幅回路２４および符号判定回路１２０に出力される。
そして、符号判定回路１２０からデジタル増幅回路２３に、増幅率βを示す増幅率制御信号Ｓ５１の符号が反転され、増幅率−βを示す増幅率制御信号Ｓ１２０が生成され、増幅率制御信号Ｓ１２０がデジタル増幅回路２３に出力される。
【００７６】
そして、デジタル増幅回路２３および２４において、Ｉ信号Ｓ２０の振幅と、Ｑ信号Ｓ２１の振幅との誤差を抑制するように増幅処理が行われてＩ信号Ｓ２３およびＱ信号Ｓ２４が生成される。
そして、Ｉ信号Ｓ２３およびＱ信号Ｓ２４に対して、前述した第１実施形態の場合と同様に、補間回路２８，２９およびコスタスループ回路５５の処理が行われる。
【００７７】
上述したように、受信装置１２１では、ＩＱ振幅誤差補正回路５１において、Ｉ信号Ｓ３１とＱ信号Ｓ３２との振幅の絶対値の誤差を積分することで、Ｉ信号の振幅とＱ信号の振幅との間の定常的な誤差を抑制するように、デジタル増幅回路２３，２４の増幅率を制御できる。
その結果、同相検波回路１２および直交検波回路１４などのアナログ回路の特性のバラツキによって生じるＩＱ振幅誤差を適切に抑制でき、従来に比べて、復調時におけるビットエラーレートを改善できる。
また、受信装置１２１では、同相検波回路１２および直交検波回路１４などのアナログ回路の性能に対しての要求を緩和でき、構成の簡単化および低価格化が図れる。
【００７８】
第３実施形態
図１０は、本実施形態の受信装置１３１の構成図である。
図１に示すように、受信装置１は、例えば、入力端子１０、局部発振回路１１、同相検波回路１２、移相回路１３、直交検波回路１４、アナログ増幅回路１５，１６、ＬＰＦ回路１８，１９、Ａ／Ｄ変換回路２０，２１、発振回路２２、デジタル増幅回路２３，２４、補正回路２８，２９、複素乗算回路３０、ロールオフフィルタ回路３１，３２、位相検出回路３３、ループフィルタ回路３４、数値制御発振回路３５、信号変換回路３６，３７、軟判定回路４５、シンボルタイミング再生回路４６およびＡＧＣ(Auto Gain Control) 回路４７、ＰＷＭ信号生成回路４８、ローパスフィルタ４９、ＡＧＣ回路５０、ＩＱ振幅誤差補正回路５１および加算回路５２，５３を有する。
図１０において、図１と同じ符号を付した構成要素は、前述した第１実施形態で説明した同じ符号の構成要素と同じである。
すなわち、受信装置１２１は、図１に示す受信装置１からＡＧＣ回路５０に、ＩＱ振幅誤差補正回路５１、減算回路５２および加算回路５３を加えた構成をしている。
また、ＩＱ振幅誤差補正回路５１は、第２実施形態で説明した図８に示すものと同じである。
【００７９】
図１０に示す受信装置１３１は、請求項１１に記載の受信装置に対応している。
また、図１０に示す構成要素と請求項１１の構成要素との対応は以下に示すようになる。同相検波回路１２および１４が本発明の分離回路に対応し、アナログ増幅回路１５が本発明のアナログ増幅回路に対応し、Ａ／Ｄ変換回路２０，２１が本発明のＡ／Ｄ変換回路に対応し、デジタル増幅回路２４が本発明の第１のデジタル増幅回路に対応し、デジタル増幅回路２３が本発明の第２のデジタル増幅回路に対応し、ＡＧＣ回路４７が本発明の第１の増幅制御回路に対応し、ＡＧＣ回路５０、ＩＱ振幅誤差補正回路５１、減算回路５２および加算回路５３が本発明の第２の増幅制御回路に対応している。
【００８０】
受信装置１３１では、第１実施形態で説明した図６に示すＡＧＣ回路５０から加算回路５２および５３に、増幅率αを示す増幅率制御信号Ｓ５０が入力される。
ここで、増幅率αは、例えば、「０≦α≦１」を満たしている。
また、第２実施形態で説明した図８に示すＩＱ振幅誤差補正回路５１から加算回路５２および５３に、増幅率βを示す増幅率制御信号Ｓ５１が入力される。
ここで、増幅率βは、例えば、「０≦β≦１」を満たしている。
【００８１】
そして、減算回路５２において、増幅率制御信号Ｓ５０から増幅率制御信号Ｓ５１が減算され、その減算結果である「α−β」を示す増幅率制御信号Ｓ５２がデジタル増幅回路２３に出力される。
また、加算回路５３において、増幅率制御信号Ｓ５０と増幅率制御信号Ｓ５１とが加算され、その加算結果である「α＋β」を示す増幅率制御信号Ｓ５３がデジタル増幅回路２４に出力される。
【００８２】
デジタル増幅回路２３，２４は、前述した第１実施形態の場合と同じ構成を有しているが、増幅率制御信号Ｓ５０ではなく、それぞれ増幅率−βを示す増幅率制御信号Ｓ１２０および増幅率βを示す増幅率制御信号Ｓ５１に基づいて、Ａ／Ｄ変換回路２０および２１からのＩ信号Ｓ２０およびＱ信号Ｓ２１を（１−β）倍および（１＋β）倍に増幅してＩ信号Ｓ２３およびＱ信号Ｓ２４を生成する。
【００８３】
図１１（Ａ）は、本実施形態のデジタル増幅回路２３の構成図である。
本実施形態のデジタル増幅回路２３では、図１０に示すＡ／Ｄ変換回路２０からのＩ信号Ｓ２０が、乗算回路８０および加算回路８１に出力される。
乗算回路８０において、Ｉ信号Ｓ２０と、増幅率「α−β」を示す増幅率制御信号Ｓ５２とが乗算され、その乗算結果である信号Ｓ８０が加算回路８１に出力される。
加算回路８１では、Ｉ信号Ｓ２０と信号Ｓ８０とが加算され、その加算結果であるＩ信号Ｓ２３が図１０に示す補間回路２８に出力される。
本実施形態のデジタル増幅回路２３は、Ｉ信号Ｓ２０を（１＋α−β）倍に増幅してＩ信号Ｓ２３を生成する。
【００８４】
図１１（Ｂ）は、本実施形態のデジタル増幅回路２４の作用を説明するための図である。
本実施形態のデジタル増幅回路２４では、図１０に示すＡ／Ｄ変換回路２１からのＱ信号Ｓ２１が、乗算回路８２および加算回路８３に出力される。
乗算回路８２において、Ｑ信号Ｓ２１と、増幅率「α＋β」を示す増幅率制御信号Ｓ５３とが乗算され、その乗算結果である信号Ｓ８２が加算回路８３に出力される。
加算回路８３では、Ｑ信号Ｓ２１と信号Ｓ８２とが加算され、その加算結果であるＱ信号Ｓ２４が図１に示す補間回路２９に出力される。
本実施形態のデジタル増幅回路２４は、Ｑ信号Ｓ２１を（１＋α＋β）倍に増幅してＱ信号Ｓ２４を生成する。
【００８５】
受信装置１３１は、上述した第１実施形態の受信装置１の効果と、第２実施形態の受信装置１２１の効果との双方を発揮できる。
すなわち、受信装置１３１によれば、図１３に示すＡＧＣ回路４７において信号Ｓ１５２と参照用振幅信号Ｓ１６０とが実際に完全に一致しないことによる増幅率制御信号Ｓ４７に継続して生じる微小な振幅の振動を抑制できると共に、Ｉ信号の振幅とＱ信号の振幅との間の定常的な誤差を抑制できる。
【００８６】
【発明の効果】
以上説明したように、本発明の受信装置およびその方法によれば、受信信号を安定して状態で処理できるため、例えば復調処理の特性を高めることができる。
【図面の簡単な説明】
【図１】図１は、本発明の第１実施形態の受信装置の構成図である。
【図２】図２は、図１に示すデジタル増幅回路の構成図である。
【図３】図３は、図１に示す複素乗算回路の構成図である。
【図４】図４は、図１に示す数値制御発振回路の構成図である
【図５】図５は、図４に示す数値制御発振回路の動作を説明するための図であり、ラッチ回路から出力される信号の値の変化を示す図である。
【図６】図６は、図１に示すＡＧＣ回路の構成図である。
【図７】図７は、本発明の第２実施形態の受信装置の構成図である。
【図８】図８は、図７に示すＩＱ振幅誤差補正回路の構成図である。
【図９】図９は、図７に示すデジタル増幅回路の作用を説明するための図である。
【図１０】図１０は、本発明の第３実施形態の受信装置の構成図である。
【図１１】図１１は、図１０に示すデジタル増幅回路の構成図である。
【図１２】図１２は、従来の受信装置の構成図である。
【図１３】図１３は、図１２に示すＡＧＣ回路の構成図である。
【符号の説明】
１０…入力端子、１１…局部発振回路、１２…同相検波回路、１３…移相回路、１４…直交検波回路、１５，１６…増幅回路、１７，１８，１９…ＬＰＦ回路、２０，２１…Ａ／Ｄ変換回路、２３，２４…デジタル増幅回路、２８，２９…補間回路、３０…複素乗算回路、３１，３２…ロールオフフィルタ回路、３３…位相検出回路、３４…ループフィルタ回路、３５…数値制御発振回路、３６，３７…信号変換回路、４５…軟判定回路、４６…シンボル再生回路、４７…ＡＧＣ回路、４８…ＰＷＭ信号生成回路、４９…ローパスフィルタ、５０…ＡＧＣ回路、５１…ＩＱ振幅誤差補正回路、１２０…符号反転回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiving apparatus and method used in satellite communication and satellite broadcasting.
[0002]
[Prior art]
FIG. 12 is a configuration diagram of a receiving apparatus 100 that receives a modulation signal used in a conventional satellite communication network or the like.
In the receiving apparatus 100, processing is performed as follows.
The in-phase component of the received signal (intermediate frequency signal) S10 received via the satellite repeater is detected by the in-phase detection circuit 12 using the local oscillation signal S11, and a baseband I signal S12 is generated.
An I signal S20 is generated from the I signal S12 through an amplification process in the amplification circuit 15, an LPF process in the LPF circuit 18, and an A / D conversion process in the A / D conversion circuit 20.
At this time, in the amplifier circuit 15, the I signal S12 is amplified at an amplification factor according to the amplification factor control signal S49 from the low-pass filter 49, and the I signal S15 is generated.
[0003]
In parallel with this, the quadrature component of the received signal S10 is detected by the quadrature detection circuit 14 using the local generation signal S13 having a 90-degree phase difference with the local oscillation signal S11, and a baseband Q signal S14 is generated. Is done.
Then, the Q signal S21 is generated from the Q signal S14 through the amplification process in the amplifier circuit 16, the LPF process in the LPF circuit 19, and the A / D conversion process in the A / D conversion circuit 21.
At this time, in the amplifier circuit 16, the Q signal S14 is amplified at an amplification factor corresponding to the amplification factor control signal S49 from the low-pass filter 49, and the Q signal S16 is generated.
[0004]
Next, in the interpolation circuits 28 and 29, the I signal S20 and the Q signal S21 are interpolated based on the symbol timing S46 from the symbol timing reproduction circuit 46 so that the soft decision circuit 45 can determine the symbol at an appropriate timing. Processing is performed to generate an I signal S28 and a Q signal S29, respectively.
[0005]
Next, the complex multiplication circuit 30 uses the carrier recovery (frequency acquisition and phase synchronization) signals S36 and S37 from the signal conversion circuits 36 and 37 to perform frequency acquisition processing on the I signal S28 and the Q signal S29. And the phase synchronization process is performed, and the I signal S30a and the Q signal S30b are generated.
[0006]
Next, in the roll-off filter circuit 31, the I signal S30a is subjected to filter processing for reducing intersymbol interference to generate an I signal S31.
In the roll-off filter circuit 32, the Q signal S30b is subjected to filter processing for reducing intersymbol interference to generate the Q signal S32.
[0007]
Next, the phase detection circuit 33 detects a phase determined by the I signal S31 and the Q signal S32, and generates a phase signal S33 indicating the phase.
The phase signal S33 is output to the loop filter circuit 34 and smoothed to generate the phase signal S34.
Next, in the numerically controlled oscillation circuit 35, a signal S35 having an oscillation frequency corresponding to the value of the phase signal S34 is generated and output to the signal conversion circuits 36 and 37. Next, a signal S36 having a SIN characteristic corresponding to the signal S35 and a signal S37 having a COS characteristic corresponding to the signal S35 are output from the signal conversion circuits 36 and 37 to the complex multiplication circuit 30.
[0008]
Here, the Costas loop 25 is configured by the complex multiplication circuit 30, the roll-off filter circuits 31, 32, the phase detection circuit 33, the loop filter circuit 34, the numerically controlled oscillation circuit 35, and the signal conversion circuits 36, 37.
The Costas loop 25 acts to pull in the frequency detuning component generated in the I signal S28 and the Q signal S29 by feeding back the phase signal S33 from the phase detection circuit 33.
[0009]
In receiving apparatus 100, I signal S 31 and Q signal S 32 generated by roll-off filter circuits 31 and 32 are output to AGC (Auto Gain Control) circuit 47.
The AGC circuit 47 uses the amplitude values of the I signal S31 and the Q signal S32 so as to perform processing using stable and appropriate amplitudes in the subsequent circuits of the A / D conversion circuits 20 and 21. A digital amplification factor control signal S47 for controlling the amplification factor of 16 is generated, for example, with a resolution of 8 bits.
The digital amplification factor control signal S47 is converted into an amplification factor control signal S48, which is a PWM signal for obtaining an analog signal, in a PWM (Pulse Width Modulation) signal generation circuit 48 and output to the low-pass filter 49.
When the high frequency component is removed by the low-pass filter 49, the gain control signal S48 becomes an analog gain control signal S49 and is output to the amplifier circuits 15 and 16.
[0010]
The configuration of the conventional AGC circuit 47 shown in FIG. 12 will be described below.
FIG. 13 is a configuration diagram of the AGC circuit 47 shown in FIG.
In the AGC circuit 47 shown in FIG. 13, the multiplication of the I signal S31 and the Q signal S32 shown in FIG. 12 is performed by the multiplication circuits 150 and 151, and the signals S150 and S151 that are the multiplication results are output to the addition circuit 152. The
Next, the addition circuit 152 performs addition of the signals S150 and S151, and a signal S152 as a result of the addition is output to the addition circuit 153.
Next, in the addition circuit 153, the reference signal S160 having the optimum amplitude is subtracted from the signal S152 to generate the signal S153, and the signal S153 is output to the addition circuit 154.
[0011]
Next, in the addition circuit 154 and the delay circuit 155, the signal S153 is averaged by integration, and the resultant signal S155 is output to the amplification circuit 156.
Next, in the amplifier circuit 156, the signal S155 is amplified to generate an amplification factor control signal S47.
[0012]
[Problems to be solved by the invention]
In the receiving apparatus 100 shown in FIG. 12 described above, the amplification factors of the amplification circuits 15 and 16 are determined based on the analog amplification factor control signal S47, whereas the AGC processing in the AGC circuit 47 is performed digitally. Is called.
For this reason, in the AGC circuit 47 shown in FIG. 13, the signal S52 and the reference amplitude signal S160 do not actually completely coincide with each other, and the amplification factor control signal S49 continuously vibrates with a minute amplitude. There is a problem of adversely affecting 100 characteristics.
[0013]
In order to solve such a problem, for example, Japanese Patent Application Laid-Open No. 7-336174 discloses a digital AGC apparatus that performs all AGC processing digitally.
In this digital AGC apparatus, since the AGC process is all performed digitally, it is possible to finely optimize the AGC process. Therefore, there is a problem that the resolution of the portion to be performed needs to be 100 times or more the normal, which is not realistic from the viewpoint of the device scale and the price.
[0014]
In addition, in a device that performs processing by separating the in-phase component and the quadrature component in the tuner unit, such as the receiving device 100 shown in FIG. 12, the characteristics of analog elements such as the in-phase detection circuit 12 and the quadrature detection circuit 14 vary. Therefore, for example, even when the I signal and the Q signal originally have the same amplitude, a slight error occurs due to variations in these analog elements.
Such an error is called IQ amplitude error (IQ Amplitude Imbalance), and becomes a factor that degrades the bit error rate during demodulation.
[0015]
The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a receiving apparatus and method capable of obtaining high characteristics with a small-scale and low-cost configuration.
[0016]
[Means for Solving the Problems]
In order to solve the above-described problems of the prior art and achieve the above-described object, a receiving apparatus according to a first aspect of the present invention amplifies an analog received signal based on a first gain control signal. An analog amplification circuit, an A / D conversion circuit for A / D converting the amplified reception signal, and a digital reception signal obtained by the A / D conversion based on a second amplification factor control signal And a first digital amplification circuit that detects a difference between the amplitude of the digital reception signal and a predetermined reference amplitude, and generates the first amplification factor control signal so as to reduce the detected difference. And a second amplification control circuit that integrates the time variation of the amplitude of the first amplification factor control signal to generate the second amplification factor control signal.
[0017]
In the receiving apparatus of the first aspect, the analog reception signal is amplified based on the first amplification factor control signal in the analog amplifier circuit.
Next, in the A / D conversion circuit, the amplified received signal is A / D converted.
Next, in the digital amplifier circuit, the digital reception signal obtained by the A / D conversion is amplified based on the second amplification factor control signal.
In the course of these processes, the first amplification control circuit detects the difference between the amplitude of the digital received signal and a predetermined reference amplitude, and reduces the detected difference. An amplification factor control signal is generated.
Further, in the second amplification control circuit, the time change of the amplitude of the first amplification factor control signal is integrated to generate the second amplification factor control signal.
[0018]
In the receiving apparatus according to the first aspect of the present invention, preferably, when the second amplification factor control signal indicates a coefficient α, the digital amplifier circuit is configured to receive the digital signal obtained by the A / D conversion. The received signal is amplified by (1 + α) times.
[0019]
The receiving apparatus according to the first aspect of the present invention is preferably a multiplication circuit that multiplies a digital reception signal amplified by the digital amplification circuit and a feedback signal, and a signal output from the multiplication circuit. A phase detection circuit that generates a phase signal by detecting a phase of the signal, and a numerical control circuit that generates the feedback signal having an oscillation frequency corresponding to the phase signal, wherein the first amplification control circuit includes the multiplication A difference between the amplitude of the signal output from the circuit and a predetermined reference amplitude is detected, and the first amplification factor control signal is generated so as to reduce the detected difference.
[0020]
The receiving apparatus according to the second aspect of the present invention includes a separation circuit that separates a phase-modulated analog reception signal into an in-phase component signal and a quadrature component signal, and a first amplification factor control signal. An analog amplification circuit for amplifying the in-phase component signal and the quadrature component signal, an A / D conversion circuit for A / D converting the amplified in-phase component signal and the quadrature component signal, A digital amplification circuit that amplifies the in-phase component signal and the quadrature component signal obtained by the A / D conversion based on the second amplification factor control signal; and the in-phase component signal obtained from the digital amplification circuit; A Costas loop circuit that performs frequency pull-in processing and phase synchronization processing of a quadrature component signal, and an amplitude and location obtained from the in-phase component signal and the quadrature component signal from the Costas loop circuit. A first amplification control circuit that generates the first amplification factor control signal so as to detect a difference from the reference amplitude and reduce the detected difference, and the first amplification factor control signal A second amplification control circuit that integrates the time variation of the amplitude and generates the second amplification factor control signal so as to reduce the amplitude of the first amplification factor control signal using the integration result;
[0021]
In the receiving apparatus according to the second aspect of the present invention, the phase-modulated analog reception signal is separated into the in-phase component signal and the quadrature component signal of the carrier wave by the separation circuit. Next, the analog amplification circuit amplifies the in-phase component signal and the quadrature component signal based on the first amplification factor control signal.
Next, in the A / D conversion circuit, the amplified in-phase component signal and quadrature component signal are A / D converted.
Next, in the digital amplification circuit, the in-phase component signal and the quadrature component signal obtained by the A / D conversion are amplified based on the second amplification factor control signal.
Next, in the processing circuit, frequency pull-in processing and phase synchronization processing of the in-phase component signal and the quadrature component signal obtained from the digital amplifier circuit are performed.
In the course of these processes, in the first amplification control circuit, the difference between the amplitude obtained from the in-phase component signal and the quadrature component signal from the processing circuit and a predetermined reference amplitude is detected, and is detected. The first gain control signal is generated so as to reduce the difference.
Further, in the second amplification control circuit, the time variation of the amplitude of the first amplification factor control signal is integrated, and the integration result is used to reduce the amplitude of the first amplification factor control signal. A gain control signal of 2 is generated.
[0022]
In the receiving apparatus according to the second aspect of the present invention, preferably, the second amplification control circuit generates the digital second amplification factor control signal, and the receiving apparatus receives the digital second signal. And a conversion circuit for converting the gain control signal to analog and outputting the analog control signal to the first analog amplification circuit and the analog amplification circuit.
[0023]
The receiving apparatus according to the third aspect of the present invention includes a separation circuit that separates a phase-modulated analog reception signal into an in-phase component signal and a quadrature component signal of a carrier wave, and a first gain control signal. And an analog amplification circuit for amplifying the in-phase component signal and the quadrature component signal, and an A / D conversion circuit for A / D converting the amplified in-phase component signal and the quadrature component signal, respectively. , Based on a second amplification factor control signal, a first digital amplification circuit that amplifies the orthogonal component signal obtained by the A / D conversion, and on the basis of a third amplification factor control signal, the A / D A second digital amplification circuit that amplifies the in-phase component signal obtained by the D conversion, the amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the A / D conversion, and a predetermined reference amplitude Diff of A first amplification control circuit for generating the first amplification factor control signal so as to reduce the detected difference, and an in-phase component signal and a quadrature component signal obtained by the A / D conversion, A second amplification control circuit that generates the second amplification factor control signal and the third amplification factor control signal so as to integrate the difference of the amplitudes of the two and reduce the difference using the integration result; Have
[0024]
In the receiving apparatus according to the third aspect of the present invention, first, the phase-modulated analog received signal is separated into the in-phase component signal and the quadrature component signal of the carrier wave by the separation circuit.
Next, the analog amplification circuit amplifies the in-phase component signal and the quadrature component signal based on the first amplification factor control signal.
Next, in the A / D conversion circuit, the amplified in-phase component signal and quadrature component signal are A / D converted.
Next, in the first digital amplifier circuit, the orthogonal component signal obtained by the A / D conversion is amplified based on the second amplification factor control signal.
The second digital amplifier circuit amplifies the in-phase component signal obtained by the A / D conversion based on the third gain control signal.
In the course of these processes, the first amplification control circuit detects the difference between the amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the A / D conversion and a predetermined reference amplitude, The first gain control signal is generated so as to reduce the detected difference.
Further, in the second amplification control circuit, the difference in amplitude between the in-phase component signal and the quadrature component signal obtained by the A / D conversion is integrated, and the difference is reduced using the integration result. The second gain control signal and the third gain control signal are generated.
[0025]
In the receiving apparatus according to the third aspect of the present invention, preferably, the second amplification control circuit includes the second amplification factor control signal indicating a coefficient β and the third amplification indicating a coefficient “−β”. The first digital amplification circuit amplifies the orthogonal component signal obtained by the A / D conversion by (1 + β) times based on the second amplification factor control signal. The second digital amplifier circuit amplifies the in-phase component signal obtained by the A / D conversion by (1−β) times based on the third gain control signal.
[0026]
According to a fourth aspect of the present invention, there is provided a receiving device comprising: a separation circuit that separates a phase-modulated analog reception signal into a signal having an in-phase component and a signal having a quadrature component; and a first gain control signal. And an analog amplification circuit for amplifying the in-phase component signal and the quadrature component signal, and an A / D conversion circuit for A / D converting the amplified in-phase component signal and the quadrature component signal, respectively. , Based on a second amplification factor control signal, a first digital amplification circuit that amplifies the orthogonal component signal obtained by the A / D conversion, and on the basis of a third amplification factor control signal, the A / D A second digital amplification circuit that amplifies the in-phase component signal obtained by the D conversion, the amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the A / D conversion, and a predetermined reference amplitude Diff of In order to reduce the detected difference, a first amplification control circuit that generates the first amplification factor control signal and a time variation of the amplitude of the first amplification factor control signal are integrated to obtain a fourth And an amplitude difference between the in-phase component signal and the quadrature component signal obtained by the A / D conversion is integrated to generate a fifth amplification factor control signal. The amplitude difference between the in-phase component signal and the quadrature component signal obtained by the A / D conversion is reduced using the amplification factor control signal and the fifth amplification factor control signal, and the first A second amplification control circuit for generating the second amplification factor control signal and the third amplification factor control signal so as to reduce the amplitude of the amplification factor control signal;
[0027]
In the receiving apparatus according to the fourth aspect of the present invention, preferably, the second amplification control circuit includes the fourth amplification factor control signal indicating a coefficient α and the fifth amplification factor indicating a coefficient β. Based on the control signal, the second amplification factor control signal indicating the coefficient (1 + α + β) and the third amplification factor control signal indicating the coefficient (1 + α−β) are generated, and the first digital amplification is performed. The circuit amplifies the signal of the orthogonal component obtained by the A / D conversion by (1 + α + β) times based on the second amplification factor control signal, and the second digital amplification circuit Based on the amplification factor control signal, the signal of the in-phase component obtained by the A / D conversion is amplified by (1 + α−β) times.
[0028]
The reception method according to the first aspect of the present invention amplifies an analog reception signal based on the first amplification factor control signal, A / D-converts the amplified reception signal, and performs second amplification. Based on the rate control signal, the digital received signal obtained by the A / D conversion is amplified, the difference between the amplitude of the digital received signal and a predetermined reference amplitude is detected, and the detected difference is calculated. The first gain control signal is generated so as to be reduced, and the second gain control signal is generated by integrating the time variation of the amplitude of the first gain control signal.
[0029]
Further, the reception method of the second aspect of the present invention separates the phase-modulated analog reception signal into the in-phase component signal and the quadrature component signal of the carrier, and based on the first amplification factor control signal, Amplifying the in-phase component signal and the quadrature component signal, A / D converting the amplified in-phase component signal and quadrature component signal, and based on a second gain control signal, the A Amplifying the in-phase component signal and the quadrature component signal obtained by the / D conversion, performing frequency pull-in processing and phase synchronization processing on the amplified in-phase component signal and quadrature component signal, and obtained by the processing Detecting the difference between the amplitude obtained from the signal of the in-phase component and the signal of the quadrature component and a predetermined reference amplitude, and generating the first amplification factor control signal so as to reduce the detected difference, First The time variation of the amplitude amplification factor control signal by integrating the amplitude of said first gain control signal to generate the second gain control signal so as to decrease with the integration result.
[0030]
Further, the reception method of the third aspect of the present invention separates the phase-modulated analog reception signal into the in-phase component signal and the quadrature component signal of the carrier wave, and based on the first amplification factor control signal, Amplifying the in-phase component signal and the quadrature component signal, A / D converting the amplified in-phase component signal and the quadrature component signal, and based on a second gain control signal, The quadrature component signal obtained by the A / D conversion is amplified, and the in-phase component signal obtained by the A / D conversion is amplified based on the third gain control signal, and the A / D conversion is performed. A difference between the amplitude obtained from the obtained in-phase component signal and quadrature component signal and a predetermined reference amplitude is detected, and the first amplification factor control signal is generated so as to reduce the detected difference. Obtained by the A / D conversion The second amplification factor control signal and the third amplification factor control are integrated so that the difference in amplitude between the in-phase component signal and the quadrature component signal is integrated and the difference is reduced using the integration result. Generate a signal.
[0031]
Further, the reception method of the fourth aspect of the present invention separates the phase-modulated analog reception signal into the in-phase component signal and the quadrature component signal of the carrier, and based on the first amplification factor control signal, Amplifying the in-phase component signal and the quadrature component signal, A / D converting the amplified in-phase component signal and the quadrature component signal, and based on a second gain control signal, The quadrature component signal obtained by the A / D conversion is amplified, and the in-phase component signal obtained by the A / D conversion is amplified based on the third gain control signal, and the A / D conversion is performed. A difference between an amplitude obtained from the obtained in-phase component signal and quadrature component signal and a predetermined reference amplitude is detected, and the first amplification factor control signal is generated so as to reduce the detected difference. And the first gain control signal A fourth amplification factor control signal is generated by integrating the time variation of the width, and a fifth amplification is performed by integrating the difference in amplitude between the in-phase component signal and the quadrature component signal obtained by the A / D conversion. A rate control signal is generated, and the amplitudes of the in-phase component signal and the quadrature component signal obtained by the A / D conversion are calculated using the fourth gain control signal and the fifth gain control signal. The second gain control signal and the third gain control signal are generated so as to reduce the difference and reduce the amplitude of the first gain control signal.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
The receiving apparatus according to the embodiment of the present invention will be described below.
FIG. 1 is a configuration diagram of a receiving device 1 according to the present embodiment.
The receiving apparatus 1 uses, for example, frequency division multiple access (FDMA) such as SCPC (Single Channel Per Carrier) method, and phase such as BPSK (Binary Phase Shift Keying) and QPSK (Quadrature Phase Shift Keying). This is used in a receiving apparatus that receives a shift-modulated signal via a satellite repeater and demodulates the received signal.
[0033]
As shown in FIG. 1, the receiving device 1 includes, for example, an input terminal 10, a local oscillation circuit 11, an in-phase detection circuit 12, a phase shift circuit 13, a quadrature detection circuit 14, analog amplification circuits 15 and 16, and LPF circuits 18 and 19. A / D conversion circuits 20 and 21, oscillation circuit 22, digital amplification circuits 23 and 24, correction circuits 28 and 29, complex multiplication circuit 30, roll-off filter circuits 31 and 32, phase detection circuit 33, loop filter circuit 34, A numerical control oscillation circuit 35, signal conversion circuits 36 and 37, a soft decision circuit 45, a symbol timing reproduction circuit 46, an AGC (Auto Gain Control) circuit 47, a PWM signal generation circuit 48, a low-pass filter 49, and an AGC circuit 50 are provided.
[0034]
Here, the receiving device 1 corresponds to the receiving device of claims 1 and 5.
The correspondence between the components shown in FIG. 1 and the components of claim 1 is as follows. The analog amplifier circuit 15 corresponds to the analog amplifier circuit of the present invention, the A / D converter circuits 20 and 21 correspond to the A / D converter circuit of the present invention, and the digital amplifier circuits 23 and 24 correspond to the digital amplifier circuit of the present invention. Correspondingly, the AGC circuit 47 corresponds to the first amplification control circuit of the present invention, and the AGC circuit 50 corresponds to the second amplification control circuit of the present invention.
The correspondence between the components shown in FIG. 1 and the components of claim 5 is as follows.
The correspondence between the components shown in FIG. 1 and the components of claim 5 is as follows. The in-phase detection circuits 12 and 14 correspond to the separation circuit of the present invention, the analog amplification circuit 15 corresponds to the analog amplification circuit of the present invention, and the A / D conversion circuits 20 and 21 correspond to the A / D conversion circuit of the present invention. The digital amplifier circuits 23 and 24 correspond to the digital amplifier circuit of the present invention, the Costas loop circuit 55 corresponds to the processing circuit of the present invention, the AGC circuit 47 corresponds to the first amplification control circuit of the present invention, The AGC circuit 50 corresponds to the second amplification control circuit of the present invention.
[0035]
The local oscillation circuit 11 generates a local oscillation signal S11 having an intermediate frequency that is a carrier wave of the reception signal S10, and outputs this to the in-phase detection circuit 12 and the phase shift circuit 13.
The in-phase detection circuit 12 multiplies the local oscillation signal S11 by the QPSK-modulated intermediate frequency reception signal S10 input from the input terminal 10, thereby detecting the in-phase component of the carrier wave and generating the baseband I signal S12. This is generated and output to the analog amplifier circuit 15.
The phase shift circuit 13 generates a local oscillation signal S13 by shifting the phase of the local oscillation signal S11 from the local oscillation circuit 11 by 90 degrees, and outputs this to the quadrature detection circuit 14. The quadrature detection circuit 14 detects the quadrature component of the carrier wave by multiplying the local oscillation signal S13 and the QPSK-modulated reception signal S10 input from the input terminal 10, and generates a baseband Q signal S14. This is output to the analog amplifier circuit 16.
[0036]
Based on the amplification factor control signal S49 from the LPF circuit 49, the analog amplifier circuit 15 amplifies the I signal S12 to generate an I signal S15, and outputs this to the LPF circuit 18.
Based on the amplification factor control signal S49 from the LPF circuit 49, the analog amplifier circuit 16 amplifies the Q signal S14 to generate a Q signal S16, and outputs this to the LPF circuit 19.
[0037]
The LPF circuit 18 removes the high frequency component of the I signal S15 to generate the I signal S18, and outputs this to the A / D conversion circuit 20.
The LPF circuit 19 generates a Q signal S19 by removing the high frequency component of the Q signal S16, and outputs this to the A / D conversion circuit 21.
[0038]
The oscillation circuit 22 generates an oscillation signal S22 having the same frequency as the predetermined sampling frequency of the reception signal S10, and outputs this to the A / D conversion circuits 20 and 21.
Here, the sampling frequency is set to be larger than twice the symbol rate Rs for convenience of symbol timing reproduction (carrier reproduction).
[0039]
Based on the oscillation signal from the oscillation circuit 22, the A / D conversion circuit 20 performs A / D conversion of the I signal S 18 to generate a digital I signal S 20, and outputs this to the digital amplification circuit 23.
The A / D conversion circuit 21 performs A / D conversion of the Q signal S 19 based on the oscillation signal from the oscillation circuit 22 to generate a digital Q signal S 21, and outputs this to the digital amplification circuit 23.
[0040]
Based on the amplification factor α indicated by the amplification factor control signal S50 from the AGC circuit 50, the digital amplifier circuit 23 amplifies the I signal S20 from the A / D conversion circuit 20 to generate an I signal S23, and interpolates this. It outputs to the circuit 28.
Here, the amplification factor α satisfies, for example, “0 ≦ α ≦ 1”.
FIG. 2A is a configuration diagram of the digital amplifier circuit 23.
As shown in FIG. 2A, the digital amplifier circuit 23 includes a multiplier circuit 80 and an adder circuit 81.
In the digital amplifier circuit 23, the I signal S 20 from the A / D conversion circuit 20 shown in FIG. 1 is output to the multiplication circuit 80 and the addition circuit 81.
In the multiplication circuit 80, the I signal S20 is multiplied by the amplification factor control signal S50 indicating the amplification factor α, and a signal S80 as a result of the multiplication is output to the addition circuit 81.
In the adder circuit 81, the I signal S20 and the signal S80 are added, and an I signal S23 as a result of the addition is output to the interpolation circuit 28 shown in FIG.
The digital amplifier circuit 23 amplifies the I signal S20 by (1 + α) times to generate an I signal S23.
The digital amplifying circuit 23 serves to supplementarily correct a portion that cannot be corrected by the AGC processing of the analog amplifying circuit 15, and the range that can be corrected may be narrow.
When the digital amplifier 23 performs amplitude correction of about ± 25% at maximum with respect to the 8-bit I signal S20, the multiplier circuit 80 shown in FIG. It can be realized with a circuit.
[0041]
The digital amplifier circuit 24 amplifies the Q signal S21 from the A / D conversion circuit 21 based on the amplification factor α indicated by the amplification factor control signal S50 from the AGC circuit 50, generates a Q signal S24, and interpolates this. Output to the circuit 29.
FIG. 2B is a configuration diagram of the digital amplifier circuit 24.
As shown in FIG. 2B, the digital amplifier circuit 24 includes a multiplier circuit 82 and an adder circuit 83.
In the digital amplifier circuit 24, the Q signal S 21 from the A / D conversion circuit 21 shown in FIG. 1 is output to the multiplication circuit 82 and the addition circuit 83.
In the multiplication circuit 82, the Q signal S 21 is multiplied by the amplification factor control signal S 50 indicating the amplification factor α, and a signal S 82 that is the multiplication result is output to the addition circuit 83.
In the adder circuit 83, the Q signal S21 and the signal S82 are added, and a Q signal S24 as a result of the addition is output to the interpolation circuit 29 shown in FIG.
The digital amplifier circuit 24 amplifies the Q signal S21 by (1 + α) times to generate a Q signal S24.
The digital amplifier circuit 24 serves to supplementarily correct a portion that cannot be corrected by the AGC processing of the analog amplifier circuit 16, and the range that can be corrected may be narrow.
When the digital amplification circuit 24 performs amplitude correction of about ± 25% at maximum with respect to the 8-bit Q signal S21, the multiplication circuit 82 shown in FIG. It can be realized with a circuit.
[0042]
The interpolation circuit 28 generates an I signal S28 by interpolating the I signal S23 based on the symbol timing signal S46 from the symbol timing reproduction circuit 46 so that the soft decision circuit 45 can determine the symbol at an appropriate timing. To do.
The interpolation circuit 29 generates a Q signal S29 by performing an interpolation process on the Q signal S24 based on the symbol timing signal S46 from the symbol timing reproduction circuit 46 so that the soft decision circuit 45 can determine the symbol at an appropriate timing. To do.
[0043]
The complex multiplication circuit 30 uses the signals S36 and S37 for carrier reproduction (for frequency acquisition and phase synchronization) from the signal conversion circuits 36 and 37, and based on the following equation (1), the I signal S28 and the Q signal S29. Are subjected to frequency pull-in processing and phase synchronization processing to generate an I signal S30a and a Q signal S30b.
[0044]
[Expression 1]

[0045]
FIG. 3 is a configuration diagram of the complex multiplication circuit 30.
As shown in FIG. 3, the complex multiplication circuit 30 includes multiplication circuits 60, 61, 62, 63 and addition circuits 64, 65.
In the complex multiplication circuit 30, the Q signal S 29 from the interpolation circuit 29 shown in FIG. 1 is input to the multiplication circuits 60 and 61.
Further, the I signal S28 from the interpolation circuit 28 shown in FIG.
Further, a signal S 36 having a SIN characteristic from the signal conversion circuit 36 is output to the multiplication circuits 61 and 63.
A signal S37 having COS characteristics from the signal conversion circuit 37 is output to the multiplication circuits 60 and 62.
[0046]
Then, the multiplication circuit 60 multiplies the Q signal S29 and the signal S37, and outputs the multiplication result signal S60 to the addition circuit 65.
Further, the multiplication circuit 61 multiplies the Q signal S29 and the signal S36 and outputs a signal S61 as a result of the multiplication to the addition circuit 64.
Further, the multiplication circuit 62 multiplies the I signal S28 and the signal S37, and the multiplication result signal S62 is output to the addition circuit 64.
Further, the multiplication circuit 63 multiplies the I signal S20 and the signal S43, and the multiplication result signal S63 is output to the addition circuit 65.
[0047]
In addition circuit 65, signal S63 is subtracted from signal S60, and the subtraction result is Q signal S30b.
In addition, the addition circuit 64 adds the signal S61 and the signal S62, and the addition result is the I signal S30a.
[0048]
The roll-off filter circuit 31 performs filter processing for reducing the intersymbol interference on the I signal S30a to generate an I signal S31, which is generated by the phase detection circuit 33, the soft decision circuit 45, the symbol timing recovery circuit 46, and the AGC. Output to the circuit 47.
The roll-off filter circuit 32 performs a filter process for reducing intersymbol interference on the Q signal S30b to generate a Q signal S32, which is generated as a phase detection circuit 33, a soft decision circuit 45, a symbol reproduction circuit 46, and an AGC circuit. Output to 47.
In the present embodiment, the case where the roll-off filter circuits 31 and 32 are configured in the Costas loop 55 is exemplified, but these may be installed immediately after the interpolation circuits 28 and 29.
[0049]
The phase detection circuit 33 detects a phase determined by the I signal S31 and the Q signal S32, and outputs a phase signal S33 indicating the phase to the loop filter circuit 34.
[0050]
The loop filter circuit 34 removes the high frequency component of the phase signal S33 to generate the phase signal S34, and outputs this to the numerically controlled oscillation circuit 35.
[0051]
The numerically controlled oscillation circuit 35 is a cumulative addition circuit that does not prohibit overflow, performs an addition operation up to its dynamic range in accordance with the value of the phase signal S34, enters an oscillation state, and sets an oscillation frequency in accordance with the value of the phase signal S34. A signal S35 is generated and output to the signal conversion circuits 36 and 37. That is, the numerically controlled oscillation circuit 35 digitally performs the same operation as the voltage controlled oscillation circuit (VCO) in the analog circuit.
FIG. 4 is a configuration diagram of the numerically controlled oscillation circuit 35.
As shown in FIG. 4, the numerically controlled oscillation circuit 35 includes an adder circuit 70, a latch circuit 71, and an amplifier circuit 72.
In the numerically controlled oscillation circuit 35, the adder circuit 70 adds the 8-bit signal S34 input from the loop filter circuit 34 shown in FIG. 1 and the 16-bit signal S71 output from the latch circuit 71 to add a 16-bit signal. A signal S70 is generated. The signal S70 is output to the latch circuit 71.
In the latch circuit 71, the signal S70 is delayed by one system clock cycle, and is output to the adder circuit 70 and the amplifier circuit 72 as the signal S71.
In the amplifier circuit 72, the 16-bit signal S71 is 2^-8Amplified twice to generate an 8-bit signal S35.
The signal S35 is output to the signal conversion circuits 43 and 44.
[0052]
FIG. 5 is a diagram for explaining the operation of the numerically controlled oscillation circuit 35, and shows a change in the value of the signal S 71 output from the latch circuit 71.
As shown in FIG. 5, in the latch circuit 71, when the signal S70 overflows, the value of the signal S71 is set to zero. Further, according to the value of the signal S70, that is, according to the value of the signal S41, the slope of the signal S71 increases and the cycle changes. Specifically, the larger the value of the signal S41, the shorter the cycle of the signal S71, that is, the higher the frequency. According to the numerically controlled oscillation circuit 35, a signal S35 having a frequency up to ½ of the frequency of the system clock signal can be generated. The frequency resolution of the numerically controlled oscillation circuit 35 is (system clock signal frequency) × 2^-16become.
[0053]
The signal conversion circuit 36 has a ROM storing an 8-bit resolution signal having a SIN characteristic as shown in FIG. 4, and a SIN characteristic signal read from the ROM in response to a signal S35 from the numerical control oscillation circuit 35. S36 is output to the complex multiplication circuit 30.
As shown in FIG. 4, the signal conversion circuit 37 has a ROM storing an 8-bit resolution signal having a COS characteristic, and a COS characteristic signal read from the ROM in accordance with a signal S35 from the numerical control oscillation circuit 35. S37 is output to the complex multiplication circuit 30.
[0054]
Here, the complex multiplier circuit 30, the roll-off filter circuits 31, 32, the phase detection circuit 33, the loop filter circuit 34, the numerically controlled oscillation circuit 35, and the signal conversion circuits 36, 37 constitute a Costas Loop circuit 55. The
[0055]
The soft decision circuit 45 makes a soft decision between the I signal S31 from the roll-off filter circuit 31 and the Q signal S32 from the roll-off filter circuit 32, and outputs the result to a subsequent error correction circuit. Then, after error correction, a reproduction signal is generated using the I signal and the Q signal.
[0056]
The symbol timing recovery circuit 46 detects the symbol timing of the I signal S31 and the Q signal S32 from the roll-off filter circuits 31 and 32, and outputs a symbol timing signal S46 corresponding to the result to the interpolation circuits 28 and 29.
[0057]
The AGC circuit 47 uses the amplitude values of the I signal S31 and the Q signal S32 so that processing can be performed using stable and appropriate amplitude in the subsequent circuits of the A / D conversion circuits 20 and 21. , 16 is generated with a resolution of, for example, 8 bits, and is output to the PWM signal generation circuit 48.
For example, the AGC circuit 47 has the same configuration as the configuration shown in FIG.
[0058]
The PWM signal generation circuit 48 converts the digital amplification factor control signal S47 into an amplification factor control signal S48 that is a PWM signal for obtaining an analog signal, and outputs this to the low-pass filter 49.
The low-pass filter 49 removes the high frequency component of the amplification factor control signal S48, generates an analog amplification factor control signal S49, and outputs it to the analog amplification circuits 15 and 16.
[0059]
The AGC circuit 50 integrates the temporal change of the amplification factor control signal S47 from the AGC circuit 47 shown in FIG. 1 to generate an amplification factor control signal S50 indicating the amplification factor α. 24.
FIG. 6 is a configuration diagram of the AGC circuit 50.
As shown in FIG. 6, it has a delay circuit 90, adder circuits 91 and 92, a delay circuit 93, and an amplifier circuit 94.
In the AGC circuit 50, the amplification factor control signal S47 from the AGC circuit 47 shown in FIG. 1 is output to the delay circuit 90 and the adder circuit 91.
Next, the delay circuit 90 and the adder circuit 91 detect the time change of the amplification factor control signal S47, and the signal S91 indicating the detected time change is output to the adder circuit 92.
Next, the signal S91 is integrated by the adder circuit 92 and the delay circuit 93, and the resulting signal S93 is output to the amplifier circuit 94.
Next, the signal S93 is amplified by the amplifier circuit 94 to generate an amplification factor control signal S50.
[0060]
Hereinafter, the operation of the receiving apparatus 1 will be described.
The in-phase component of the received signal S10 received via the satellite repeater is detected by the in-phase detection circuit 12 using the local oscillation signal S11, and a baseband I signal S12 is generated.
In parallel with this, the quadrature component of the received signal S10 is detected by the quadrature detection circuit 14 using the local generation signal S13 having a 90-degree phase difference with the local oscillation signal S11, and a baseband Q signal S14 is generated. Is done.
[0061]
By the amplification process based on the amplification factor control signal S49 in the analog amplifier circuit 15, the I signal S15 is generated from the I signal S12.
Through the LPF process in the LPF circuit 18 and the A / D conversion process in the A / D conversion circuit 20, an I signal S20 is generated from the I signal S15.
Next, in the digital amplifier circuit 23 shown in FIG. 2A, the I signal S23 is generated from the I signal S20 based on the amplification factor control signal S50 from the AGC circuit 50.
Next, in the interpolation circuit 28, the I signal S23 is interpolated based on the symbol timing signal S46 from the symbol timing reproduction circuit 46 so that the soft decision circuit 45 can determine the symbol at an appropriate timing. A signal S28 is generated.
[0062]
Further, the following Q signal processing is performed in parallel with the above-described I signal processing.
That is, the Q signal S16 is generated from the Q signal S14 by the amplification process based on the amplification factor control signal S49 in the analog amplifier circuit 16.
Through the LPF process in the LPF circuit 19 and the A / D conversion process in the A / D conversion circuit 21, a Q signal S21 is generated from the Q signal S16.
Next, in the digital amplifier circuit 24 shown in FIG. 2B, the Q signal S24 is generated from the Q signal S21 based on the amplification factor control signal S50 from the AGC circuit 50.
Next, in the interpolation circuit 29, the Q signal S24 is interpolated based on the symbol timing signal S46 from the symbol timing reproduction circuit 46 so that the soft decision circuit 45 can determine the symbol at an appropriate timing. A signal S29 is generated.
[0063]
Then, in the Costas loop circuit 55, frequency pull-in processing and phase synchronization processing of the I signal S28 and the Q signal S29 are performed.
In the process, the I signal S31 and the Q signal S32 from the roll-off filter circuits 31 and 32 are output to the AGC circuit 47.
With the configuration shown in FIG. 13, the AGC circuit 47 sets the amplitude values of the I signal S31 and the Q signal S32 so that processing using stable and appropriate amplitudes can be performed in the subsequent circuits of the A / D conversion circuits 20 and 21. The digital amplification factor control signal S47 for controlling the amplification factors of the amplifier circuits 15 and 16 is generated with a resolution of, for example, 8 bits.
The digital amplification factor control signal S47 is converted into an amplification factor control signal S48, which is a PWM signal for obtaining an analog signal, in the PWM signal generation circuit 48 and output to the low-pass filter 49.
When the high frequency component is removed by the low-pass filter 49, the gain control signal S48 becomes an analog gain control signal S49 and is output to the amplifier circuits 15 and 16.
[0064]
Further, in the AGC circuit 50 shown in FIG. 6, the time change of the amplification factor control signal S47 is integrated to generate an amplification factor control signal S50 indicating the amplification factor α, and the amplification factor control signal S50 is converted into the digital amplification circuit 23, 24.
[0065]
As described above, according to the receiving apparatus 1, in addition to the conventional control of the amplification factors of the analog amplifier circuits 15 and 16 by the AGC circuit 47, the amplification factor control signal S47 generated by the AGC circuit 47 is used. The gain control of the digital amplifier circuits 23 and 24 is performed by the AGC circuit 50 used.
Here, in the AGC circuit 50, the gain control signal S50 having a change amount equal to or less than the resolution of the AGC circuit 47 is obtained by integrating the time change of the gain control signal S47, and the gain control signal S50 is used to digitally The amplification factors of the amplifier circuits 23 and 24 are controlled. As a result, in the AGC circuit 47 shown in FIG. 13, it is possible to suppress a minute amplitude vibration that is continuously generated in the amplification factor control signal S47 due to the fact that the signal S152 and the reference amplitude signal S160 do not actually completely match. . As a result, according to the receiving apparatus 121, the amplitude of the symbol data of the received signal at the time of demodulation can be optimized, and the characteristics of the receiving apparatus 1 can be improved compared to the conventional receiving apparatus 100 described above.
[0066]
That is, in the receiving apparatus 1, the AGC circuit 50 and the digital amplifier circuits 23 and 24 serve to supplementarily correct portions that cannot be corrected by the AGC circuit 47 and the analog amplifier circuits 15 and 16.
[0067]
Second embodiment
FIG. 7 is a configuration diagram of the receiving device 121 of the present embodiment.
As illustrated in FIG. 7, the reception device 121 includes, for example, an input terminal 10, a local oscillation circuit 11, an in-phase detection circuit 12, a phase shift circuit 13, a quadrature detection circuit 14, analog amplification circuits 15 and 16, and LPF circuits 18 and 19. A / D conversion circuits 20 and 21, oscillation circuit 22, digital amplification circuits 23 and 24, correction circuits 28 and 29, complex multiplication circuit 30, roll-off filter circuits 31 and 32, phase detection circuit 33, loop filter circuit 34, A numerical control oscillation circuit 35, signal conversion circuits 36 and 37, a soft decision circuit 45, a symbol timing reproduction circuit 46, an AGC (Auto Gain Control) circuit 47, a PWM signal generation circuit 48, a low-pass filter 49, and an IQ amplitude error correction circuit 51 Have.
[0068]
The receiving apparatus 121 illustrated in FIG. 7 corresponds to the receiving apparatus according to the eighth aspect.
The correspondence between the constituent elements shown in FIG. 7 and the constituent elements of claim 8 is as follows. The in-phase detection circuits 12 and 14 correspond to the separation circuit of the present invention, the analog amplification circuit 15 corresponds to the analog amplification circuit of the present invention, and the A / D conversion circuits 20 and 21 correspond to the A / D conversion circuit of the present invention. The digital amplifier circuit 24 corresponds to the first digital amplifier circuit of the present invention, the digital amplifier circuit 23 corresponds to the second digital amplifier circuit of the present invention, and the AGC circuit 47 corresponds to the first amplification control of the present invention. Corresponding to the circuit, the IQ amplitude error correction circuit 51 corresponds to the second amplification control circuit of the present invention.
[0069]
In FIG. 7, the constituent elements having the same reference numerals as those in FIG. 1 are the same as the constituent elements having the same reference numerals described in the first embodiment.
That is, the receiving apparatus 121 has a configuration in which an IQ amplitude error correction circuit 51 and a sign determination circuit 120 are added instead of the AGC circuit 50 from the receiving apparatus 1 shown in FIG.
[0070]
Hereinafter, the IQ amplitude error correction circuit 51 will be described.
FIG. 8 is a block diagram of the IQ amplitude error correction circuit 51 shown in FIG.
As shown in FIG. 8, the IQ amplitude error correction circuit 51 includes absolute value generation circuits 110 and 111, a subtraction circuit 112, an addition circuit 113, a delay circuit 114, and an amplification circuit 115.
In the IQ amplitude error correction circuit 51, the I signal S31 from the roll-off filter circuit 31 shown in FIG.
In the absolute value generation circuit 110, a signal S110 indicating the absolute value of the I signal S31 is generated and output to the subtraction circuit 112.
Further, the Q signal S32 from the roll-off filter circuit 32 shown in FIG.
In the absolute value generation circuit 111, a signal S111 indicating the absolute value of the Q signal S32 is generated and output to the subtraction circuit 112.
[0071]
Next, in the subtraction circuit 112, the signal S111 is subtracted from the signal S110, and the signal S112, which is the result of the subtraction, is output to the addition circuit 113.
Next, the signal S 112 is integrated by the adder circuit 113 and the delay circuit 114, and the signal S 114 as a result of the integration is output to the amplifier circuit 115.
Next, in the amplification circuit 115, the signal S114 is amplified to generate an amplification factor control signal S51 indicating the amplification factor β.
Here, the amplification factor α satisfies, for example, “0 ≦ α ≦ 1”.
The amplification factor control signal S51 is output from the IQ amplitude error correction circuit 51 to the digital amplification circuit 23 and the sign determination circuit 120 shown in FIG.
In the sign determination circuit 120, the sign of the amplification factor control signal S51 is inverted, and for example, an amplification factor control signal S120 indicating the amplification factor −β is output to the digital amplification circuit 23.
[0072]
The digital amplifier circuits 23 and 24 have the same configuration as that of the first embodiment described above, but not the amplification factor control signal S50, but the amplification factor control signal S120 and the amplification factor β that respectively indicate the amplification factor −β. The I signal S20 and the Q signal S21 from the A / D conversion circuits 20 and 21 are amplified by (1−β) times and (1 + β) times based on the amplification factor control signal S51 indicating I signal S23 and Q signal. S24 is generated.
[0073]
FIG. 9A is a diagram for explaining the operation of the digital amplifier circuit 23 of the present embodiment.
In the digital amplifier circuit 23 of the present embodiment, the I signal S20 from the A / D conversion circuit 20 shown in FIG. 7 is output to the multiplication circuit 80 and the addition circuit 81.
In the multiplication circuit 80, the I signal S20 is multiplied by the amplification factor control signal S120 indicating the amplification factor −β, and a signal S80 as a result of the multiplication is output to the addition circuit 81.
In the adder circuit 81, the I signal S20 and the signal S80 are added, and an I signal S23 as a result of the addition is output to the interpolation circuit 28 shown in FIG.
The digital amplifier circuit 23 of the present embodiment amplifies the I signal S20 by (1−β) times to generate the I signal S23.
[0074]
FIG. 9B is a diagram for explaining the operation of the digital amplifier circuit 24 of the present embodiment.
In the digital amplifier circuit 24 of the present embodiment, the Q signal S21 from the A / D conversion circuit 21 shown in FIG. 7 is output to the multiplication circuit 82 and the addition circuit 83.
In the multiplication circuit 82, the Q signal S21 and the amplification factor control signal S51 indicating the amplification factor β are multiplied, and the multiplication result signal S82 is output to the addition circuit 83. In the adder circuit 83, the Q signal S21 and the signal S82 are added, and a Q signal S24 as a result of the addition is output to the interpolation circuit 29 shown in FIG.
The digital amplifier circuit 24 of the present embodiment amplifies the Q signal S21 by (1 + β) times to generate the Q signal S24.
[0075]
The operation of the receiving device 121 will be described.
In the receiving device 121, the received signal S10 received via the satellite repeater undergoes the same processing as that of the receiving device 1 of the first embodiment described above, and then is transferred from the A / D conversion circuits 20 and 21 to the digital amplifier circuits 23 and 24. , I signal S20 and Q signal S21 are output.
Further, the I signal S31 and the Q signal S32 from the subsequent roll-off filter circuits 31 and 32 are input to the IQ amplitude error correction circuit 51, and the IQ amplitude error correction circuit 51 shown in FIG. An amplification factor control signal S51 corresponding to a value obtained by integrating the difference from the amplitude of the signal S32 is generated.
The amplification factor control signal S51 is output to the digital amplifier circuit 24 and the sign determination circuit 120.
Then, the sign determination circuit 120 inverts the sign of the amplification factor control signal S51 indicating the amplification factor β to the digital amplification circuit 23 to generate an amplification factor control signal S120 indicating the amplification factor −β. It is output to the digital amplifier circuit 23.
[0076]
Then, in the digital amplifier circuits 23 and 24, amplification processing is performed so as to suppress an error between the amplitude of the I signal S20 and the amplitude of the Q signal S21, and the I signal S23 and the Q signal S24 are generated.
Then, the processes of the interpolation circuits 28 and 29 and the Costas loop circuit 55 are performed on the I signal S23 and the Q signal S24 as in the case of the first embodiment described above.
[0077]
As described above, in the receiving apparatus 121, the IQ amplitude error correction circuit 51 integrates the error of the absolute values of the amplitudes of the I signal S31 and the Q signal S32, so that the amplitude of the I signal and that of the Q signal are integrated. The amplification factors of the digital amplifier circuits 23 and 24 can be controlled so as to suppress a stationary error between them.
As a result, IQ amplitude errors caused by variations in characteristics of analog circuits such as the in-phase detection circuit 12 and the quadrature detection circuit 14 can be appropriately suppressed, and the bit error rate at the time of demodulation can be improved as compared with the prior art.
Further, in the receiving device 121, it is possible to relax the demand for the performance of analog circuits such as the in-phase detection circuit 12 and the quadrature detection circuit 14, and the configuration can be simplified and the price can be reduced.
[0078]
Third embodiment
FIG. 10 is a configuration diagram of the receiving device 131 of the present embodiment.
As shown in FIG. 1, the receiving device 1 includes, for example, an input terminal 10, a local oscillation circuit 11, an in-phase detection circuit 12, a phase shift circuit 13, a quadrature detection circuit 14, analog amplification circuits 15 and 16, and LPF circuits 18 and 19. A / D conversion circuits 20 and 21, oscillation circuit 22, digital amplification circuits 23 and 24, correction circuits 28 and 29, complex multiplication circuit 30, roll-off filter circuits 31 and 32, phase detection circuit 33, loop filter circuit 34, Numerical control oscillation circuit 35, signal conversion circuits 36 and 37, soft decision circuit 45, symbol timing recovery circuit 46 and AGC (Auto Gain Control) circuit 47, PWM signal generation circuit 48, low-pass filter 49, AGC circuit 50, IQ amplitude error A correction circuit 51 and addition circuits 52 and 53 are provided.
In FIG. 10, the constituent elements having the same reference numerals as those in FIG. 1 are the same as the constituent elements having the same reference numerals described in the first embodiment.
That is, the receiving apparatus 121 is configured by adding an IQ amplitude error correction circuit 51, a subtracting circuit 52, and an adding circuit 53 to the AGC circuit 50 from the receiving apparatus 1 shown in FIG.
The IQ amplitude error correction circuit 51 is the same as that shown in FIG. 8 described in the second embodiment.
[0079]
A receiving apparatus 131 shown in FIG. 10 corresponds to the receiving apparatus described in claim 11.
The correspondence between the components shown in FIG. 10 and the components of claim 11 is as follows. The in-phase detection circuits 12 and 14 correspond to the separation circuit of the present invention, the analog amplification circuit 15 corresponds to the analog amplification circuit of the present invention, and the A / D conversion circuits 20 and 21 correspond to the A / D conversion circuit of the present invention. The digital amplifier circuit 24 corresponds to the first digital amplifier circuit of the present invention, the digital amplifier circuit 23 corresponds to the second digital amplifier circuit of the present invention, and the AGC circuit 47 corresponds to the first amplification control of the present invention. Corresponding to the circuit, the AGC circuit 50, the IQ amplitude error correction circuit 51, the subtraction circuit 52, and the addition circuit 53 correspond to the second amplification control circuit of the present invention.
[0080]
In the receiving device 131, the gain control signal S50 indicating the gain α is input from the AGC circuit 50 shown in FIG. 6 described in the first embodiment to the adder circuits 52 and 53.
Here, the amplification factor α satisfies, for example, “0 ≦ α ≦ 1”.
Further, the amplification factor control signal S51 indicating the amplification factor β is input to the addition circuits 52 and 53 from the IQ amplitude error correction circuit 51 shown in FIG. 8 described in the second embodiment.
Here, the amplification factor β satisfies, for example, “0 ≦ β ≦ 1”.
[0081]
Then, the subtraction circuit 52 subtracts the amplification factor control signal S51 from the amplification factor control signal S50, and outputs the amplification factor control signal S52 indicating “α−β” as the subtraction result to the digital amplification circuit 23.
Further, the addition circuit 53 adds the amplification factor control signal S50 and the amplification factor control signal S51, and outputs the amplification factor control signal S53 indicating “α + β” as the addition result to the digital amplification circuit 24.
[0082]
The digital amplifier circuits 23 and 24 have the same configuration as that of the first embodiment described above, but not the amplification factor control signal S50, but the amplification factor control signal S120 and the amplification factor β that respectively indicate the amplification factor −β. The I signal S20 and the Q signal S21 from the A / D conversion circuits 20 and 21 are amplified (1−β) times and (1 + β) times based on the amplification factor control signal S51 indicating I signal S23 and Q signal. S24 is generated.
[0083]
FIG. 11A is a configuration diagram of the digital amplifier circuit 23 of the present embodiment.
In the digital amplifier circuit 23 of the present embodiment, the I signal S20 from the A / D conversion circuit 20 shown in FIG. 10 is output to the multiplication circuit 80 and the addition circuit 81.
In the multiplication circuit 80, the I signal S 20 is multiplied by the amplification factor control signal S 52 indicating the amplification factor “α−β”, and a signal S 80 that is the multiplication result is output to the addition circuit 81.
In the adder circuit 81, the I signal S20 and the signal S80 are added, and an I signal S23 as a result of the addition is output to the interpolation circuit 28 shown in FIG.
The digital amplifier circuit 23 of this embodiment amplifies the I signal S20 by (1 + α−β) times to generate the I signal S23.
[0084]
FIG. 11B is a diagram for explaining the operation of the digital amplifier circuit 24 of the present embodiment.
In the digital amplifier circuit 24 of the present embodiment, the Q signal S21 from the A / D conversion circuit 21 shown in FIG. 10 is output to the multiplication circuit 82 and the addition circuit 83.
In the multiplication circuit 82, the Q signal S 21 is multiplied by the amplification factor control signal S 53 indicating the amplification factor “α + β”, and a signal S 82 that is the multiplication result is output to the addition circuit 83.
In the adder circuit 83, the Q signal S21 and the signal S82 are added, and a Q signal S24 as a result of the addition is output to the interpolation circuit 29 shown in FIG.
The digital amplifier circuit 24 of the present embodiment amplifies the Q signal S21 by (1 + α + β) times to generate the Q signal S24.
[0085]
The receiving device 131 can exhibit both the effects of the receiving device 1 of the first embodiment described above and the effects of the receiving device 121 of the second embodiment.
That is, according to the receiving device 131, in the AGC circuit 47 shown in FIG. 13, the minute amplitude vibration continuously generated in the amplification factor control signal S47 due to the fact that the signal S152 and the reference amplitude signal S160 do not actually completely coincide with each other. And a steady error between the amplitude of the I signal and the amplitude of the Q signal can be suppressed.
[0086]
【The invention's effect】
As described above, according to the receiving apparatus and method of the present invention, the received signal can be processed in a stable state, so that, for example, the characteristics of demodulation processing can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a receiving apparatus according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of the digital amplifier circuit shown in FIG. 1;
FIG. 3 is a configuration diagram of the complex multiplication circuit shown in FIG. 1;
4 is a block diagram of the numerically controlled oscillation circuit shown in FIG. 1. FIG.
5 is a diagram for explaining the operation of the numerically controlled oscillation circuit shown in FIG. 4, and is a diagram showing a change in the value of a signal output from a latch circuit. FIG.
FIG. 6 is a configuration diagram of the AGC circuit shown in FIG. 1;
FIG. 7 is a configuration diagram of a receiving apparatus according to a second embodiment of the present invention.
FIG. 8 is a configuration diagram of the IQ amplitude error correction circuit shown in FIG. 7;
9 is a diagram for explaining the operation of the digital amplifier circuit shown in FIG. 7; FIG.
FIG. 10 is a configuration diagram of a receiving device according to a third embodiment of the present invention.
11 is a configuration diagram of the digital amplifier circuit shown in FIG. 10;
FIG. 12 is a configuration diagram of a conventional receiving apparatus.
FIG. 13 is a configuration diagram of the AGC circuit shown in FIG. 12;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Input terminal, 11 ... Local oscillation circuit, 12 ... In-phase detection circuit, 13 ... Phase shift circuit, 14 ... Quadrature detection circuit, 15, 16 ... Amplifier circuit, 17, 18, 19 ... LPF circuit, 20, 21 ... A / D conversion circuit, 23, 24 ... digital amplification circuit, 28, 29 ... interpolation circuit, 30 ... complex multiplication circuit, 31, 32 ... roll-off filter circuit, 33 ... phase detection circuit, 34 ... loop filter circuit, 35 ... numerical value Control oscillation circuit, 36, 37 ... signal conversion circuit, 45 ... soft decision circuit, 46 ... symbol reproduction circuit, 47 ... AGC circuit, 48 ... PWM signal generation circuit, 49 ... low pass filter, 50 ... AGC circuit, 51 ... IQ amplitude Error correction circuit, 120... Sign inversion circuit

Claims (20)

An analog amplification circuit for amplifying an analog reception signal based on the first amplification factor control signal;
An A / D conversion circuit for A / D converting the amplified received signal;
A digital amplification circuit for amplifying a digital reception signal obtained by the A / D conversion based on a second amplification factor control signal;
A first amplification control circuit that detects a difference between an amplitude of the digital reception signal and a predetermined reference amplitude and generates the first amplification factor control signal so as to reduce the detected difference;
A receiving apparatus comprising: a second amplification control circuit that integrates a temporal change in amplitude of the first amplification factor control signal to generate the second amplification factor control signal. When the second gain control signal indicates a coefficient α,
The receiving apparatus according to claim 1, wherein the digital amplifying circuit amplifies a digital received signal obtained by the A / D conversion by (1 + α) times. The receiving apparatus according to claim 2, wherein the coefficient α satisfies −1 ≦ α ≦ 1. A multiplication circuit for multiplying a digital reception signal amplified by the digital amplification circuit and a feedback signal;
A phase detection circuit that detects a phase of a signal output from the multiplication circuit and generates a phase signal;
A numerical control circuit for generating the feedback signal of the oscillation frequency according to the phase signal,
The first amplification control circuit detects a difference between an amplitude of a signal output from the multiplication circuit and a predetermined reference amplitude, and reduces the detected difference so as to reduce the detected difference. The receiving apparatus according to claim 1, wherein the receiving apparatus generates a control signal. A separation circuit that separates the phase-modulated analog reception signal into a signal of an in-phase component and a signal of a quadrature component of a carrier;
An analog amplification circuit that amplifies the in-phase component signal and the quadrature component signal based on a first amplification factor control signal;
An A / D conversion circuit for A / D converting the amplified in-phase component signal and quadrature component signal;
A digital amplification circuit that amplifies the in-phase component signal and the quadrature component signal obtained by the A / D conversion based on a second amplification factor control signal;
A processing circuit that performs frequency pull-in processing and phase synchronization processing of the in-phase component signal and the quadrature component signal obtained from the digital amplifier circuit;
The first gain control signal is detected so as to detect a difference between an amplitude obtained from the in-phase component signal and the quadrature component signal from the processing circuit and a predetermined reference amplitude, and to reduce the detected difference. A first amplification control circuit for generating
The second gain control signal is generated by integrating the time change of the amplitude of the first gain control signal and using the integration result so that the amplitude of the first gain control signal is reduced. And a second amplification control circuit. When the second gain control signal indicates a coefficient α,
The receiving apparatus according to claim 5, wherein the digital amplifying circuit amplifies the digital received signal obtained by the A / D conversion by (1 + α) times. The second amplification control circuit includes:
Generating the digital second gain control signal;
The receiving device is:
The receiving apparatus according to claim 5, further comprising a conversion circuit that converts the digital second amplification factor control signal into analog and outputs the analog second amplification signal to the first analog amplification circuit and the analog amplification circuit. A separation circuit that separates the phase-modulated analog reception signal into a signal of an in-phase component and a signal of a quadrature component of a carrier;
An analog amplification circuit that amplifies the in-phase component signal and the quadrature component signal based on a first amplification factor control signal;
An A / D conversion circuit for A / D converting the amplified in-phase component signal and the quadrature component signal;
A first digital amplification circuit that amplifies the signal of the orthogonal component obtained by the A / D conversion based on a second amplification factor control signal;
A second digital amplification circuit that amplifies the in-phase component signal obtained by the A / D conversion based on a third amplification factor control signal;
The difference between the amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the A / D conversion and a predetermined reference amplitude is detected, and the first difference is reduced so as to reduce the detected difference. A first amplification control circuit for generating an amplification factor control signal;
The second amplification factor control signal is integrated so that the difference in amplitude between the in-phase component signal and the quadrature component signal obtained by the A / D conversion is integrated, and the difference is reduced using the integration result. And a second amplification control circuit for generating the third amplification factor control signal. The second amplification control circuit generates the second amplification factor control signal indicating a coefficient β and the third amplification factor control signal indicating a coefficient (−β),
The first digital amplification circuit amplifies the orthogonal component signal obtained by the A / D conversion by (1 + β) times based on the second amplification factor control signal,
9. The second digital amplifier circuit according to claim 8, wherein the in-phase component signal obtained by the A / D conversion is amplified by (1-β) times based on the third amplification factor control signal. Receiver device. The receiving apparatus according to claim 9, wherein the coefficient β satisfies −1 ≦ β ≦ 1. A separation circuit that separates the phase-modulated analog reception signal into a signal of an in-phase component and a signal of a quadrature component of a carrier;
An analog amplification circuit that amplifies the in-phase component signal and the quadrature component signal based on a first amplification factor control signal;
An A / D conversion circuit for A / D converting the amplified in-phase component signal and the quadrature component signal;
A first digital amplification circuit that amplifies the signal of the orthogonal component obtained by the A / D conversion based on a second amplification factor control signal;
A second digital amplification circuit that amplifies the in-phase component signal obtained by the A / D conversion based on a third amplification factor control signal;
The difference between the amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the A / D conversion and a predetermined reference amplitude is detected, and the first difference is reduced so as to reduce the detected difference. A first amplification control circuit for generating an amplification factor control signal;
The fourth gain control signal is generated by integrating the time variation of the amplitude of the first gain control signal, and the amplitude of the in-phase component signal and the quadrature component signal obtained by the A / D conversion is calculated. The difference is integrated to generate a fifth amplification factor control signal, and the signal of the in-phase component obtained by the A / D conversion using the fourth amplification factor control signal and the fifth amplification factor control signal The second amplification factor control signal and the third amplification factor control signal are generated so that the difference in amplitude between the signal and the orthogonal component signal is reduced and the amplitude of the first amplification factor control signal is reduced. And a second amplification control circuit. The second amplification control circuit has the second amplification factor indicating the coefficient (1 + α + β) based on the fourth amplification factor control signal indicating the factor α and the fifth amplification factor control signal indicating the factor β. Generating an amplification factor control signal and the third amplification factor control signal indicating a coefficient (1 + α−β);
The first digital amplification circuit amplifies the orthogonal component signal obtained by the A / D conversion by (1 + α + β) times based on the second amplification factor control signal,
12. The second digital amplifier circuit according to claim 11, wherein the second digital amplifier circuit amplifies the in-phase component signal obtained by the A / D conversion by (1 + α−β) times based on the third amplification factor control signal. Receiver device. Amplifying the analog received signal based on the first gain control signal;
A / D conversion of the amplified received signal,
Amplifying the digital received signal obtained by the A / D conversion based on the second gain control signal;
Detecting the difference between the amplitude of the digital reception signal and a predetermined reference amplitude, and generating the first amplification factor control signal so as to reduce the detected difference;
A receiving method for integrating the time variation of the amplitude of the first gain control signal to generate the second gain control signal. When the second gain control signal indicates a coefficient α,
The reception method according to claim 13, wherein the digital reception signal obtained by the A / D conversion is amplified by (1 + α) times. The digital received signal amplified by the digital amplifier circuit is multiplied by the feedback signal,
Detecting the phase of the signal obtained by the multiplication and generating a phase signal;
Generating the feedback signal of the oscillation frequency according to the phase signal;
The difference between a signal amplitude obtained by multiplication and a predetermined reference amplitude is detected, and the first amplification factor control signal is generated so as to reduce the detected difference. Reception method. The phase-modulated analog received signal is separated into in-phase and quadrature component signals of the carrier,
Amplifying the in-phase component signal and the quadrature component signal based on a first amplification factor control signal;
A / D-convert the amplified in-phase component signal and quadrature component signal,
Based on the second amplification factor control signal, the in-phase component signal and the quadrature component signal obtained by the A / D conversion are amplified,
Perform frequency pull-in processing and phase synchronization processing on the amplified in-phase component signal and quadrature component signal,
The first gain control is performed so as to detect a difference between an amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the processing and a predetermined reference amplitude, and to reduce the detected difference. Generate a signal,
Reception of integrating the time variation of the amplitude of the first amplification factor control signal and generating the second amplification factor control signal so that the amplitude of the first amplification factor control signal is reduced using the integration result Method. The phase-modulated analog received signal is separated into in-phase and quadrature component signals of the carrier,
Amplifying the in-phase component signal and the quadrature component signal based on a first amplification factor control signal;
A / D-convert the amplified in-phase component signal and the quadrature component signal,
Based on the second amplification factor control signal, the signal of the orthogonal component obtained by the A / D conversion is amplified,
Based on the third gain control signal, the signal of the in-phase component obtained by the A / D conversion is amplified,
The difference between the amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the A / D conversion and a predetermined reference amplitude is detected, and the first difference is reduced so as to reduce the detected difference. Generate the gain control signal,
The second amplification factor control signal is integrated so that the difference in amplitude between the in-phase component signal and the quadrature component signal obtained by the A / D conversion is integrated, and the difference is reduced using the integration result. And a reception method for generating the third amplification factor control signal. Generating the second gain control signal indicating the coefficient β and the third gain control signal indicating the coefficient (−β);
Based on the second amplification factor control signal, the signal of the orthogonal component obtained by the A / D conversion is amplified by (1 + β) times,
The reception method according to claim 17, wherein the in-phase component signal obtained by the A / D conversion is amplified by (1−β) times based on the third amplification factor control signal. The phase-modulated analog received signal is separated into in-phase and quadrature component signals of the carrier,
Amplifying the in-phase component signal and the quadrature component signal based on a first amplification factor control signal;
A / D-convert the amplified in-phase component signal and the quadrature component signal,
Based on the second amplification factor control signal, the signal of the orthogonal component obtained by the A / D conversion is amplified,
Based on the third gain control signal, the signal of the in-phase component obtained by the A / D conversion is amplified,
The difference between the amplitude obtained from the in-phase component signal and the quadrature component signal obtained by the A / D conversion and a predetermined reference amplitude is detected, and the first difference is reduced so as to reduce the detected difference. Generate the gain control signal,
Integrating a time variation of the amplitude of the first gain control signal to generate a fourth gain control signal;
Integrating a difference in amplitude between the in-phase component signal and the quadrature component signal obtained by the A / D conversion to generate a fifth amplification factor control signal;
The fourth gain control signal and the fifth gain control signal are used to reduce the difference in amplitude between the in-phase component signal and the quadrature component signal obtained by the A / D conversion, and A receiving method for generating the second gain control signal and the third gain control signal so as to reduce the amplitude of the first gain control signal. Based on the fourth gain control signal indicating the coefficient α and the fifth gain control signal indicating the coefficient β, the second gain control signal indicating the coefficient (1 + α + β) and the coefficient (1 + α A third amplification factor control signal indicating -β),
Based on the second amplification factor control signal, the signal of the orthogonal component obtained by the A / D conversion is amplified by (1 + α + β) times,
The reception method according to claim 19, wherein the in-phase component signal obtained by the A / D conversion is amplified by (1 + α−β) times based on the third amplification factor control signal.

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