JPS6359196A - Delaying device - Google Patents

Delaying device

Info

Publication number
JPS6359196A
JPS6359196A JP20222486A JP20222486A JPS6359196A JP S6359196 A JPS6359196 A JP S6359196A JP 20222486 A JP20222486 A JP 20222486A JP 20222486 A JP20222486 A JP 20222486A JP S6359196 A JPS6359196 A JP S6359196A
Authority
JP
Japan
Prior art keywords
signal
delay
circuit
delayed
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20222486A
Other languages
Japanese (ja)
Other versions
JP2529216B2 (en
Inventor
Yoshio Hirauchi
平内 喜雄
Masanori Hamada
浜田 雅則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61202224A priority Critical patent/JP2529216B2/en
Publication of JPS6359196A publication Critical patent/JPS6359196A/en
Application granted granted Critical
Publication of JP2529216B2 publication Critical patent/JP2529216B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To independently change the quantity of delay of a luminance signal component included in a video signal and the quantity of delay of a chrominance signal component and to simultaneously obtain by repeatedly inputting a part of the video signal to a line memory by the use of a memory of a large capacity. CONSTITUTION:The video signal is inputted from a signal terminal 21, delayed by one line in the line memory 23 using a delay element through a multiplexer 22, distributed in a distribution circuit 24 and supplied to a flip flop 25 and a picture element exchange circuit 26. In the line memory 23 and the picture element exchange circuit 26, a processing is executed by a clock 2 having the clock rate of the frequency twice of the sampling rate of an input signal. In the picture element exchange circuit 26, the two picture elements of the video signal delayed in the line memory 23 are combined to one set, an operation for switching mutual positions is performed and they are guided to a terminal different from a terminal to which the input signal of the multiplexer 22 is supplied. Thereby, the video signal having the partly different quantity of delay can be obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は輝度信号と色信号とが水平走査期間内で時分割
多重され、色信号については広帯域信号と狭帯域信号と
が線順次の形態で伝送されるカラーテレビジョン信号の
処理装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method in which a luminance signal and a chrominance signal are time-division multiplexed within a horizontal scanning period, and for the chrominance signal, a wideband signal and a narrowband signal are transmitted in a line-sequential manner. The present invention relates to a color television signal processing device.

従来の技術 テレビジョン信号のディジタル信号処理において、2次
元処理のために水平走査期間に相当する時間遅延を行な
うラインメモリが利用されている。
BACKGROUND OF THE INVENTION In digital signal processing of television signals, a line memory is utilized which provides a time delay corresponding to a horizontal scanning period for two-dimensional processing.

また3次元処理のためには信号を垂直走査期間。In addition, for three-dimensional processing, the signal needs to be scanned in a vertical scanning period.

遅延させるようなフィールドメモリ等も使用されている
Field memories and the like that cause delays are also used.

テレビジョン信号を伝送する1方法として第5図に示す
ように輝度信号と色信号とを時分割多重し、且つ色信号
については第6図に示すように広帯域信号と狭帯域信号
とを1走査線おきに配置する線順次の形態で伝送するア
ナログコンポーネント伝送方法が考えられるが、このよ
うな信号を処理する上で例えば輝度信号を1ライン遅延
させたものと色信号を2ライン遅延させたものとを同時
に出力させる場合、1ライン分の信号の遅延を行なうラ
インメモリを2段縦続接続し、最終出力から色信号部分
を取り出し、途中のタップより輝度信号部分を取り出し
て処理する方法が一般に多く用いられている。
One method of transmitting television signals is to time-division multiplex the luminance signal and color signal as shown in FIG. An analog component transmission method that transmits data in a line-sequential manner arranged every other line can be considered, but in processing such signals, for example, the luminance signal is delayed by one line, and the color signal is delayed by two lines. When outputting both at the same time, the most common method is to connect two stages of line memories that delay the signal for one line in cascade, extract the chrominance signal part from the final output, and extract the luminance signal part from the taps in the middle for processing. It is used.

以下に本発明に関係する従来例について図面を参照しな
がら説明する。
A conventional example related to the present invention will be described below with reference to the drawings.

第7図は輝度信号と色信号とが時分割多重されて伝送さ
れるテレビジョン信号の、輝度信号部分を1ライン、色
信号部分を2ライン遅延させるための遅延装置の例を示
したものである。
Figure 7 shows an example of a delay device for delaying the luminance signal part by one line and the chrominance signal part by two lines in a television signal in which the luminance signal and chrominance signal are time-division multiplexed and transmitted. be.

信号端子11から入力された映像信号はFIFO(Fi
rst−In First−Out )メモリ等の遅延
素子を用いた第1のラインメモリ12で1ライン遅延さ
れ、第2のラインメモリ13で更に1ライン遅延される
。第1のラインメモリ12の出力は第2のラインメモリ
13の入力になると同時にマルチプレクサ14の一方の
入力となる。また、第2のラインメモリ13の出力はマ
ルチプレクサ14の他方の入力となり、マルチプレクサ
14で水平走査期間内の輝度信号部分と色信号部分とを
区別するための制御信号であるY/C信号により、輝度
信号が伝送されてくる期間は第1のラインメモリ12の
出力である1ライン遅延された輝度信号を、色信号が伝
送されてくる期間は第2のラインメモリ13の出力であ
る2ライン遅延された色信号を選択して信号出力端子1
5へ送り出す。
The video signal input from the signal terminal 11 is sent to the FIFO (Fi
The signal is delayed by one line in the first line memory 12 using a delay element such as a memory (rst-In First-Out), and further delayed by one line in the second line memory 13. The output of the first line memory 12 becomes an input of the second line memory 13 and simultaneously becomes one input of the multiplexer 14. Further, the output of the second line memory 13 becomes the other input of the multiplexer 14, and the multiplexer 14 uses the Y/C signal, which is a control signal to distinguish between the luminance signal part and the color signal part within the horizontal scanning period. During the period when the luminance signal is transmitted, the luminance signal delayed by one line, which is the output of the first line memory 12, is transmitted, and during the period when the color signal is transmitted, the luminance signal, which is the output of the second line memory 13, is delayed by two lines. Select the color signal and connect it to signal output terminal 1.
Send it to 5.

発明が解決しようとする問題点 従来の装置では、上述した構成では輝度信号を1ライン
遅延させたものと色信号を2ライン遅延させたものとを
同時に出力させる場合、1ライン分の容量をもつライン
メモリを2段縦続接続し、最終出力から色信号部分を取
り出し、途中のタップより輝度信号部分を取り出して処
理する構成であるため、映像信号の最大遅延量に等しい
数だけのラインメモリを必要とし、回路規模が大きくな
らざるをえないという問題点を有していた。
Problems to be Solved by the Invention In the conventional device, the above configuration has a capacity for one line when simultaneously outputting a luminance signal delayed by one line and a color signal delayed by two lines. The configuration is such that two stages of line memories are connected in cascade, and the chrominance signal part is taken out from the final output, and the luminance signal part is taken out and processed from an intermediate tap, so a number of line memories equal to the maximum delay amount of the video signal is required. However, there was a problem in that the circuit size had to be large.

本発明はかかる点に鑑み、2ライン以上の容量を持つ1
個の大容量のメモリを用いることで、映像信号に含まれ
る輝度信号成分の遅延量と色信号成分の遅延量とを独立
に変化させて得られる遅延装置を提供することを目的と
する。
In view of this point, the present invention provides a single line having a capacity of two or more lines.
An object of the present invention is to provide a delay device that can independently change the delay amount of a luminance signal component and the delay amount of a color signal component included in a video signal by using a large capacity memory.

問題点を解決するだめの手段 本発明によれば、1水平走査期間信号を遅延する遅延回
路を通過した映像信号のうちの一部分を再度前記遅延回
路を通過させるように構成することにより、1水平走査
期間遅延された信号成分と2水平走査期間遅延された信
号成分とが同時に得られ、また、1水平走査期間信号を
保持する遅延fA 置への入力信号の選択条件を変化さ
せることにより、輝度信号および色信号の遅延量を独立
に1水平走査期間あるいは2水平走査期間のいずれかに
設定でき、異なる遅延量を有する信号成分の、徂み合わ
せが同時に得られることを特徴とする。
Means for Solving the Problems According to the present invention, a portion of the video signal that has passed through the delay circuit that delays the signal for one horizontal scanning period is passed through the delay circuit again. The signal component delayed by the scanning period and the signal component delayed by two horizontal scanning periods are simultaneously obtained, and the luminance can be adjusted by changing the selection conditions of the input signal to the delay fA position that holds the signal for one horizontal scanning period. The delay amount of the signal and the color signal can be independently set in either one horizontal scanning period or two horizontal scanning periods, and the signal components having different delay amounts can be simultaneously obtained.

作  用 本発明は前述した構成により、時分割多重された映像信
号の一部分を大容量メモリで構成したラインメモリに反
復入力することにより小規模の回路構成で部分的に異な
る遅延量を有する映像信号を得ることができる。
According to the above-described configuration, the present invention repeatedly inputs a portion of a time-division multiplexed video signal to a line memory configured with a large-capacity memory, thereby generating a video signal having partially different delay amounts using a small-scale circuit configuration. can be obtained.

実施例 以下に本発明の実施例について図面を参照しながら説明
する。第1図は本発明における遅延装置の第1の実施例
を示したものである。
Examples Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of a delay device according to the present invention.

第1図においては、輝度信号と色信号とが水平走査期間
内に時分割多重されている映像信号が信号端子21から
入力され、マルチプレクサ22を介してF I F O
(First −In First−Out )メモリ
等の遅延素子を用いたラインメモリ23で1ライン遅延
される。1ライ/遅延された映像信号は分配回路24で
分配され後述するフリップフロツブ25と画素交換回路
26に供給される。
In FIG. 1, a video signal in which a luminance signal and a chrominance signal are time-division multiplexed within a horizontal scanning period is input from a signal terminal 21, and sent via a multiplexer 22 to an FIFO.
(First-In First-Out) The signal is delayed by one line in the line memory 23 using a delay element such as a memory. The one-line/delayed video signal is distributed by a distribution circuit 24 and supplied to a flip-flop 25 and a pixel exchange circuit 26, which will be described later.

ラインメモリ23と画素交換回路26では入力信号のサ
ンプリングレートの2倍の周波数のクロックレートを有
するクロック2で処理を行なう。
The line memory 23 and the pixel exchange circuit 26 perform processing using a clock 2 having a clock rate twice the sampling rate of the input signal.

また、後述するフリップフロップ25では入力信号のサ
ンプリングレートと同一の周波数を有するクロック1で
処理を行なっている。
Further, a flip-flop 25, which will be described later, performs processing using a clock 1 having the same frequency as the sampling rate of the input signal.

画素交換回路26では、ラインメモリ23で遅延された
映像信号の2画素を1組にして相互の位置を入れ替える
操作を行ない、前記マルチプレクサ22の入力信号が供
給される端子とは異なる方の端子に導かれる。
In the pixel exchange circuit 26, the two pixels of the video signal delayed by the line memory 23 are combined into a pair, and their positions are swapped. be guided.

制御回路27は第2図に具体的構成の一例を示すとおり
、輝度信号部分を論理”1“レベル、色信号部分を論理
″0”レベルとするような水平走査期間の輝度信号部分
と色信号部分とを区別するための制御信号であるY/C
信号と、入力信号が有するサンプリングレートと同周波
数のクロック1とを入力として双方の信号の論理積を求
めることにより入力映像信号の輝度信号部分の遅延量と
色信号部分の遅延量の制御を行なう信号を生成する。
As an example of a specific configuration is shown in FIG. 2, the control circuit 27 controls the luminance signal portion and the color signal during the horizontal scanning period such that the luminance signal portion is at the logic “1” level and the color signal portion is at the logic “0” level. Y/C, which is a control signal for distinguishing between
A signal and a clock 1 having the same frequency as the sampling rate of the input signal are input, and the logical product of both signals is calculated to control the delay amount of the luminance signal portion and the delay amount of the color signal portion of the input video signal. Generate a signal.

マルチプレクサ22では、曲の入力として画素交換回路
26からの出力信号が加えられ、制御回路27からの制
御信号によって双方が切り替えられるが、輝度信号部分
についてはそのまま、色信号部分については入力信号1
画素分の時間に人力信号と遅延された信号を1mにして
2画素に圧縮した信号がラインメモリ23に4かれる。
In the multiplexer 22, the output signal from the pixel exchange circuit 26 is added as the music input, and both are switched by the control signal from the control circuit 27, but the luminance signal portion remains unchanged, and the color signal portion is input to the input signal 1.
Four signals are stored in the line memory 23 by compressing the human input signal and the delayed signal into 1 m in time for a pixel and compressing the signal into two pixels.

より具体的には、Y/C信号が論理”1′ルベルを示す
輝度信号部分ておいては入力信号がクロック2のレート
で2回続けてラインメモリ23に導かれ、Y / C@
号が論理”O”レベルを示す色信号部分においては入力
信号1画素分の時間にサンプリングレートの半分に時間
圧縮された入力信号と画素交換回路から供給された信号
で1ライン遅延された信号とが多重されてラインメモリ
23に導かれることになる。
More specifically, in the luminance signal portion where the Y/C signal indicates a logic "1" level, the input signal is led to the line memory 23 twice in succession at the rate of clock 2, and the Y/C@
In the color signal part where the signal indicates the logic "O" level, the input signal is time-compressed to half the sampling rate in the time of one pixel of the input signal, and the signal is delayed by one line with the signal supplied from the pixel exchange circuit. are multiplexed and guided to the line memory 23.

フリップフロップ26はクロック1により、ラインメモ
リ23内をクロック2で処理された2画素で1組になっ
ている映像信号のうち1つおきに配置されている遅延量
の少なくない方の信号、即ち1ライン遅延の輝度信号と
2ライン遅延の色信号を選択し、所望の映像信号を出力
端子28より送り出している。
The flip-flop 26 uses the clock 1 to select the signal with the least amount of delay, which is placed every other video signal in the line memory 23 and is processed by the clock 2, and which is a set of two pixels. A luminance signal delayed by one line and a color signal delayed by two lines are selected, and a desired video signal is sent out from the output terminal 28.

次に第3図てより本発明における遅延装置の第2の実施
例を示す。第3図において第1図のものと同一物は同一
番号を付し、回路動作も同様であるので説明を省略する
Next, FIG. 3 shows a second embodiment of the delay device according to the present invention. In FIG. 3, the same parts as those in FIG. 1 are given the same numbers, and the circuit operations are also the same, so the explanation will be omitted.

第3図の制御回路37では、輝度信号部分を論理”1ル
ベル、色信号部分を論理”0パレペルとするような水平
走査期間の輝度信号部分と色信号部分とを区別するため
の制御信号であるY/C信号と、入力信号が有するサン
プリングレートと同周波数のクロック1と、それに加え
て、例えば次頁の表に示すような論理で輝度信号部分の
遅延量と色信号部分の遅延量を独立に1ラインあるいは
2ラインに設定するための2ビツトの制御信号を入力と
して、前記2ピア)の制御信号で論理演算されたY/C
信号とクロック1との論理積を求めることにより入力映
像信号の輝度信号成分と色信号成分の遅延量の制御を行
なう信号を生成している。
The control circuit 37 in FIG. 3 uses a control signal for distinguishing between the luminance signal part and the chrominance signal part in the horizontal scanning period, such that the luminance signal part is set to logic "1 level" and the color signal part is set to logic "0 level level". In addition to a certain Y/C signal and a clock 1 with the same frequency as the sampling rate of the input signal, calculate the delay amount of the luminance signal portion and the delay amount of the color signal portion using the logic shown in the table on the next page. Y/C which is logically operated using the control signals of the above two peers, with a 2-bit control signal for independently setting 1 line or 2 lines as input.
By calculating the logical product of the signal and clock 1, a signal for controlling the delay amount of the luminance signal component and color signal component of the input video signal is generated.

制御回路37の具体的構成の一例を第4図て示す。An example of a specific configuration of the control circuit 37 is shown in FIG.

これは、入力信号と制御信号のビット○との論理和を求
め、その出力と制御信号のビット1との排他的論理和を
求めたものを更にクロック1との論理積を求めて、その
結果を切り替え制御信号としてマルチプレクサ22に供
給する構成【てなっている。この制御信号は、”oo”
(並びはビット1、ビットoの順、以下同様)で輝度信
号を1ライン、色信号を2ラインの遅延、”01’”で
輝度信号、色信号とも2ラインの遅延、” 10 ”で
輝度信号を2ライン、色信号を1ラインの遅延、” 1
1 ”で輝度信号、色信号とも1ラインの遅延が行なわ
れるように本発明の遅延装置を制御している。
This is done by calculating the logical sum of the input signal and bit ○ of the control signal, calculating the exclusive logical sum of the output and bit 1 of the control signal, and then calculating the logical product of the result with clock 1. is supplied to the multiplexer 22 as a switching control signal. This control signal is “oo”
(The order is bit 1, bit o, and so on.) The luminance signal is delayed by 1 line and the chrominance signal is delayed by 2 lines. "01" is a delay of 2 lines for both the luminance signal and chrominance signal, and "10" is the luminance signal. 2 lines delay for signal, 1 line delay for color signal, ” 1
The delay device of the present invention is controlled so that both the luminance signal and the chrominance signal are delayed by one line at 1''.

なお、本発明の実施例はシフトレジスタ型のFIFOメ
モリを用いたラインメモリについて示したが、ランダム
アクセスメモリを用いたものも構成を変更することで可
能であり、フィールド遅延を行なうフィールドメモリに
ついても同様な効果が得られることはあきらかである。
Although the embodiments of the present invention have been described with respect to a line memory using a shift register type FIFO memory, it is also possible to use a random access memory by changing the configuration, and a field memory that performs field delay is also applicable. It is clear that similar effects can be obtained.

発明の効果 本発明による遅延装置は大容量のメモリを用い、映像信
号の一部をラインメモリに反復入力することによシ、映
像信号に含まれる輝度信号成分の遅延量と色信号成分の
遅延量とを独立に変化させて同時に得られることが可能
になり、その実用的効果は大きい。
Effects of the Invention The delay device according to the present invention uses a large-capacity memory and repeatedly inputs a part of the video signal to the line memory, thereby controlling the delay amount of the luminance signal component and the delay of the color signal component included in the video signal. It becomes possible to change the amount independently and obtain them simultaneously, which has a great practical effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例における遅延装置のブロ
ック図、第2図は第1図における制御回路の一具体的構
成図、第3図は本発明の第2の実施例における遅延装置
のブロック図、第4図は第3図における制御回路の一具
体的構成図、第5図は時分割多重信号の信号波形図、第
6図は時分割多重信号の色信号部分における走査の線順
次の様子を示した図、第7図は従来例における遅延装置
のブロック図である。 11.21・・・・・・入力端子、12,13.23・
・・・・・ラインメモリ、14.22・・・・・・マル
チプレクサ、15.28・・・・・・出力端子、24・
・・・・・分配回路、25・・・・・・フリップフロッ
プ、26・・・・・・画素交換回路、27.37・・・
・・・制御回路。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第3図 第4図 L         −−噌」
FIG. 1 is a block diagram of a delay device in a first embodiment of the present invention, FIG. 2 is a specific configuration diagram of a control circuit in FIG. 1, and FIG. 3 is a block diagram of a delay device in a second embodiment of the present invention. A block diagram of the device, FIG. 4 is a specific configuration diagram of the control circuit in FIG. 3, FIG. 5 is a signal waveform diagram of the time division multiplexed signal, and FIG. 6 is a diagram of scanning in the color signal portion of the time division multiplexed signal. FIG. 7, which is a diagram showing the state of line sequential operation, is a block diagram of a conventional delay device. 11.21... Input terminal, 12, 13.23.
... Line memory, 14.22 ... Multiplexer, 15.28 ... Output terminal, 24.
...Distribution circuit, 25...Flip-flop, 26...Pixel exchange circuit, 27.37...
...Control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 L ---

Claims (2)

【特許請求の範囲】[Claims] (1)輝度信号と色信号とが水平走査期間内で時分割多
重されて伝送されるカラーテレビジョン信号の処理装置
で、前記輝度信号と色信号の多重位置を示すY/C信号
で前記カラーテレビジョン信号の遅延を制御する遅延装
置であって、カラーテレビジョン信号をマルチプレクサ
を介して遅延させる遅延回路と、遅延回路を通過したテ
レビジョン信号を分配する分配回路と、前記分配回路の
一方の出力の2画素を1組にして相互に信号位置を交換
する画素交換回路と、画素交換回路の出力信号と前記カ
ラーテレビジョン信号とを切り替えて多重する前記マル
チプレクサと、マルチプレクサにより輝度信号部分と色
信号部分との切り替えを行なうために前記Y/C信号を
入力の1つとする制御回路とを備えることにより、前記
分配回路の他方の出力に1水平走査期間遅延された信号
成分と2水平走査期間遅延された信号成分とが得られる
ことを特徴とする遅延装置。
(1) A color television signal processing device in which a luminance signal and a chrominance signal are time-division multiplexed and transmitted within a horizontal scanning period, in which a Y/C signal indicating a multiplexing position of the luminance signal and chrominance signal is transmitted. A delay device for controlling the delay of a television signal, comprising: a delay circuit that delays a color television signal via a multiplexer; a distribution circuit that distributes the television signal that has passed through the delay circuit; and one of the distribution circuits. a pixel exchange circuit that pairs two output pixels and exchanges signal positions with each other; a multiplexer that switches and multiplexes the output signal of the pixel exchange circuit and the color television signal; and a control circuit which takes the Y/C signal as one of its inputs in order to switch between the signal component and the signal component, so that the signal component delayed by one horizontal scanning period and the signal component delayed by two horizontal scanning periods are provided at the other output of the distribution circuit. A delay device characterized in that a delayed signal component is obtained.
(2)Y/C信号を入力とする制御回路において前記Y
/C信号の極性を反転あるいは一定値にすることにより
カラーテレビジョン信号が含む輝度信号と色信号の遅延
時間を独立に制御できることを特徴とする特許請求の範
囲第1項記載の遅延装置。
(2) In a control circuit that receives a Y/C signal as input, the Y
2. The delay device according to claim 1, wherein the delay time of a luminance signal and a color signal included in a color television signal can be independently controlled by inverting or setting the polarity of the /C signal to a constant value.
JP61202224A 1986-08-28 1986-08-28 Delay device Expired - Lifetime JP2529216B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61202224A JP2529216B2 (en) 1986-08-28 1986-08-28 Delay device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61202224A JP2529216B2 (en) 1986-08-28 1986-08-28 Delay device

Publications (2)

Publication Number Publication Date
JPS6359196A true JPS6359196A (en) 1988-03-15
JP2529216B2 JP2529216B2 (en) 1996-08-28

Family

ID=16454018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61202224A Expired - Lifetime JP2529216B2 (en) 1986-08-28 1986-08-28 Delay device

Country Status (1)

Country Link
JP (1) JP2529216B2 (en)

Also Published As

Publication number Publication date
JP2529216B2 (en) 1996-08-28

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