JPS6276877A - Two dimensional interpolation digital filter - Google Patents

Abstract

PURPOSE:To extend the operational time, to attain the high integration, and to decrease power consumption by providing a change-over means to output the first and the second outputs alternately and to inverse the output order of the two outputs at every horizontal scanning line. CONSTITUTION:A selector 35 selects the output from the second delay circuit 36 and that from the first arithmetic circuit 32 in such an order. As a result, in an output terminal po, an information in which its center marked (x) is interpolated is outputted at the point of time F, by using rhomb-shaped lattice points (g), (f), (b), and (j), and an information in which its center (g) is interpolated by using pentagonal lattice points (g), (c), (k), (b), and (j), is outputted at the point of time G, and the delay of the filter is just 3T. On the other hand, when the second horizontal scanning signal has an even-number lines, o/e the inverse of signal is in H, and selectors 42 and 57 selects the lower side. In such a way, the addition and the subtraction can be executed at the speed half of a conventional one, also, an output which filter-delay is constant and is correctly interpolated can be obtained. As a result, a high-density packaging and low power consumption can be attained, and the degree of integration can be improved in an LSI processing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a two-dimensional interpolation digital filter that performs two-dimensional interpolation on a receiving side of a digital signal transmitted by subsampling image information.

[Technical background of the invention and its problems 3 As a method of band compression of image information, sub-Nyquist frequency sampling of image information at a frequency lower than the Nyquist frequency is used.
sampling is known. In sub-Nyquist sampling, since the image information of the points that should originally be transmitted is thinned out and transmitted, it is necessary to interpolate the information of the thinned out points on the receiving side. In this case, in order to obtain good image quality, it is desirable that the information on the pixel to be interpolated be interpolated using information on a plurality of adjacent points. With line interlaced image information, image information one field before is also required for interpolation.

From the subsampled image information, the center and -L bottom 3
To extract a line, in the case of non-interlaced image information, two
1 horizontal scan with line delay circuit 1.2 (1) - 1>111
The signal delayed by 111 seconds is output from the first output terminal po1, the signal delayed by 111 times is extracted from the second output terminal po2, and the signal delayed by 111 times is output from the third output terminal po3.
It is sufficient to extract the signal delayed by 11 periods. In addition, when uniform information is line interlaced, as shown in FIG. 5, the 1-field delay circuit 3 and the 1-line delay circuit 4 are connected in series, and the signal input from the second output terminal po2 is output as it is. A signal delayed by 1 field is taken out from the first output terminal po1, and sent to the J tt'+ output terminal po3 by 1 field → -11-1 period delay 1 no! Just cover it to extract this signal. In either case, the first
, a continuous horizontal scanning signal can be extracted in the order of the second and third output terminals. B (The one-field delay circuit 3 actually has a shorter delay time than one field by 1/2 line. For example, if one frame is 1125 lines, it is set to a 562-line delay.

The three lines of image information extracted in this way are interpolated by a two-dimensional interpolation digital filter on the receiving side. FIG. 6 is an example of a conventional three-line, three-tap two-dimensional interpolation digital filter.

The coefficients of each filter are vertically and horizontally symmetrical as shown in FIG. From the transmitting side, as shown in Figure 8, a, b, c
, . . . receive the signal sampled in a checkered pattern, input the (n-1)th line to the first input terminal pH, input the n-th line to the second input terminal p12, and input the n-1st line to the second input terminal p12. The signal of the (n+1)th line is input to ρi3. Then, O is interpolated by the selectors 11 and 12 at the position of the X mark of the signal of each line, and the signal is returned to the T period signal again. The 0/'e signal whose value is inverted between odd and even lines and the 2T period rectangular wave φ are input to the υ1 transitive OR circuit 13, and the output of this circuit 13 causes the above 1? 11.12.

Now, as an example, input terminal pt2. p+1, p+3
Let us consider the case where e, g, and b in FIG. 8 are respectively input. In the first half of the 2T period, the selector 11 selects 0, so that the output of the O11 delay path 13 is 0, and the output of the d11 delay path 14 is 0. Therefore, the output of the coefficient circuit 15 is kood, the output of the adder 16 is 0, the output of the coefficient circuit 17 is 01, and the output of the adder 18 is 00d.

On the other hand, the output of the adder 19 is b+g, and this is selected in the first half of the 2T period, so the output of the selector 12 is also b
+g. Then, the output of the delay circuit 20 is O, the output of the delay circuit 21 is a + f', and the output of the coefficient circuit 22 is O. Also, the output of the adder 23 is a + b +f
+ g, the output of adder 25 is 11 (a+b+f+o)
becomes. Therefore, the value finally obtained from the adder 26 is kll(a+b+f+cj)+kOOd.

Similarly, in the second half of the 2T cycle, e is set to selector 11.
, O11 is output to the ill delay circuit 13, 01 is output to the d1 selector 12, 01 is output to the delay circuit 20, and O is output to the delay circuit 21, so in the end, 10 (b) is output to the output terminal po.
01(d+e) is output to +g)+.

In such conventional digital filters, addition and multiplication must be performed within one hour. Particularly, when the sampling period T is short, such as in a high-definition television signal, a high-speed logic element, such as an ECL, must necessarily be used.

However, ECL generates a large amount of heat and requires a terminating resistor to be attached to each terminal, which prevents high-density packaging and has the problem of high power consumption. Also,
Even if it were to be made into an LSI, it would be necessary to use bipolar, which has a faster switching speed than 0MO8.
There was also the problem that the degree of integration could not be increased very much.

-〇- [Objective of the Invention] The present invention aims to provide a two-dimensional interpolation digital filter that can increase the allowable calculation time and thereby achieve higher integration and lower power consumption. There is.

(Summary of the Invention) The present invention provides a two-dimensional interpolation digital filter that performs two-dimensional interpolation and filtering on a digital image signal obtained by rib-sampling two-dimensional image information in a checkered pattern. Three consecutive horizontal scanning signals are extracted, and two calculation means perform parallel calculations based on these three horizontal scanning signals. These two calculation means each perform calculations in 2T cycles. By obtaining the output alternately every hour, the calculation time is essentially doubled compared to the conventional method.

Of these two calculation means, the first calculation means calculates the point to be interpolated and the five pixel points located diagonally above and below this point (
The second calculating means is to add information by multiplying the information (hereinafter referred to as "5-1 rank dried fish") by a coefficient, and the second calculation means is to add The information is multiplied by a coefficient and added.

Note that since the sampling points are reversed between the odd-numbered lines and the even-numbered lines, a circuit for alignment is required. In the present invention, the center scanning line and the scanning lines above and below it are shifted by two pixels between when the center horizontal scanning signal among the three horizontal scanning signals is an even numbered scanning line and when it is an odd numbered scanning line. A variable delay means (1) is provided, and the position is adjusted so that the calculation is performed correctly.Also, so that the delay of the filter is always constant, the output is set after the first calculation means or the second calculation means. A second variable delay means is provided for changing the timing by two kings.

〔Effect of the invention〕

According to the present invention, since calculations can be performed at 1/2 the rate of the output signal, there is no need to use high-speed logic elements such as ECL even with high-speed digital signals such as high-definition television signals, and high-density packaging is possible. Lower power consumption can be achieved. Furthermore, in LSI implementation, since it can be configured with 0MO8, the integration area can be increased.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

FIG. 1 is a diagram showing the configuration of a 3-line, 3-tap, two-dimensional interpolation digital filter according to this embodiment.

That is, among the three consecutive horizontal scanning signals extracted through the circuit shown in FIG. 4 or FIG.
l, second input terminal 1) i2. Each is input to the third input terminal pi3. These three horizontal scanning signals
As shown in FIG. 3 and FIG. 3, the signal has a cycle of <2T, and its phase is the same between even and odd lines.

Among these horizontal scanning signals, the first and second horizontal scanning signals are added by an adder 31 and input to a first arithmetic circuit 32 and a second arithmetic circuit 33. Further, the second horizontal scanning signal is passed through the first variable delay circuit 34,
The above first and second signals are input to the arithmetic circuits 32 and 33. The first output from the first arithmetic circuit 32 is given to one input terminal of the selector 35, and the second output from the second arithmetic circuit 33 is
It is applied to the other input terminal of the selector 35 via the second variable delay circuit 36. The selector 35 alternately selects these two outputs at T cycles and outputs the two signals to the output terminal po.

The first variable delay circuit 34 is for making the signal on the center line different by exactly 2T time between the odd line and the even line. The output of the signal delayed by 2T time is inverted between the even and odd lines.
The selector 42 operates to select according to the /e signal.

The first arithmetic circuit 32 is a circuit that multiplies the five-ranked dried fish by a predetermined coefficient and adds the result.The output of the first variable delay circuit 34 is delayed by 2T time in the delay circuit 43, and the output in the coefficient circuit 44 is After being multiplied by a coefficient koO, it is applied to one input of the adder 45, and the crimping output from the adder 31 and a signal obtained by delaying this output by two times in the delay circuit 46 are sent to the adder 47. By adding them together, multiplying them by a predetermined coefficient kll in the coefficient circuit 48, delaying them by two times in the delay circuit 49, and applying them to the other input of the adder 45, τ is obtained from the adder 45. The interpolation and filtering output of the pixel at the center of the fish is obtained.

On the other hand, the second arithmetic circuit 33 is a circuit that multiplies the rhombic grid pattern by a predetermined coefficient and adds the result.
An adder 51 adds the output of 4 and a signal obtained by delaying this output by two times in a delay circuit 50, and multiplies the output by a predetermined coefficient k (11) in a coefficient circuit 52. At the same time, the addition output from the adder 31 is delayed by the circuit!
: After delaying by two times at step 54 and multiplying by a coefficient klo at coefficient circuit 55, the adder 53 outputs interpolation and filtering of the pixel at the center of the rhombic grid by feeding it to the other input of the adder 53. This is what you get.

The second variable delay circuit 36 is a circuit for making the delay time of the entire filter constant, and outputs a signal obtained by delaying the output from the second arithmetic circuit 33 and this output by two times in the delay circuit 56. The selector 57 operates to select the outputs according to the o/e signal which inverts the output between even and odd lines.

The selector 35 alternately selects the output from the first arithmetic circuit 32 and the output from the second variable delay circuit 36 in T cycles, but one non-pull point is exactly reversed between the even and odd lines. do. Therefore, the signal φ with 21 periods
and the stone/e signal are applied to the exclusive OR circuit 58 to invert the signal φ between the even and odd lines, and this signal is applied to the selector 35 as a switching signal.

In a digital filter with such a configuration, now,
As shown in FIG. 2, when the second horizontal scanning signal is an odd line, the following operation is performed.

The o/e signal becomes the ``L I+ level,'' and the selector 42.
57, the upper input is selected. Input terminal pil,
Assuming that d, h, and l are currently input to pi2 and pi3, respectively, the output of the selector 42 is h1, and the output of the adder 31 is d+. Therefore, the output of the delay circuit 43 is o1, the output of the coefficient circuit 44 is +<oog, the output of the delay circuit 46 is c i-k, and the output of the adder 47 is c
+d+ becomes +1, and the output of the coefficient circuit 48 becomes kll (c+d+1). Therefore, from the first arithmetic circuit,
At time point G, an output of koOg + kll (b + c + j + k) is output.

On the other hand, the output of the delay circuit 50 is 01, and the output of the adder 51 is g
Since the output of the coefficient circuit 52 is 01 (0+h), the output of the delay circuit 5/I is c0k, and the output of the coefficient circuit 55 is kin (C+k), the second
The output of the arithmetic circuit 33 is kol(0+h) tenths (c
10k).

Since the output of the second arithmetic circuit 33 is delayed by two stages by the variable delay circuit 36 of i#I2, the selector 57 outputs an output of kol (f + o) ten times (b + j) at the time of F. Ru.

The selector 35 selects the output of the second delay circuit 36 and the output of the first arithmetic circuit 32 in this order. As a result, the output terminal po has a diamond-shaped grid. , f, b.

, j, and the information obtained by interpolating the X mark at the center is output at point F, and the number of dried fish 0. c, ni, b.

, j, and the center g is interpolated and output at the time point G. In other words, the delay of the filter is exactly 3T! l
:Become.

On the other hand, as shown in FIG. 3, when the second horizontal scanning signal is an even line, the δ/e signal becomes "H11", and the selectors 42 and 57 select the lower side.
d, h, l to input terminals phi, po2, po3
If we consider the case where koof + k11 (
+b+j) is output to c+, and the selector 57 outputs
At the time of H, 01(o+f)+10(c+k) is output. The selector 35 outputs the output of the first arithmetic circuit 32,
The signals are output in the order of the output of the second variable delay circuit 36. As a result, the output terminal pO has five first rank dried fish f, c, b,
A signal obtained by interpolating the point f using j is output at time G, = 14- A signal obtained by interpolating the X mark at the center of A using diamond g, f, c, and k. is output at the time of H, so the delay of the filter is also 31- in this case.

In this way, according to this embodiment, tightening and division can be performed using the conventional method.
A speed of 7'2 is sufficient, the filter delay is constant, and a correctly interpolated output can be obtained.

Note that the present invention can be modified in various ways without departing from the gist thereof.

For example, the first variable delay circuit 34 may be provided after the adder 31 and the second variable delay circuit 36 may be provided after the first arithmetic circuit 32.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a two-dimensional interpolation digital filter according to an embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams for explaining the operation of the digital filter. Figure 4 and L-I"5
The figure is a block diagram showing a circuit that extracts three consecutive horizontal scanning signals, Figure 6 is a block diagram showing a conventional two-dimensional interpolation digital filter, and Figure 7 is a two-dimensional interpolation filter coefficient and pixel. FIG. 8 is a diagram showing subsampled pixel information. 11.12.35, 42.57...Selector, 32.
...First arithmetic circuit, 33...Second arithmetic circuit, 34
. . . first variable delay circuit, 36 . . . second variable delay circuit. Applicant's agent Patent attorney Takehiko Suzue kn k+n kll 1jj Ko v h Y r
------ko+ koo ko+ kn k+o kn Figure 7 II-I CL A LI
AL------n X d X e X
----n+1 f x g x
h---Figure 8

Claims (1)

[Claims] In a two-dimensional interpolation digital filter that performs two-dimensional interpolation and filtering of a digital image signal obtained by subsampling two-dimensional image information in a checkered pattern,
means for extracting three consecutive horizontal scanning signals from the digital image signal; a first variable delay means for shifting a horizontal scanning line and the horizontal scanning lines above and below it by two pixels; a point to be interpolated from each pixel signal of the three horizontal scanning signals; and a point diagonally above and below this point. a first arithmetic means for extracting points existing in , multiplying and adding each by a coefficient to obtain a first output; a second calculation means for extracting points, multiplying and adding coefficients to each point to obtain a second output; and a second calculation means for making the delay amount between the first output and the second output constant.
and a switching means for alternately outputting the first output and the second output and reversing the output order of the two outputs every horizontal scanning line. Two-dimensional interpolation digital filter.