JP2529216B2 - Delay device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a luminance signal and a chrominance signal which are time-division multiplexed within a horizontal scanning period, and a wideband signal and a narrowband signal are transmitted in a line-sequential form for the chrominance signal. The present invention relates to a color television signal processing device.

2. Description of the Related Art In digital signal processing of television signals, 2
A line memory that performs a time delay corresponding to a horizontal scanning period is used for dimension processing. Further, for three-dimensional processing, a field memory or the like that delays a signal during a vertical scanning period is also used.

As one method of transmitting a television signal, a luminance signal and a chrominance signal are time-division multiplexed as shown in FIG. 5, and a wide band signal and a narrow band signal as shown in FIG. An analog component transmission method of transmitting in a line-sequential form arranged every other time is conceivable. To process such a signal, for example, a luminance signal delayed by one line and a color signal delayed by two lines are used. In general, a method is often used in which line memories for delaying signals for one line are cascaded in two stages, a color signal part is extracted from the final output, and a luminance signal part is extracted from a tap in the middle. Has been.

A conventional example related to the present invention will be described below with reference to the drawings.

FIG. 7 shows one line of the luminance signal portion of the television signal transmitted by time-division multiplexing the luminance signal and the color signal,
It shows an example of a delay device for delaying the color signal portion by two lines.

The video signal input from signal terminal 11 is FIFO (First-I
n First-Out) 1 line is delayed by the first line memory 12 using a delay element such as a second line memory 13
Is delayed by one line. The output of the first line memory 12 becomes the input of the second line memory 13 and simultaneously becomes one input of the multiplexer 14. The output of the second line memory 13 becomes the other input of the multiplexer 14,
The output of the first line memory 12 is the period during which the luminance signal is transmitted by the Y / C signal which is a control signal for distinguishing the luminance signal portion and the color signal portion in the horizontal scanning period by the multiplexer 14. The luminance signal delayed by one line is selected and sent to the signal output terminal 15 by selecting the color signal delayed by two lines which is the output of the second line memory 13 during the period in which the color signal is transmitted.

Problems to be Solved by the Invention In the conventional device, in the above-described configuration, when a luminance signal delayed by one line and a color signal delayed by two lines are simultaneously output, the device has a capacity for one line. Since the line memory is cascaded in two stages and the color signal part is extracted from the final output and the luminance signal part is extracted from the tap in the middle, the number of line memories equal to the maximum delay amount of the video signal is required. However, there is a problem that the circuit scale must be increased.

In view of this point, the present invention uses one large-capacity memory having a capacity of two lines or more to independently change the delay amount of the luminance signal component and the delay amount of the chrominance signal component included in the video signal. It is an object of the present invention to provide a delay device obtained by the above.

According to the present invention, a part of a video signal that has passed through a delay circuit that delays a signal for one horizontal scanning period is made to pass through the delay circuit again. A signal component delayed by the scanning period and a signal component delayed by two horizontal scanning periods are obtained at the same time, and the luminance signal is changed by changing the selection condition of the input signal to the delay device holding the one horizontal scanning period signal. And the delay amount of the color signal can be independently set to either one horizontal scanning period or two horizontal scanning periods, and a combination of signal components having different delay amounts can be obtained at the same time.

With the above-described configuration, the present invention repeatedly inputs a part of the time-division-multiplexed video signal to the line memory configured by the large-capacity memory to generate a video signal having a partially different delay amount with a small-scale circuit configuration. Obtainable.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the delay device according to the present invention, and FIG. 8 shows a desired output signal from a video signal input from the signal input terminal 21 in the first embodiment. 6 is a signal waveform diagram for explaining the operation of FIG. Note that, in FIG. 8, for convenience, one horizontal scanning period is illustrated as a video signal including four color signal pixels and six luminance signal pixels.

In FIG. 1, a luminance signal and a color signal are time-division multiplexed within a horizontal scanning period (hereinafter referred to as a line),
The video signal shown in FIG. 8A is input from the signal input terminal 21, and the input video signal and the output signal of the pixel exchange circuit 26 described later are selected by the multiplexer 22 according to the control of the output signal of the control circuit 27, The signal is shaped into the signal shown in FIG. 8 [E] and delayed by one line in the line memory 23 using a delay element such as a FIFO (First-In First Out) memory. The video signal delayed by one line obtained as the output of the line memory 23 has a signal waveform shown in FIG.
It is distributed at 24 and supplied to a flip-flop 25 and a pixel exchange circuit 26 described later.

The line memory 23 and the pixel exchange circuit 26 perform processing with the clock 2 shown in FIG. 8F, which has a clock rate of a frequency twice the sampling rate of the input video signal. The flip-flop 25, which will be described later, performs processing with the clock 1 having the same frequency as the sampling rate of the input video signal shown in FIG. 8C.

In the pixel exchange circuit 26, the video signal shown in FIG.
A process of changing the positions of the pixels into one set is performed. In the first embodiment, the input signal to the pixel exchange circuit 26 is the output signal of the delay circuit 24 shown in FIG. 8 [G]. In the chrominance signal portion, the input signal and the signal delayed by one line by the delay circuit 24 are switched by the multiplexer 22, so that they are alternately inserted in the cycle of the clock 2, but the luminance signal is shown in FIG. 8 [D]. Since it is controlled by the switching control signal indicated by, the same input signal is lined up twice in a cycle of the clock 2. Therefore, as is apparent from FIG. 8 [H], the color signal portion shows the pixel exchange for every two pixels, but the luminance signal portion has the same pixel exchange as the color signal. An output signal that is apparently unchanged is obtained.

The signal subjected to the pixel exchange processing has a signal waveform as shown in FIG. 8 [H]. The signal subjected to the pixel exchange processing is guided to a terminal different from the terminal to which the video signal input from the signal input terminal 21 of the multiplexer 22 is supplied.

The control circuit 27 uses a logic circuit as shown in FIG. 2 as an example of its concrete configuration to control the luminance signal portion at a logical "0" level and the color signal portion at a logical "1" level. A Y / C signal as shown in FIG. 8 [B] which is a control signal for distinguishing the luminance signal part and the color signal part,
A signal for controlling the delay amount of the luminance signal portion and the delay amount of the color signal portion of the input video signal is generated by obtaining the logical product of both from the clock 1. The control signal generated by the control circuit 27 has a signal waveform as shown in FIG.

One of the inputs of the multiplexer 22 is the signal input terminal 21
The video signal input from the pixel exchange circuit 26 is applied to the other video signal, and the output signal from the pixel exchange circuit 26 is applied to the other, and the signals selected by the control signal output from the control circuit 27 are combined. In the control method of this embodiment, the video signal input from the signal input terminal 21 is selected as it is for the luminance signal portion, the input video signal for the color signal portion and the line memory 23 are delayed, and the pixel exchange circuit 26 The signals whose positions have been exchanged are paired and a signal compressed in the time corresponding to one pixel of the input video signal is guided to the line memory 23 again. More specifically, a portion in which the control signal output from the control circuit 27 is at the logical "1" level is an image input from the signal input terminal 21 at a portion in which the output of the pixel exchange circuit 26 is at the logical "0" level. The signal is selected by multiplexer 22. Therefore, in the case of the present embodiment, in the luminance signal portion in which the Y / C signal indicates the logical "0" level, the input video signal is continuously guided twice at the rate of the clock 2 to the line memory 23, and the Y / C signal is output. In the color signal portion indicating the logic "1" level, the video signal input from the signal input terminal 21 and the signal supplied from the pixel exchange circuit 26 are set to 1 for the input video signal in the time of one pixel of the input video signal. The line-delayed signal is combined and guided to the line memory 23 again.

The flip-flop 25 is a set of two pixels processed by the clock 2 in the line memory 23, and the flip-flop 25 corresponds to a video signal as shown in FIG. 8 [H].
The state at the rising edge of the inverted signal of the clock 1 indicated by is held and is led to the output terminal 28 as a signal having a signal waveform as shown in FIG.

By the signal processing described above, in the present embodiment, the luminance signal with 1-line delay and the color signal with 2-line delay can be simultaneously obtained from the output terminal 28.

The flip-flop output signal shown in FIG. 8 [J] is delayed by one pixel from the desired delay amount for both the luminance signal and the chrominance signal with respect to the input video signal. This is because it is expressed in order to explain in detail the manner in which it is held. Actually, the delay amount of the entire system is adjusted in consideration of the fact that the flip-flop 25 delays by one pixel and a half, and An output signal with a desired delay amount can be obtained.

Next, FIG. 3 shows a second embodiment of the delay device according to the present invention. In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals, and the circuit operation is also the same, so that the description will be omitted.

The control circuit 37 shown in FIG. 3 is a control for distinguishing between the luminance signal portion and the color signal portion in the horizontal scanning period in which the luminance signal portion is set to the logical "1" level and the color signal portion is set to the logical "1" level. In addition to the Y / C signal which is a signal, the clock 1 having the same frequency as the sampling rate of the input signal,
For example, with the logic as shown in the table on the next page, a 2-bit control signal for independently setting the delay amount of the luminance signal portion and the delay amount of the chrominance signal portion to 1 line or 2 lines is input, and the 2-bit control signal is input. A signal for controlling the delay amount of the luminance signal component and the chrominance signal component of the input video signal is generated by obtaining the logical product of the Y / C signal logically operated by the control signal and the clock 1.

FIG. 4 shows an example of a specific configuration of the control circuit 37. This calculates the logical sum of the input signal and bit 0 of the control signal,
The exclusive OR of the output and bit 1 of the control signal is further calculated with the clock 1 and the result is supplied to the multiplexer 22 as a switching control signal. This control signal is bit 1, bit 0
The following four combinations can be considered for the value of.

When the control signal is bit 1 = "0", bit 0 = "0",
The output signal waveform of the control circuit 27 configured as shown in FIG. 4 is as in case 1 [A] shown in FIG. 9, and when the signal value is “0”, the image input from the signal input terminal 21 When the signal is “1”, the signal input via the line memory 23, the distribution circuit 24, and the pixel exchange circuit 26 is multiplexed by the multiplexer 22.
The delay device of the present invention is controlled so that a signal obtained by delaying the luminance signal by one line and the color signal by two lines is obtained at the output terminal 28. This is similar to the logic described in the first embodiment.

Further, similarly to the above, when the control signal is bit 1 = “0” and bit 0 = “1”, the output signal waveform of the control circuit 27 is as in case 2 [B] shown in FIG. The color signals are controlled to be delayed by two lines. Further, the output signal waveform of the control circuit 27 when the control signal is bit 1 = “1” and bit 0 = “0” is as shown in case 3 [C] of FIG. It is controlled to delay by one line, and the control signal is bit 1 = "1", bit 0 =
The output signal waveform of the control circuit 27 in the case of "1" is as shown in case 4 [D] of FIG. 9, and the delay device of the present invention is controlled so that both the luminance signal and the chrominance signal are delayed by one line.

Although the embodiment of the present invention shows the line memory using the shift register type FIFO memory, the one using the random access memory is also possible by changing the configuration, and the field memory for performing the field delay is also applicable. Clearly, the same effect can be obtained.

The delay device according to the present invention uses a large-capacity memory, and by repetitively inputting a part of the video signal into the line memory,
The delay amount of the luminance signal component and the delay amount of the chrominance signal component included in the video signal can be independently changed and simultaneously obtained, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a delay device in the first embodiment of the present invention, FIG. 2 is a concrete configuration diagram of a control circuit in FIG. 1, and FIG. 3 is a delay in the second embodiment of the present invention. FIG. 4 is a block diagram of the apparatus, FIG. 4 is a specific configuration diagram of the control circuit in FIG. 3, FIG. 5 is a signal waveform diagram of a time division multiplex signal, and FIG. 6 is a scan of a color signal portion of the time division multiplex signal. FIG. 7 is a block diagram of a delay device in a conventional example, FIG. 8 is a signal waveform diagram for explaining the operation of the first embodiment, and FIG. 9 is an operation of the second embodiment. It is an explanatory signal waveform diagram. 11,21 …… Input terminal, 12,13,23 …… Line memory, 14,2
2 ... Multiplexer, 15, 28 ... Output terminal, 24 ... Distribution circuit, 25 ... Flip-flop, 26 ... Pixel exchange circuit,
27,37 …… Control circuit.

Claims (2)

(57) [Claims] 1. A processing apparatus for a color television signal, wherein a luminance signal and a chrominance signal are time-division multiplexed within a horizontal scanning period, and a wideband chrominance signal and a narrowband signal are transmitted in a line-sequential form. Is a delay device for controlling the amount of delay between the luminance signal and the color signal by a Y / C signal that represents the luminance signal portion and the chrominance signal portion in the logical level, and delays the output signal of the multiplexer by one horizontal scanning period. Circuit, a distribution circuit for dividing the output signal of the delay circuit into two, a pixel exchange circuit for exchanging the signal positions of two adjacent output pixels of the distribution circuit as one set, and an output signal of the pixel exchange circuit And a control signal for controlling the multiplexer, the multiplexer selecting the delayed video signal which is the input signal and the color television video signal which is the input signal by switching by a control signal. Is provided from the Y / C signal and a clock signal to obtain a luminance signal delayed by one horizontal scanning period and a color signal delayed by two horizontal scanning periods at the other output of the distribution circuit. A delay device characterized by the above. 2. A color television set in which a Y / C signal is used as at least an input signal to generate a control signal for selecting an output signal of a multiplexer, by inverting or setting a constant value of the polarity of the Y / C signal. The luminance signal and the chrominance signal included in the John signal are independently set in one horizontal scanning period or two.
The delay device according to claim 1, wherein the delay device generates a control signal for delaying the horizontal scanning period.