JPS63250210A - Generator for pseudo-random noise code - Google Patents

Abstract

PURPOSE:To simplify a cascade connecting by utilizing an AND gate and an exclusive OR (EOR) gate, setting a suitable value and attaining a feedback from the flip flop of a shift register last step to the flip flop of a shift register first step. CONSTITUTION:When the setting method of data, which set a feedbacking condition by changing the positions of AND gate and EOR gate necessary at the time of cascade connecting, is changed, the data are one-bit-shifted and read. To feedbacking condition setting data to a shift register first step, namely to the DATO of the IC of the first step, certainly 'high' level is set, the input terminal (FB)I of a first step is fixed to a 'low' level and with the AND gate (ANDc) and the EOR gate (Ec), the output of a shift register last step can be feedback to the input of the shift register first step. Thus, an external connec tion is eliminated and the cascade connecting can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a pseudorandom noise code generator for digital data.

B0 Summary of the Invention In the feedback path from the final stage output of the shift register (feedback signal output) to the input of each stage of the shift register (feedback signal input), feedback signal output to and from other code generators is performed. An input/output terminal is provided that also serves as a feedback signal input, and the feedback signal output is a 3-state output.When in the enable state, it is possible to output the feedback signal to the outside and input the feedback signal to the inside.When in the high impedance state, the feedback signal is output in three states. , a pseudorandom noise code generator having a feedback circuit that functions exclusively for external feedback signal input.

When connected in cascade, an AND gate and an exclusive OR (hereinafter referred to as (abbreviated as EOR) gate.

Provided at the input section of the first stage flip-flop, this AN
By using the D gate and the EOR gate and setting appropriate values, it becomes possible to feed back from the flip-flop in the last stage of the shift register to the flip-flop in the first stage of the shift register inside the code generator.

C6 As a pseudo-random noise code generator that can set conventional technology codes and is suitable for IC implementation, for example, patent application No. 61-1630
There is one described in No. 88 and shown in FIG. In FIG. 5, SR, to SR.

is a flip-flop that constitutes a shift register, E 1
~E is an EOR gate, and G and ~Gl are steering gates for giving initial values to the flip-flops.

In the code generator shown in FIG. 5, the following (i
) to (iii) need to be provided externally.

(i) Initial value of flip-flop (n) Feedback state (iti) Number of stages of shift register
The period of the code can be controlled by the data of .it).

FIG. 6 shows the basic configuration of a pseudo-random noise code generator using a modular shift register.
A H-1 corresponds to the data in (ii) above, and when it is at the "r high" level, there is feedback from the shift register final stage SR, and when it is at the "low" level, there is no feedback. Furthermore, the period of the code to be output is determined by the number of stages N of the shift register, and in order to obtain a long-period code, N must be increased. (For example, the period of an m-series code is 2N-1.) In the code generator of FIG. 5, the final stage of the shift register is determined by the multiplexer based on the data (■) above (in the case of K≦n).

By the way, the feature of the code generator shown in Figure 5 is that even when integrated into an IC, multiple units can be connected in cascade.

The desired long-period code can be easily obtained ( N
> n). FIG. 7(a) shows a connection method when the code generator of FIG. 1 is used alone, and FIG. 7(b) shows a connection method when the code generator of FIG. 1 is used in cascade connection.

In the code generator of FIG. 5, the CAS terminal is connected to each I
C shift register nth stage output.

The FBI terminal is the input terminal to the first stage. Also.

The FBO terminal is a feedback signal input terminal to each stage of the shift register of each IC, and the FB2 terminal is the output terminal of the multiplexer, that is, the output terminal of the final stage of the shift register specified by the data in the above (leg) (hereinafter referred to as the feedback signal output terminal). ).

Therefore, by connecting the CAS terminal to the FBI terminal of the next IC, the number of stages of the shift register can be increased as necessary. Also, the FB2 terminal is a 3-state output.

If all terminals other than the FB2 terminal of the final stage IC are set to high impedance state, net3 in Figure 7(b)
The output signal from the final stage of the shift register is obtained. If this is connected to the FBO terminal of each IC, the configuration shown in FIG. 6 will be obtained, and a long period code can be output.

D0 Problems to be Solved by the Invention However, since the code generator shown in FIG. 5 enables cascade connection, even when used alone, the
As shown in Figure (a), there is a drawback that external wiring is required.

An object of the present invention is to provide a pseudo-connection system that eliminates the need for external connection of cascade connection terminals when using an IC alone, simplifies the cascade connection method, and reduces the number of pins. An object of the present invention is to provide a random noise code generator.

Means for Solving Problem E1 In order to achieve the above object, the present invention provides one of a first latch means for outputting to a steering gate and setting an initial value of a flip-flop, and an exclusive OR gate. A first AN that outputs to the input of and controls the EOR calculation.
A D gate, second and fourth latch means for outputting to the first AND gate and controlling the feedback state, and the first AND gate, exclusive OR gate, steering gate, and flip-flop are constituent units. a modular shift register configured by connecting a plurality of flip-flops in cascade; a multiplexer to which the output of each flip-flop is input; third and fifth latch means for controlling the multiplexer; Two signals are input: a latch enable pulse for latching the initial state, feedback state, and final stage selection state to the first, second, and third latch means, respectively, and a chip select of the pseudorandom noise code generator. A second AND gate and the output of the second AND gate are used as control signals, and in response to two selection signals, the first, second and third latch means are selected, and time division is performed from the data line. and a demultiplexer circuit for inputting data to each of the latch means, further comprising a feedback circuit for feeding back the output of the multiplexer to each component of the modular shift register. The gist is:

Since the positions of the AND gate and the EOR gate, which are required for F0 action cascade connection, have been changed, it is also necessary to change the method of setting data for setting the feedback state. In the conventional method, data for setting the feedback state is read as shown in FIG. 2(a), but in the method of the present invention, the data is shifted by one bit and read as shown in FIG. 2(b). Figure 2 (
a) shows data for setting the feedback state in the conventional method;
b) shows feedback state setting data of the present invention. AI is data for setting the feedback state to the i+1th stage of the modular shift register, and a "high" level indicates feedback, and a "low" level indicates no feedback. H indicates "high" level, and X indicates marriage regardless.

In addition, in the method of the present invention, the feedback state setting data to the first stage of the shift register, that is, DATO of the first stage IC, is always set to the "r high" level, and the FBI terminal is fixed to the "low" level, and the ANDc, The EC allows the output of the final stage of the shift register to be fed back to the input of the first stage of the shift register.

G. EXAMPLES The present invention will be explained in more detail below using examples with reference to the drawings, but these are merely illustrative and various modifications and improvements can be made without going beyond the scope of the present invention. Of course it is possible.

FIG. 1 is a block diagram showing the configuration of a pseudo-random noise code generator according to the present invention, and FIG. 3 is an external connection diagram when the pseudo-random noise code generator shown in FIG. 1 is used.

The FBI terminal in Figure 1 corresponds to the conventional FBI terminal, and the FBO terminal is the same as the conventional FBO terminal.
This terminal also serves as the FB2 terminal.

The code generator of the present invention shown in FIG. 1 has the following two features.

(1) By connecting and merging the feedback signal output terminal and the feedback signal input terminal within the same code generator, it is possible to directly feed back the signal within the code generator, and the number of pins is reduced. Further, for cascade connection, the feedback signal output section is made into a 3-state output so that the feedback signal output and the feedback signal input can be electrically separated. That is, in a cascade connection, the feedback signal outputs of all but the final stage code generator can be brought into a high impedance state and used as terminals exclusively for feedback signal input.

(2) When code generators using modular shift registers are connected in cascade, an EOR gate and It is necessary to insert an AND gate to specify the presence or absence of feedback. In the conventional system, these were installed at the output section of the n-th stage flip-flop to form a code generator (E, , AND, ) in Fig. 5, but in the system of the present invention, these were installed at the input section of the first stage. The code generator shown in FIG. 4 (EC, ANDc) constitutes a code generator.

Next, a connection method for constructing the modular shift register shown in FIG. 6 using the code generator of the present invention will be explained.

To configure a modular shift register, the following two conditions must be met.

(i) The output of the flip-flop in the final stage of the shift register is input to the feedback signal input of each stage of the shift register, and (...) The output of the flip-flop in the final stage of the shift register is input to the flip-flop in the first stage of the shift register. be entered in the input.

a. When used alone According to characteristic (1), condition (i) is satisfied if the feedback signal output is enabled. Also, by utilizing the property that when one input to the EOR gate is fixed at a "low" level, the state of the other input is output as is, feedback is provided by ANDc according to feature (2). Condition (it) can be satisfied by specifying and fixing the input on the FBI side of the EC to a "low" level. Figure 4 (a
) shows the feedback method, and (b) shows the equivalent circuit. That is, when used alone, there is no need to externally connect the cascade connection terminals.

b. When used in a cascade connection, according to feature (1), only the feedback signal output section of the code generator in the final stage of the cascade connection is enabled, and all the feedback signal output sections of the other code generators are set to high impedance. If these are all connected, the feedback signal from the code generator at the final stage will be input to all code generators, so condition (i) is satisfied. Further, condition (ii) can be satisfied if the ANDc gate and EC gate of the code generator at the first stage of the cascade connection are set in the same way as when used alone.

FIG. 3(a) shows an external wiring method when the pseudorandom noise code generator of the present invention is used alone, and FIG. 3(b) shows an external wiring method when used in cascade connection.

FIG. 4(a) shows a method of feeding back signals from the last stage of the shift register to the first stage of the pseudorandom noise code generator according to the present invention, and FIG. 4(b) shows its equivalent circuit.

As explained in detail about the H0 invention, according to the present invention, when the code generator is used alone, there is no need for external wiring, a simple cascade connection method can be realized, and the number of pins is reduced. can get.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a pseudo-random noise code generator according to the present invention, FIG. 2 is a diagram showing feedback state setting data when m code generators are connected in cascade, and FIG. 4 is a diagram showing the method of feeding back signals from the last stage of the shift register to the first stage of the pseudo random noise code generator of the present invention, and FIG. 5 is an external connection diagram when using the pseudo random noise code generator shown in the figure. A block diagram of a conventional pseudo-random t1 noise code generator, Fig. 6 is a basic configuration diagram of a pseudo-random noise code generator using a modular shift register, and Fig. 7 is a diagram of the pseudo-random noise code generator when using the pseudo-random noise code generator of Fig. 5. It is an external connection diagram. PNG (a) (b) Fig. 3 (a) (b) Fig. 4 1 Symbol Y Zaigui (N 孜襦亥) Jiang Shidan Fig. 6 NG PNGl PNG2 --- PN
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Claims (1)

[Claims] (a) A first latch means that outputs to the steering gate and sets the initial value of the flip-flop; (b) A first latch means that outputs to one input of the exclusive OR gate and sets the initial value of the flip-flop;
a first AND gate that controls the R operation; (c) second and fourth latch means that output to the first AND gate and control the feedback state; (d) the first AND gate, exclusive; disjunction gate,
a modular shift register configured by connecting a plurality of steering gates and flip-flops in cascade as structural units; (e) a multiplexer to which the outputs of each of the flip-flops are input; (f) a third controller that controls the multiplexer; and a fifth latch means, (g) a latch enable pulse and a pseudorandom for latching the initial state, feedback state, and final stage selection state of each flip-flop to the first, second, and third latch means, respectively. a second AND gate receiving the two chip select signals of the noise code generator as input; and (h) using the output of the second AND gate as a control signal;
In response to the two selection signals, the first, second and third
in a pseudo-random noise code generator including a demultiplexer circuit for selecting the latch means of and inputting data from the data line to each latch means in a time-division manner, further (i) shifting the output of the multiplexer in the above modular type; A pseudo-random noise code generator comprising a feedback circuit that feeds back to each constituent unit of a register.