JPS60176322A - M sequence code generator - Google Patents

Abstract

PURPOSE:To simplify the constitution by setting a feedback input part to a multistage shift register, in a code fetching part, and fetching a desired code length by only a feedback value set value to the multistage shift register. CONSTITUTION:A code generating part 1 is constituted by combining a multistage shift register 2 formed by coupling successively plural flip-flops 21-27, and a feedback logical circuit 3 for feeding back the logical coupling of an output of its each stage to the first stage flip-flop 21. Said feedback logical circuit 3 is constituted of gate circuits 31-37 for inputting an output of each stage of the shift register 2, and exclusive OR circuits 41-46, and as for said gate circuits 31-37, its opening and closing state is set by a feedback value setting part 8. The feedback value setting part 8 sets the contents of data buses D0-D6 to a latching circuit 81 by a feedback tap signal I4, and determines the opening and closing state of the gate circuits 31-37 based on the contents of this latch data. These operations are controlled by a main control part 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a code generator applied to a common communication system such as spread spectrum communication. The present invention relates to an M-sequence code generator used to generate the longest code among code sequences (hereinafter referred to as "M-sequence number 1").

<Background of the Invention> As shown in FIG. 3, conventional code generators of this type include a code generation section 1 consisting of a combination of a multi-stage shift register and a feedback logic circuit, a clock supply section 6, an initial value setting section 7, and a feedback logic circuit. It is constructed by adding a value setting section 8 and the like, and extracts an M-sequence code having a code length corresponding to the number of stages of the shift register from the final output terminal of the multi-stage shift register. Incidentally, in recent years, in order to promote encryption in communication systems, there has been a demand for a system that can: 1) dynamically switch the code length of the 1j code; In order to meet such demands, conventionally, a code length specifying section 10 for specifying the code length of the code to be extracted, and an output selecting section 11 for selecting a code output stage of a multi-stage shift register based on the specified code length. and is configured to extract an M-sequence code of a desired gradient length from a selected output stage. For this reason, the conventional method requires a code length designation section 10 and an output selection section 11, which increases the number of circuits and circuit wiring in the code generator, leading to a complicated circuit configuration and an increase in the cost of the device. There were disadvantages such as

<Object of the invention> The present invention achieves the following by changing the code extraction part.
) It is an object of the present invention to provide an M-sequence code generator that eliminates the need for a code length designation section and an output selection section, thereby simplifying the circuit configuration and reducing costs.

<Configuration and Effects of the Invention> In order to achieve efficient distribution, the present invention sets the feedback input section to the multi-stage shift register to the code extraction section, so that only the feedback value setting to the multi-stage shift register is possible. The configuration is such that an M-sequence code of a desired code length can be extracted.

According to the present invention, the code length specifying section and the output selecting section are no longer necessary, the number of circuits and wiring are reduced, the circuit configuration can be simplified, and the cost of the device can be reduced. It has a great effect.

<Description of Embodiments> FIG. 1 is a circuit block diagram of an M-sequence code generator according to the present invention, and FIG. 2 shows a specific example of the circuit.

In the illustrated example, the shrine number generation unit 1 includes a plurality of flip-flops.
It is constructed by combining a multistage shift register 2 formed by 11@order combinations of flops 21 to 27, and a feedback logic circuit 3 that feeds back the logical combination of each stage output in the multistage shift register 2 to the first stage flip-flop 21, In the present invention,
A code extractor 5 is set in the feedback input section to extract an M-sequence code having a code length (2°-1) corresponding to the number of stages n of the shift register 2. The feedback logic circuit 3 includes gate circuits 31 to 3 that input the outputs of each stage of the shift register 2.
7, and exclusive OR circuits 41 to 46 which input each gate output and a logical combination output from a subsequent stage, and each of the gate circuits 31 to 37 has its open/closed state determined by a feedback value setting unit 8 to be described later. is set.

The clock supply unit 6 supplies a clock of a predetermined frequency (for example, 3.2 NHZ) output from a crystal oscillator (not shown) to each of the flip-flops 21 to 27 of the shift register 2 via a gate circuit 61. The gate circuit 61
are controlled to open and close by the latch circuits 62 and 63, and the latch operation of each latch circuit 62 and 63 (in the illustrated example, the data bus I
).

is controlled by a start signal 11 and a stop signal I2.

The initial value setting unit 7 is a circuit for directly initializing each flip-flop 21N27 of the multi-stage shift register 2, and opens the buffers 71- and 72 with the initial set signal I3, and inputs the contents of the data buses Do to 1)6. is output to each of the flip-flops 21-27.

The feedback value setting unit 8 is a circuit for setting the calculation mechanism of the feedback logic circuit 3, in other words, the logical combination state of the outputs of each stage in the shift register 2, and uses the feedback tap signal I4 to set the data bus 1)o. ~1] The contents of 6 are transferred to latch circuit 8.
1, and the open/close states of each of the gate circuits 31 to 37 are determined based on the contents of this latch data.

] The operation of each part of the circuit described in 2 is controlled by the main control section 9 including a computer.
The main control unit 9 inputs each of the symbol signals 11 to I4 in iiJ and executes an M-sequence code generation process.

Now, if data bus Do is logic "1" and other data buses D1-1)6 are logic "o", initial set signal 13
buffer 71. , when the 72 gates are opened,
The shift register 2 is initialized based on the data contents of each data bus 1) θ to 1) 6, and the flip-flop 21
is logic "1", and the other flip-flops 22 to 27 are logic rOJ.

This becomes the output.

At the same time, data bus Do, ■) 5 is logic "1", data Ha: 7. DI-1) 4, D6 is the theory Fl OJ (7)
At this time, assuming that these data contents are set in the latch circuit 81 by the feedback tap signal -14, the feedback logic circuit 3 is such that the gate circuit 31.36 is "gate open" and the other gate circuits 32 to 35.37 are "gate open". The circuit state is set to "gate open".

Thus, when the start signal II is sent out in the state described in -1- and the logic "1" data of the data bus I)o is set in the latch circuit 8, the previous latch circuit 63 is set and the gate circuit 61 is released. This allows the clock to be applied to each of the flip-flops 21 to 2 of the shift register 2.
In this case, the code extractor 5 outputs the code length or 26-10M sequence code as "1111101010".
1100110111...'' is output 1lli times. In the conventional method in which the final output stage of a multi-stage shift register is used as a code extraction section, the code arrangement starts from the initial setting state r 000001111.10101
Q110011.0111...''.
Although a 6-bit phase difference occurs between the method and the method of the present invention,
Such a phase shift can be easily corrected using a program if necessary.

Thus, to stop code generation, the stop signal I2
As a result, the gate circuit 61 is closed via the latch circuits 62' and 63, and the clock supply to the shift register 2 is stopped. Also, the code length can be switched by the feedback value setting section 8.
This can be easily realized by obscuring the data contents to be latched.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an M-series code generator according to the present invention, FIG. 2 is an electrical wiring diagram showing an example of its specific circuit configuration, and FIG.
The figure is a block diagram of a conventional example. 1... Code generation section 2... Multi-stage shift register 3... Feedback logic circuit 5... Code extraction section 8... Feedback value setting section Patent applicant Tateishi Electric Co., Ltd.

Claims (1)

[Claims] It is equipped with a code generation section configured by a combination of a multi-stage shift register and a feedback logic circuit, and a feedback value setting section for setting a feedback input to the multi-stage shift register, and the feedback input section is provided with an M-sequence code. M-sequence code generator with extractor set.