JPH05233092A - Method and circuit for distributing clock signal - Google Patents

Abstract

PURPOSE:To prevent clock skew caused by phase deviation in the single phase clock signal distribution of a semiconductor integrated circuit. CONSTITUTION:Clock signals CLK from the outside are distributed by an inverter 11 as a buffer provided at the central part of a semiconductor chip 1 so as to be inputted the clock signals CLK from the outside, and a clock buffer composed of serially connected inverters constituting an inverter group, which has hierarchical structure while making equal the wiring width and wiring length of an output signal passage from this buffer inverter 11, and arranged at a previously decided position on the semiconductor chip 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution signal method and a distribution circuit, and more particularly to a clock signal distribution method and a distribution circuit for distributing a single-phase clock externally supplied to a semiconductor chip on the chip.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, one or more clock buffers are provided for each functional unit on a chip according to the circuit scale and the load capacity, and a clock input terminal is provided from the outside of the chip. The clock signal supplied to each functional block is supplied as a control signal to the circuit in each functional block via the clock buffer provided for each functional block.

FIG. 4 shows an example of a circuit arrangement in such a semiconductor integrated circuit chip. Referring to FIG. 4, this chip 1 has four functional units 2 _A , 2 _B , 2 _C , 2
_D is placed. A clock signal CLK necessary for controlling the operation as an integrated circuit is input from the outside of the chip to an inverter 4 as a buffer via a clock input terminal 3, and an output terminal of the inverter 4 causes each functional unit 2 to operate.
It is supplied to _A , 2 _B , 2 _C and 2 _D. In each functional unit, the supplied clock signal is received by the inverter 5 as a positive phase clock signal, and is supplied to the circuit in the functional block via the clock buffer composed of two stages of inverters.

_A D-type flip-flop (hereinafter referred to as a flip-flop) flip-flop 6 _A is provided in the functional unit 2 _A , and the functional unit 2 _B has the flip-flop 6 _B. These two flip-flops, the input signal IN is input to the data input of flip-flop 6 _A, the output signal QA from the flip-flop is inputted to the data input of flip-flop 6 _B, the flip-flop 6 _B Output Output signal OUT from the end
Are to be taken out. The two-stage inverter 7 is connected to the clock input terminal of the flip-flop 6 _A.
The clock signal is input through the clock buffer 8 _A composed of _A1 and 7 _A2 , and the flip-flop 6 _B is
The clock signal is input through the clock buffer 8 _{B including the} inverters 7 _B1 and 7 _B2 . In FIG. 4, the resistances R ₁ , R ₂ , R ₃ , R ₄ possessed by the signal wiring between the inverter 4 and the inverters in each functional unit are included.
And capacitances C ₁ , C ₂ , C ₃ , and C ₄ represent wiring resistance and wiring capacitance, respectively.

The operation of this semiconductor integrated circuit will be described below with reference to FIG. FIG. 5 is an operation timing chart of each signal in the flip-flop. Now, Fig. 5
Middle, at time T ₁ , the input signal IN to the flip-flop 6 _A is assumed to be at “H” level. At this time, the external clock signal CLK changes from "L" level to "H".
If rises, the output CB of the clock buffer 8 _B outputs CA and functional blocks 2 in _B clock buffer 8 _A in the functional unit 2 _A, respectively, changes from "L" level to the "H" level. At this time, flip-flop 6
_A uses the “H” level input signal IN as a data input,
After the internal delay time t ₂ of this flip-flop after the output CA of the clock buffer 8 _A becomes “H” level,
The output signal QA of "H" level is output. Then, even if the input signal IN changes to the "L" level after that, the output signal QA of the flip-flop 6 _A holds the "H" level. Next, in FIG. 5, at time T _2, when rises to "H" level from the clock signal CLK is again "L" level from the outside, an output CB of the output CA and the clock buffer 8 _B of the clock buffer 8 _A is Each changes from "L" level to "H". Flip-flop 6 at this time
_A uses the “L” level input signal IN as a data input,
After the internal delay time t _{2 of the} flip-flop after the output CA of the clock buffer 8 _A becomes “H” level,
The "L" level output signal QA is output and held.
On the other hand, flip-flop 6 _B is flip-flop 6 _A
And "H" level signal QA data input from the output signal CB of the clock buffer 8 _B from "H" to become a level after the internal delay time t ₂ of the flip-flop "H"
A level output signal OUT is output and this "H" level is held.

[0006]

In the semiconductor integrated circuit, since the clock signal gives each functional unit a time reference of operation, the phase timings of the clock signals do not match between the functional units. Then, there is a problem of so-called clock skew in which malfunction of the integrated circuit occurs due to the phase shift of the clock signal.

For example, in FIG. 4, when the external clock signal CLK rises to the "H" level at the time indicated by T ₁ in FIG. 5, the clock buffer 8 in the functional unit 2 _A is
Although rises in the output CB are both "H" level of the clock buffer 8 _B outputs CA and functional unit 2 in _B of _A, in this case, the wiring capacitance C ₃ in FIG. 4, C ₄ and the wiring resistance R _3, R ₄ As a result, the difference in delay time t ₁ = (C ₃ + C ₄ ) × (R ₃ + R ₄ ) due to the difference in time constant occurs between the rising edge of the signal CA and the rising edge of the signal CB, and Rises behind the signal CA. When the delay time difference t ₁ becomes t ₁ > t ₂ (t ₂ is the delay time in the flip-flop 6 _A ), the flip-flop 6 _B is turned on by the flip-flop 6 _{B as} shown by the broken line in FIG. When the output signal QA of the amplifier 6 _A is input, a signal OUT, which should originally have an “L” level, should be output at an incorrect “H” level.

Regarding the problem of clock skew caused by the phase difference of clock signals distributed on such a semiconductor chip, conventionally, the wiring width and the wiring length of the clock signal transmission path are made uniform, and the wiring capacitance and wiring are This is dealt with by designing so that the resistances are as equal as possible. However, in the conventional semiconductor integrated circuit, since the clock signal is distributed according to the arrangement of the functional units on the chip, the wiring of the clock signal distribution circuit is laid out on the chip according to the arrangement of the functional units. .. In other words, the wiring path for clock signal distribution is not constant because it depends on the arrangement of the functional units, and it cannot be standardized. Therefore, every time the arrangement of the functional units changes depending on the function or circuit type of the integrated circuit, the distribution circuit must be designed correspondingly. Moreover, in these designs, the propagation delay time of the clock signal is predicted by simulation, etc., but even in this case, it is difficult to eliminate experience at all, and several orders of trials are conducted to compare the simulation results with the trial results. The desired clock signal distribution must be achieved by repeating the above. As described above, the conventional clock signal distribution method and distribution circuit have a problem in that a large number of man-hours and labors are required for the design.

[0009]

According to the clock signal distribution method of the present invention, an external clock signal is input to a buffer provided on a semiconductor chip, and an output signal from this buffer is supplied to a wiring capacitance and a wiring resistance. The inverters are connected in cascade to form an inverter group having the same hierarchical structure, and are distributed by a clock buffer arranged at a predetermined position on the semiconductor chip.

The clock signal distribution circuit of the present invention is
A cascade connection that is provided in the center of the semiconductor chip and receives an external clock signal, and an inverter group that has a hierarchical structure while equalizing the wiring width and wiring length of the output signal path from this buffer Of the inverter, and a clock buffer arranged at a predetermined position on the semiconductor chip.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an arrangement of a clock distribution circuit according to a first embodiment of the present invention on a semiconductor integrated circuit chip. Note that the wiring resistance and the wiring capacitance are omitted in FIG. 1 for simplification. Referring to FIG. 1, in the present embodiment, an external clock signal CLK input to a clock input terminal 3 is passed through two stages of buffer inverters 9 and 10 to a buffer provided in the central portion of the chip 1. It is transmitted to the inverter 11. The clock signal CLK is not branched to any portion between the inverter 10 and the inverter 11, and is branched after passing through the inverter 11. The output terminals of the inverter 11 are wirings 12 _L and 12 _R having the same wiring resistance and the same wiring capacitance, and four inverters 13 _A , 13 _B , which have the same driving ability,
It is connected to the input terminals of 13 _C and 13 _D. The output terminals of these four inverters are connected to the wirings 14 _RU , 14 _RD , 14 _LU , 1 having the same wiring resistance and the same wiring capacitance.
4 _LDs with 4 inverters 15 _A , 15 _B , 15 _C , 15
It is connected to the input terminal of _D. Further, the output terminals of the four inverters are connected to the inverters 16 _Aa , 16 _Ab , 16 _Ab by the wirings having the same wiring resistance and the same wiring capacitance.
_Ac , 16 _Ad , inverter 16 _Be , 16 _Bf , 16 _Bg , 16
_Bh , inverters 16 _Ci , 16 _Cj , 16 _Ck , 16 _Cl , and inverters 16 _Dm , 16 _Dn , 16 _Dp , 16 _Dq are connected to the input ends thereof. By repeating such a configuration, the external clock signal CLK is hierarchically divided according to the size of the chip,
Distributed and supplied. In this embodiment having such a configuration, when the external clock signal CLK becomes “H” level,
The outputs a to q of the final stage inverters simultaneously become "H" level, and the external clock signal CLK becomes "L".
When it goes to the level, the output of the last stage goes to "L" level at the same time. Since the wiring resistance and the wiring capacitance are all the same in the signal paths from the clock input terminal 3 to the respective output terminals of the final-stage inverter, the signal due to the time constant difference due to the difference in the wiring resistance and the wiring capacitance. There is no difference in propagation delay time and no clock skew occurs.

In the above-described first embodiment, the clock input terminal 3 is provided substantially at the center of one side of the chip 1, and the two-stage inverters 9 and 10 as buffers are provided near the clock input terminal 3. Although the example has been described, the clock input terminal 3 is arranged in the corner of the chip 1 and the inverters 9 and 10 are arranged in the central portion of the chip as in the second embodiment shown in FIG. Even if the inverter 11 in the example is replaced, the same effect as that of the first embodiment can be obtained. As described above, the present invention is not limited to the input position of the external clock signal, the position of the input buffer, or the positive phase clock or the negative phase clock.

Further, in the first and second embodiments, the example in which the clock signal CLK from the outside is directly led to the inverter provided near the center of the chip and then distributed is shown, but it is shown in FIG. As in the case of the third embodiment, it is possible to distribute by the wiring along the side of the chip provided with the clock input terminal. Referring to FIG. 3, in the present embodiment, the clock signal CLK from the outside is input to the inverter 4 provided near the clock input terminal 3.
The output of the inverter 4 is guided in the horizontal direction in the drawing by the wiring 17 along the side of the chip on which the clock input terminal 3 is provided. This wiring 17 in the horizontal direction is branched in the vertical direction in the figure on the way. The clock signal CLK is
It is transmitted to the inside of the chip via a two-stage inverter provided in the middle of this vertical wiring. In this example,
By repeating such branching, externally supplied clock signals are distributed hierarchically on the chip. In the present embodiment, unlike the first and second embodiments, it is not necessary to introduce an external clock signal to the inverter as a buffer provided near the center of the chip, so that the circuit on the chip There is an advantage that the degree of freedom in arrangement is increased. in this case,
Since the wiring length from the clock input terminal 3 to the output terminal of the final stage inverter is different, if the wiring width is the same, the wiring resistance and the wiring capacitance will not be the same, and the signal propagation delay time will be different. .. Therefore, the wiring length, wiring width, wiring material, etc. must be designed so that the propagation delay times are equal. In this case, in the conventional clock distribution circuit, the wiring from the clock input terminal to the clock buffer in each functional unit must be randomly laid out according to the arrangement of the functional units. Every time the layout of the functional unit on the chip changes, it is necessary to re-simulate and design the clock distribution circuit. On the other hand, in this embodiment, since the clock signal distribution buffer is arranged at a predetermined position on the chip, the wiring can be standardized by giving regularity to this arrangement. Therefore, even if there is a change in the circuit configuration of the integrated circuit or the layout of the functional units, there is no need to change the design of the clock signal distribution circuit, and even if the change is made, the signal propagation delay time will be more accurate than before by simulation. It is easy to predict.

[0014]

As described above, according to the present invention, the clock signal from the outside is input to the buffer provided on the semiconductor chip, and the output signal from this buffer is made equal in wiring capacitance and wiring resistance. The inverters are connected in cascade to form an inverter group having a hierarchical structure, and are distributed by clock buffers arranged at predetermined positions on the semiconductor chip.

As a result, according to the present invention, even if the circuit configuration of the integrated circuit or the arrangement of the functional units on the chip is changed, it is not necessary to re-simulate or design the clock distribution circuit. Further, even when changing, it becomes very easy to accurately predict the signal propagation delay time by simulation. This is a great advantage for facilitating the design of the clock signal distribution circuit and reducing the design man-hours under the circumstances where the semiconductor integrated circuit becomes large in scale and various functions are required in recent years. Is.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an example of a conventional clock signal distribution circuit.

5 is a diagram showing operation timings of signals in the clock distribution circuit shown in FIG.

[Explanation of symbols]

1 chip 2A, 2B, 2C, 2D functional unit 3 clock signal input terminal 6A, 6B flip-flop 8A, 8B clock buffer 12L, 12R, 14LU, 14LD, 14RU, 14RD, 1
7 wiring

Claims (2)

[Claims] 1. An inverter group in which a clock signal from the outside is input to a buffer provided on a semiconductor chip, and an output signal from this buffer has a hierarchical structure by equalizing wiring capacitance and wiring resistance. A clock signal distribution method comprising: a serially connected inverter, and distributing by a clock buffer arranged at a predetermined position on a semiconductor chip. 2. A buffer provided in the central portion of a semiconductor chip to which a clock signal from the outside is input, and an inverter group having a hierarchical structure while equalizing the wiring width and wiring length of an output signal path from this buffer. And a clock buffer arranged at a predetermined position on a semiconductor chip, the clock signal distributing circuit.